SCG4500-155.52M

SCG4500 Series Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com Features • Phase Locked Output Frequency Control • Intrinsically Low Jitter Crystal Oscillator • LVPECL Outputs with Disable Function • Dual Input References • LOR & LOL combined alarm output • Force Free Run Function • Automatic Free Run operation on loss of both References A & B • Input Duty Cycle Tolerant • 3.3V dc Power Supply Bulletin Page Revision Date Issued By SG026 1 of 16 P08 08 Oct 02 MBatts • Small Size: 1 Square Inch General Description Maximum Dimension Package Outline The SCG4500 Series is a mixed-signal phase locked loop generating LVPECL outputs from an intrinsically low jitter, voltage controlled, crystal oscillator. The LVPECL outputs may be disabled. The SCG4500 Series can lock to one of two external references, which is selectable using the SELAB input select pin. The unit has a fast acquisition time of about 1.5 seconds and it is tolerant of different reference duty cycles. The SCG4500 Series includes an alarm output that indicates deviations from normal operation. If a Lossof-Reference (LOR) or Loss-of-Lock (LOL) is detected the alarm with indicate the need for a reference rearrangement. If both references A and B are absent the module will enter Free Run operation. The FRstatus pin will indicate that the module is in Free Run operation. Frequency stability during Free Run operation is guaranteed to ±20 ppm. Additionally the Free Run mode may be entered manually. The package dimensions are 1” x 1.025” x .45” on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloys, 180°C surface mount reflow processes. Figure 1 Block Diagram Figure 2 10 kΩ FREE RUN STATUS FORCE FREE RUN 10 kΩ ALARM 33 Ω Q REFA REFB 8 KHz PHASE ALIGNER 33 Ω DPFD LOW JITTER ANALOG FILTER VCXO QN 1/N SEL AB 10 kΩ OPTIONAL REFERENCE OUTPUT 33 Ω ENABLE/ TRI-STATE 10 kΩ Model Comparison Table Table 1 Dual Input Ref Freq Max Duty Cycle LVPECL Oscillator Output (Pins 16 & 18) Notes SCG4500 8 kHz/8 kHz 40/60 77.76 MHz,155.52 MHz,125 MHz Basic Model SCG4510 1.544MHz/1.544MHz 40/60 155.52 MHz SCG4520 19.44 MHz/19.44 MHz 40/60 77.76 MHz,155.52 MHz Model *Features which differentiate a model from the base model (SCG4500) are highlighted in boldface color and in the notes column. Preliminary Data Sheet #: SG026 Page 2 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Absolute Maximum Rating Table 1 All SCG4500 Models Symbol Parameter Minimum Nominal Maximum Units Notes Vcc Power Supply Voltage -0.5 - +4.0 Volts 1.0 Vi Input Voltage -0.5 - +5.5 Volts 1.0 Ts Storage Temperature -65.0 - +100 °C 1.0 Operating Specifications Table 2 All SCG4500 Models Symbol Parameter Minimum Nominal Maximum Units Notes Vcc Power Supply Voltage 3.135 3.3 3.465 Volts 2.0 Icc Power Supply Current 170 230 280 mA 5.0 To Temperature Range 0 - 70 °C Ffr Free Run Frequency -20 - 20 ppm Fcap Capture/pull-in range -25 - 25 ppm Fbw Jitter Filter Bandwidth - - 10 Hz 3.0 Tjtol Input Jitter Tolerance 31.25 1 - - µs µs 8 kHz Ref. units 19.44 MHz Ref. units (Input Jitter Frequencies ≥ 10 Hz) Taq Acquisition Time - 1 - s 4.0 Trf Output Rise and Fall Time (20% 80%) 100 225 350 ps 5.0 DC Output Duty Cycle 40 50 60 % MTIEsr MTIE at Synchronization Rearrangement GR-253-CORE.1999 R5-136 6.0, 7.0 Dynamic Offset Range (0°- 25°) -50 - 50 ns Dynamic Offset Range (25°- 70°) -50 - 50 ns Output Jitter Specifications Table 4 Frequency (MHz) All SCG4500 Models Jitter BW 10 Hz - 1 MHz pS (RMS) m UI SONET Jitter BW 12 kHz - 20 MHz pS (RMS) m UI 77.76 10 Typ. 0.776 Typ. 1 Max. 0.076 Max. 125.00 10 Typ. 1.250 Typ. 1 Max. 0.125 Max. 155.52 10 Typ. 1.556 Typ. 1 Max. 0.156 Max. NOTES: 1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. 2.0 Requires external regulation and supply decoupling. (22 uF, 330 pF) 3.0 3db loop response. 4.0 From a 20 PPM step in reference frequency at 25°C @ 3.3V 5.0 50-ohm load biased to 1.3 volts. 6.0 Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing. 7.0 If the selected reference is removed system response to the ALARM must be less than 10µs. Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 3 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Input And Output Characteristics Table 3 Symbol All SCG4500 Models Parameter Minimum Nominal Maximum Units CMOS Input and Output Characteristics Vih High Level Input Voltage 2.0 - 5.5 V Vil Low Level Input Voltage 0.0 - 0.8 V Tio I/O to Output Valid - - 10 ns Cl Output Capacitance - - 10 pF Voh High Level Output Voltage 2.4 - - V Vol Low Level Output Voltage - - 0.4 V Tir Input Reference Pulse Width 12.5 - - ns 2.27 2.34 2.52 V PECL Output Characteristics Voh High Level PECL Voltage Vol Low Level PECL Voltage 1.49 1.51 1.68 V Cl Output Capacitance - - 10 pF Tskew Differential Output Skew - 50 - ps Notes Input Selection / Output Response Table 4 All SCG4500 Models ENABLE SELAB INPUTS REFA REFB FR FRstatus OUTPUTS ALARM Q QN 1 0 X X X X 1 X X X X 1 X X X X X X 0 1 0 0 X X X 1 1 X X X FR 0 0 0 A A 0 0 0 X X RA 0 0 1 A A 0 0 0 X X RB 0 0 0 NA A 0 0 1 X X U 0 0 1 NA A 0 0 0 X X RB 0 0 1 A NA 0 0 1 X X U 0 0 0 A NA 0 0 0 X X RA 0 0 X NA NA 0 1 1 X X FR RESET NOTE FR NOTES: A Active FR Free Run Mode NA Not Active RA Locked to Reference A RB Locked to Reference B U Unstable (due to conditions shown, switch to active reference or Free Run) X Don’t care Preliminary Data Sheet #: SG026 Page 4 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Typical MTIE Measurement Figure 3 Typical TDEV Measurement Figure 4 Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 5 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Typical MTIE at Synchronization Rearrangement. Reference B Equal to Inverse of Reference A, No Modulation. Figure 5 Preliminary Data Sheet #: SG026 Page 6 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Pin Description Table 5 Pin # All SCG4500 Models Pin Name Pin Information Note 1 ENABLE/TRI-STATE VCXO Enable. (Enable = 0, Disable = 1 = CMOS Outputs Tri-stated) 9.0 2 TCK No Connection, Internal Factory Programming Input. 8.0 3 TDO No Connection, Internal Factory Programming Input. 8.0 4 REFA CMOS Reference Frequency Input. 5 SELAB Input Reference Select Pin. (REFA = 0, REFB = 1) 9.0 6 RESET RESET. (RESET = 1) 9.0 7 REFB CMOS Reference Frequency Input. 8 Vee Ground. 9 FRstatus Free Run Status. (FR = 1) 10 Vcc Supply Voltage relative to ground. 11 N/C No Connection. (Optional Reference Output Available) 12 ALARM Loss of Reference / Lock alarm. (Alarm = 1) 13 FR Force Free Run. (Phase Lock = 0, Free Run = 1) 9.0 14 TDI No Connection, Internal Factory Programming Input. 8.0 15 TMS No Connection, Internal Factory Programming Input. 8.0 16 QN LVPECL Complementary Output. 17 Vee Ground. 18 Q LVPECL Output. 8.0, 8.1 NOTES 8.0 Do not connect pin 8.1 Contact a Sales Representative for availibilty and use of optional reference output 9.0 Input pulled to ground Circuit Board Footprint & Keepout Recommendations Figure 6 0.8650 [21.97 mm] 0.0650 [1.65 mm] 1.0400 [26.42 mm] 0.8400 [21.34 mm] 0.1000 [2.54 mm] Keep Out Area 0.1000 [2.54 mm] 0.0350 [0.89 mm] 1.0700 [27.18 mm] Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 7 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Loss of Reference Condition Alarm Timing Figure 7 Start-up Region Alarm Output (LOR + LOL) LOR (Internal Signal) 4 LOL (Internal Signal) 2 1 Phase Detector (Internal Signal) 3 1 External Reference (Selected Input A or B) Internal Reference (Internal Signal) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 AlarmTiming Legend Use for all alarm timing diagrams Table 6 19.44 MHz Reference Input Units 1 2 3 4 5 Start-up Region 8 kHz Reference Input Units < 31.25 µsec < 1 µsec 1 µsec 31.25 µsec > 1 µsec > 31.25 µsec 125 µsec wide range LOR is active when LOL is active Minimum pulse width = 2 µsec Minimum pulse width = 62.5 µsec During Start-up, The LOL Alaram will pulse during the few seconds of operation Preliminary Data Sheet #: SG026 Page 8 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Loss of Lock Condition Alarm Timing Figure 8 Alarm Output (LOR + LOL) LOR (Internal Signal) LOL (Internal Signal) Phase Detector (Internal Signal) 5 1 1 1 3 1 1 3 External Reference (Selected Input A or B) Internal Reference (Internal Signal) 2 2 2 2 2 2 2 2 Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. 2 2 Page 9 of 16 2 2 Rev: P08 2 2 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Switch from A to B when both are good signals Figure 9 Ref A Ref B LOL portion of Alarm is Blanked Alarm 0.5 sec Sel A/B New Reference Qualification time Switch from A to B when Reference B is lost Figure 10 Ref A Ref B ~8ns Alarm Sel A/B Preliminary Data Sheet #: SG026 Page 10 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Switch from A to B after Reference A is lost Figure 11 Ref A Ref B Alarm Blanked Alarm Sel A/B 156.25µs (8 kHz Ref units) 126µs (19.44 MHz Ref units) New Reference Qualification time Switch from A to B when A is out of range Figure 12 Ref A Out of Range Ref B In Range Alarm Blanked Alarm Sel A/B New Reference Qualification time Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 11 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Switch from A to B when B is out of range Figure 13 Switch from A to B when B is out of range Ref A In Range Ref B Out of Range Alarm Blanked Alarm SEL A/B New Reference Qualification Time 0.5 sec. Switch from A to B when B is out of range Figure 14 Ref A Ref B Alarm Blanked Alarm Sel A/B New Reference Qualification time Free Run Status Preliminary Data Sheet #: SG026 Page 12 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Recommended PECL Termination Figure 15 3.3 VDC 3.3 VDC 3.3 VDC 130 82 Vcc Vcc Q D 50 OHM Transmission Line SCGxxx LVPECL OUTPUT LVPECL INPUT QN DN 50 OHM Transmission Line GND GND 130 82 3.3 VDC 3.3 VDC Vcc - 2 VDC 3.3 VDC 50 Vcc Vcc Q D 50 OHM Transmission Line SCGxxx LVPECL OUTPUT LVPECL INPUT QN DN 50 OHM Transmission Line GND GND 50 Vcc - 2 VDC 3.3 VDC 3.3 VDC 150 Vcc Vcc Q 50 SCGxxx LVPECL OUTPUT D 50 OHM Transmission Line LVPECL INPUT 100 50 QN DN 50 OHM Transmission Line GND GND 150 If PECL outputs do not drive a long line (< 0.5”), a single 150Ω termination resistor to ground may be used for each pin. Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 13 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Tape and Reel Packaging Figure 16 Preliminary Data Sheet #: SG026 Page 14 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Solder Profile Figure 17 250 200 Temp (C˚) 150 100 50 0 1 2 3 4 5 6 7 8 Time(minutes) Recommended Reflow Profile Peak Temp:217C˚ MaxRiseSlope:1.5 C˚/Sec Time Above150C˚:100Sec Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 15 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Revision Revision Date Note P00 03/26/01 Preliminary informational release P01 06/20/01 Added new products to Table 1 P02 07/10/01 Added new frequency to SCG4500 P03 07/30/01 Added new frequency to SCG4520 P04 09/06/01 Corrected mech. drawing and supply current P05 10/18/01 Added 77.76 MHZ to SCG4500 model P06 02/19/02 Changed dimension to maximums P07 03/20/02 Updated alarm diagrams P08 10/08/02 Revised mech. dimensions and drawings