SCG4500

SCG4500 Series Synchronous Clock Generators P LL 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com Features • Phase Locked Output Frequency Control • Intrinsically Low Jitter Crystal Oscillator • LVPECL Outputs with Disable Function • Dual Input References • LOR & LOL combined alarm output • Force Free Run Function • Automatic Free Run operation on loss of both References A & B • Input Duty Cycle Tolerant • 3.3V dc Power Supply Bulletin Page Revision Date Issued By SG026 1 of 16 P08 08 Oct 02 MBatts • Small Size: 1 Square Inch General Description The SCG4500 Series is a mixed-signal phase locked loop generating LVPECL outputs from an intrinsically low jitter, voltage controlled, crystal oscillator. The LVPECL outputs may be disabled. The SCG4500 Series can lock to one of two external references, which is selectable using the SELAB input select pin. The unit has a fast acquisition time of about 1.5 seconds and it is tolerant of different reference duty cycles. The SCG4500 Series includes an alarm output that indicates deviations from normal operation. If a Lossof-Reference (LOR) or Loss-of-Lock (LOL) is detected the alarm with indicate the need for a reference rearrangement. If both references A and B are absent the module will enter Free Run operation. The FRstatus pin will indicate that the module is in Free Run operation. Frequency stability during Free Run operation is guaranteed to ±20 ppm. Additionally the Free Run mode may be entered manually. The package dimensions are 1” x 1.025” x .45” on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloys, 180°C surface mount reflow processes. Maximum Dimension Package Outline Figure 1 Block Diagram Figure 2 10 kΩ FREE RUN STATUS 10 kΩ FORCE FREE RUN 33 Ω ALARM Q 33 Ω REFA REFB 8 KHz PHASE ALIGNER DPFD ANALOG FILTER LOW JITTER VCXO QN SEL AB 10 kΩ 1/N 33 Ω OPTIONAL REFERENCE OUTPUT ENABLE/ TRI-STATE 10 kΩ Model Comparison Table Table 1 Model SCG4500 SCG4510 SCG4520 Dual Input Ref Freq 8 kHz/8 kHz 1.544MHz/1.544MHz 19.44 MHz/19.44 MHz Max Duty Cycle 40/60 40/60 40/60 LVPECL Oscillator Output (Pins 16 & 18) 77.76 MHz,155.52 MHz,125 MHz 155.52 MHz 77.76 MHz,155.52 MHz Notes Basic Model *Features which differentiate a model from the base model (SCG4500) are highlighted in boldface color and in the notes column. Preliminary Data Sheet #: SG026 Page 2 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Absolute Maximum Rating Table 1 Symbol Vcc Vi Ts Parameter Power Supply Voltage Input Voltage Storage Temperature All SCG4500 Models Minimum -0.5 -0.5 -65.0 Nominal Maximum +4.0 +5.5 +100 Units Volts Volts °C Notes 1.0 1.0 1.0 Operating Specifications Table 2 Symbol Vcc Icc To Ffr Fcap Fbw Tjtol Taq Trf DC MTIEsr Parameter Power Supply Voltage Power Supply Current Temperature Range Free Run Frequency Capture/pull-in range Jitter Filter Bandwidth Input Jitter Tolerance (Input Jitter Frequencies ≥ 10 Hz) All SCG4500 Models Minimum 3.135 170 0 -20 -25 31.25 1 100 40 -50 -50 Nominal 3.3 230 1 225 50 Maximum 3.465 280 70 20 25 10 350 60 50 50 Units Volts mA °C ppm ppm Hz µs µs s ps % 6.0, 7.0 ns ns 3.0 8 kHz Ref. units 19.44 MHz Ref. units 4.0 5.0 Notes 2.0 5.0 Acquisition Time Output Rise and Fall Time (20% 80%) Output Duty Cycle MTIE at Synchronization Rearrangement Dynamic Offset Range (0°- 25°) Dynamic Offset Range (25°- 70°) GR-253-CORE.1999 R5-136 Output Jitter Specifications Table 4 Frequency (MHz) 77.76 125.00 155.52 All SCG4500 Models Jitter BW 10 Hz - 1 MHz pS (RMS) m UI 10 Typ. 10 Typ. 10 Typ. 0.776 Typ. 1.250 Typ. 1.556 Typ. SONET Jitter BW 12 kHz - 20 MHz pS (RMS) m UI 1 Max. 1 Max. 1 Max. 0.076 Max. 0.125 Max. 0.156 Max. NOTES: 1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. 2.0 Requires external regulation and supply decoupling. (22 uF, 330 pF) 3.0 3db loop response. 4.0 From a 20 PPM step in reference frequency at 25°C @ 3.3V 5.0 50-ohm load biased to 1.3 volts. 6.0 Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing. 7.0 If the selected reference is removed system response to the ALARM must be less than 10µs. Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 3 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Input And Output Characteristics Table 3 Symbol Parameter CMOS Input and Output Characteristics Vih High Level Input Voltage Vil Tio Cl Voh Vol Tir Low Level Input Voltage I/O to Output Valid Output Capacitance High Level Output Voltage Low Level Output Voltage Input Reference Pulse Width All SCG4500 Models Minimum 2.0 0.0 2.4 12.5 2.27 1.49 Nominal 2.34 1.51 50 Maximum 5.5 0.8 10 10 0.4 2.52 1.68 10 Units V V ns pF V V ns V V pF ps Notes PECL Output Characteristics Voh High Level PECL Voltage Vol Cl Tskew Low Level PECL Voltage Output Capacitance Differential Output Skew Input Selection / Output Response Table 4 RESET 1 X 0 0 0 0 0 0 0 0 ENABLE 0 1 0 0 0 0 0 0 0 0 SELAB X X X 0 1 0 1 1 0 X INPUTS REFA X X X A A NA NA A A NA REFB X X X A A A A NA NA NA All SCG4500 Models FR X X 1 0 0 0 0 0 0 0 FRstatus 1 X 1 0 0 0 0 0 0 1 OUTPUTS ALARM X X X 0 0 1 0 1 0 1 NOTE Q X 0 X X X X X X X X QN X 1 X X X X X X X X FR RA RB U RB U RA FR FR NOTES: A Active FR Free Run Mode NA Not Active RA Locked to Reference A RB Locked to Reference B U Unstable (due to conditions shown, switch to active reference or Free Run) X Don’t care Preliminary Data Sheet #: SG026 Page 4 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Typical MTIE Measurement Figure 3 Typical TDEV Measurement Figure 4 Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 5 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Typical MTIE at Synchronization Rearrangement. Reference B Equal to Inverse of Reference A, No Modulation. Figure 5 Preliminary Data Sheet #: SG026 Page 6 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Pin Description Table 5 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin Name ENABLE/TRI-STATE TCK TDO REFA SELAB RESET REFB Vee FRstatus Vcc N/C ALARM FR TDI TMS QN Vee Q All SCG4500 Models Pin Information VCXO Enable. (Enable = 0, Disable = 1 = CMOS Outputs Tri-stated) No Connection, Internal Factory Programming Input. No Connection, Internal Factory Programming Input. CMOS Reference Frequency Input. Input Reference Select Pin. (REFA = 0, REFB = 1) RESET. (RESET = 1) CMOS Reference Frequency Input. Ground. Free Run Status. (FR = 1) Supply Voltage relative to ground. No Connection. (Optional Reference Output Available) Loss of Reference / Lock alarm. (Alarm = 1) Force Free Run. (Phase Lock = 0, Free Run = 1) No Connection, Internal Factory Programming Input. No Connection, Internal Factory Programming Input. LVPECL Complementary Output. Ground. LVPECL Output. 9.0 8.0 8.0 8.0, 8.1 9.0 9.0 Note 9.0 8.0 8.0 NOTES 8.0 Do not connect pin 8.1 Contact a Sales Representative for availibilty and use of optional reference output 9.0 Input pulled to ground Circuit Board Footprint & Keepout Recommendations Figure 6 0.8650 [21.97 mm] 0.0650 [1.65 mm] 1.0400 [26.42 mm] 0.8400 [21.34 mm] Keep Out Area 0.1000 [2.54 mm] 0.1000 [2.54 mm] 0.0350 [0.89 mm] 1.0700 [27.18 mm] Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 7 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Loss of Reference Condition Alarm Timing Figure 7 Start-up Region Alarm Output (LOR + LOL) LOR (Internal Signal) 4 LOL (Internal Signal) 2 3 Phase Detector (Internal Signal) 1 1 External Reference (Selected Input A or B) Internal Reference (Internal Signal) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 AlarmTiming Legend Use for all alarm timing diagrams Table 6 19.44 MHz Reference Input Units 8 kHz Reference Input Units < 31.25 µsec 31.25 µsec > 31.25 µsec 125 µsec wide range Minimum pulse width = 62.5 µsec 1 2 3 4 5 Start-up Region < 1 µsec 1 µsec > 1 µsec LOR is active when LOL is active Minimum pulse width = 2 µsec During Start-up, The LOL Alaram will pulse during the few seconds of operation Preliminary Data Sheet #: SG026 Page 8 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Loss of Lock Condition Alarm Timing Figure 8 Alarm Output (LOR + LOL) LOR (Internal Signal) LOL (Internal Signal) 5 Phase Detector (Internal Signal) 1 1 3 3 1 1 1 External Reference (Selected Input A or B) Internal Reference (Internal Signal) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 9 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Switch from A to B when both are good signals Figure 9 Ref A Ref B Alarm LOL portion of Alarm is Blanked 0.5 sec Sel A/B New Reference Qualification time Switch from A to B when Reference B is lost Figure 10 Ref A Ref B ~8ns Alarm Sel A/B Preliminary Data Sheet #: SG026 Page 10 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Switch from A to B after Reference A is lost Figure 11 Ref A Ref B Alarm 156.25µs (8 kHz Ref units) 126µs (19.44 MHz Ref units) Alarm Blanked Sel A/B New Reference Qualification time Switch from A to B when A is out of range Figure 12 Ref A Ref B Alarm Alarm Blanked Out of Range In Range Sel A/B New Reference Qualification time Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 11 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Switch from A to B when B is out of range Figure 13 Switch from A to B when B is out of range Ref A Ref B Alarm Alarm Blanked In Range Out of Range SEL A/B New Reference Qualification Time 0.5 sec. Switch from A to B when B is out of range Figure 14 Ref A Ref B Alarm Alarm Blanked Sel A/B New Reference Qualification time Free Run Status Preliminary Data Sheet #: SG026 Page 12 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Recommended PECL Termination Figure 15 3.3 VDC 3.3 VDC 3.3 VDC 130 Vcc Q 82 Vcc D SCGxxx LVPECL OUTPUT QN GND 50 OHM Transmission Line LVPECL INPUT 50 OHM Transmission Line 130 82 DN GND 3.3 VDC 3.3 VDC Vcc - 2 VDC 3.3 VDC 50 Vcc Q Vcc D SCGxxx LVPECL OUTPUT QN GND 50 OHM Transmission Line LVPECL INPUT 50 OHM Transmission Line 50 DN GND Vcc - 2 VDC 3.3 VDC 3.3 VDC 150 Vcc Q Vcc 50 D SCGxxx LVPECL OUTPUT QN GND 150 50 OHM Transmission Line 100 LVPECL INPUT DN GND 50 50 OHM Transmission Line If PECL outputs do not drive a long line (< 0.5”), a single 150Ω termination resistor to ground may be used for each pin. Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 13 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Tape and Reel Packaging Figure 16 Preliminary Data Sheet #: SG026 Page 14 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Solder Profile Figure 17 250 200 Temp (C˚) 150 100 50 0 1 2 3 4 5 6 7 8 Time(minutes) Recommended Reflow Profile Peak Temp:217C˚ MaxRiseSlope:1.5 C˚/Sec Time Above150C˚:100Sec Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 15 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Revision P00 P01 P02 P03 P04 P05 P06 P07 P08 Revision Date 03/26/01 06/20/01 07/10/01 07/30/01 09/06/01 10/18/01 02/19/02 03/20/02 10/08/02 Note Preliminary informational release Added new products to Table 1 Added new frequency to SCG4500 Added new frequency to SCG4520 Corrected mech. drawing and supply current Added 77.76 MHZ to SCG4500 model Changed dimension to maximums Updated alarm diagrams Revised mech. dimensions and drawings