STM-S3E

Stratum 3E Timing Module (STM-S3E) 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Features • Dual Input References • Hitless Switch Over • 1.544 MHz -38.88 MHz • 8 kHz Output • 12 ppb Composite Hold Over Mode • Fast Acquisition Mode • Hold Over Good Indicator • Phase Buildout Indicator • LOR Alarms • Reference Frequency Limit Alarm Application The Connor-Winfield Stratum 3E Simplified Control Timing Module acts as a complete system clock module for Stratum 3E timing applications in accordance with GR-1244CORE, Issue 2, GR-253-CORE, Issue 3, and ITU-T G.812, Option ΙΙΙ. Connor-Winfield’s Stratum 3E Timing module helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design. Bulletin Page Revision Date Issued By TM012 1 of 16 P06 20 MAY 02 MBATTS General Description Connor-Winfield’s STM-S3E timing module provides Stratum 3E synchronization for a complete system clock solution in a single module in accordance with GR-1244CORE Issue 2, GR-253-CORE Issue 3, and ITU-T G.812 Option III. The STM-S3E provides a reliable network element clock reference to line cards used in TDM, PDH, SONET, and SDH application environments. Typical applications include digital cross talks, DSLAMs, ADMs, multiservice platforms, switches and routers. The STM-S3E meets 12 ppb Hold Over requirements over 0° – 70°C temperature range. The 5V power requirement will draw a maximum of 1.2 A during an initial start-up period and then drop to a typical current of 800 mA during normal operating conditions. It accepts two 8 kHz input references and can be manufactured to supply a fixed frequency from 1.544 MHz to 38.88 MHz. The STM-S3E offers 4 user selectable modes of operation, Reference 1, Reference 2, Hold Over and Free Run. Mode of operation is selected by two control pins (Table 6). The current mode of operation is also indicated by two status pins (Table 7). Free Run is the default mode if no control signals are asserted on the control pins. Reference 1 mode and Reference 2 mode are the two primary operating modes. When the module is locked to a valid reference, any time after initial power up or reset, the module is considered to be in the normal operating mode. During normal operation the output frequency is phase locked to the input reference frequency. The offset between the input and output is dependant upon the amount of noise that is present on the reference signal. For input tolerances, refer to Table 4. Hold Over mode provides a stable frequency that is guaranteed to be within ±0.012 ppm over the entire temperature range for the first 24 hours after entry into Hold Over. Hold Over is valid 701 seconds after a reference is selected and continues to do a running average every 8 seconds for the next 1049 seconds. Long-term Hold Over values are based on a 1049 second moving window average. Hold Over values are not updated during LOR or during Fast Acquisition mode. Hold Over values are buffered for at least 32 seconds to allow enough time to respond to the RFL alarm. Free Run is a mode of operation in which the module is not locked to a reference and its output frequency is solely dependent on the initial frequency setting of the internal oscillator. The output frequency in Free Run is guaranteed to be ±4.6ppm of the nominal frequency. A fifth, automatic mode of operation is Fast Acquisition mode. Fast Acquisition mode is entered whenever Reference 1 or 2 has been selected. After a new reference has been selected, the module uses internal filtering that limits the frequency movement to less than 2.9 ppm/sec. By 600 seconds the module switches to a slower 0.001Hz filter. While in normal mode, if the phase error is greater than 20 µs, Fast Acquisition mode will be initiated. Fast Acquisition mode is further described as fast start mode in GR-1244CORE, Issue 3, sec 3.6. The STM-S3E may be reset by asserting a logic low signal to the Reset pin or cycling the power. Using the Reset pin for a manual reset is the recommend method for resetting the module. Resetting the module by cycling the power requires more time due to the restablization of the internal ovenized oscillator. The STM-S3E provides the user with non-interruptive TriState capabilities. By asserting a logic high signal to the TriState pin, the user is able to Tri-State all outputs. While in Tri-State, the module continues normal operations and accepts all normal inputs. When the module is released from Tri-State, all output signals are valid. The STM-S3E module provides three output frequencies. The Sync_Out is the primary synchronized output. It is phase locked to the input reference during normal operation and is set to a fixed frequency when operating in Hold Over or Free Run. Clock_Out provides a frequency output that comes from an independent, undisciplined, free running oscillator that is ±4.6 ppm from the nominal frequency. This output is typically used for reference frequency qualification. The 8 kHz output is derived from the Sync_Out output. The STM-S3E module provides a variety of alarm indicators to alert the user to multiple conditions that may affect the overall performance of their system. The LOR (Loss of Reference) alarm indicates that the active reference has been lost. RFL (Reference Frequency Limit) indicates that the Sync_Out frequency is 15 ppm or more from the Free Run frequency. The PBO (Phase Build Out) pin indicates that a phase transient greater than 3.4 µs over any 0.1 second interval has occurred. The PBO indicator will remain high as long as the phase transient condition exists. The Mode Alarm pin is used to indicate that the module is not in a normal operating mode. Conditions that will cause the Mode Alarm to go high are Hold Over, Free Run, Fast Acquisition Modes or when Phase Build Out has been active for more than 0.4 seconds. During the latter condition, both the Mode Alarm indicator and the PBO indicator will be high. See Table 8 for a full description of input control pins and output indicator pins. The Hold Over Good pin indicates that an initial average has been acquired to provide a qualified Hold Over frequency. The module requires approximately 700 seconds from any reference switch or mode switch to a new reference to reacquire a valid average before the indicator goes high (Fig. 17). Initially, entry into Hold Over prior to this will result in a Free Run frequency. After the first Hold Over Good indication, entry into Hold Over will be the last valid Hold Over frequency. The STM-S3E meets the requirements for wander generation and wander transfer as required by GR-1244, sections 5.3 and 5.4. Figures 4, 5 and 6 show typical results. It also complies with phase transient requirements during Reference Rearrangement, Entry into Hold Over, and 1 µs transient. See figures 7-9 for typical performance results and requirement masks. Input jitter is attenuated at about 20 dB/ decade to minimize jitter noise from being passed to other network elements or clocks. Figure 10 illustrates the STMS3E’s typical roll off of attenuated jitter. Preliminary Data Sheet #: TM012 Page 2 of 16 Rev: P06 Date: 05/20/ 02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Table 1 Symbol VCC VI Ts VTS Parameter Power Supply Voltage Input Voltage Storage Temperature Voltage Applied to Tri-State Output Absolute Maximum Rating Minimum -0.5 -0.5 -40 -0.5 Nominal Maximum 5.5 5.5 85 5.5 Units Volts Volts deg. C Volts Notes 1.0 1.0 1.0 Table 2 Symbol Vcc VIH VIL Parameter Power Supply Voltage High level input voltage - CMOS Low level input voltage - CMOS Recommended Operating Conditions Minimum 4.75 2.0 0 Nominal Maximum 5.25 5.25 0.8 Units Volts Volts Volts 2.0 Notes Table 3 Symbol VOH VOL Parameter High level output voltage, IOH = -4.0mA, VCC = min. Low level output voltage, IOL = 8.0mA, VCC = max. DC Characteristics Minimum 2.4 Nominal 3.3 Maximum 3.6 0.4 Units Volts Volts Notes 3.0 Table 4 Parameter Frequency Range (Sync_Out) Frequency Range (Clk_Out) Supply Current Timing Reference Inputs Jitter, Wander and Phase Transient Tolerances Wander Generation Wander Transfer Jitter Generation Jitter Transfer Phase Transients Sync_Out (Pin #15) Free Run Accuracy Clock_Out (Pin #18) Accuracy Hold Over Stability Inital Offset Temperature Drift Maximum Hold Over History Minimum Time for Hold Over Pull-in/ Hold-in Range Lock Time Lock Accuracy RFL Alarm Limit Specifications Specifications 1.544 MHz - 38.88 MHz 1.544 MHz - 51.84 MHz 800 mA typical, 1.2 A during warm-up (Maximum) GR-1244-CORE 3.2.1 GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6 GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2 GR-1244-CORE 5.4 GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3 GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1 GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3 ±4.6 ppm over temperature range ±4.6 ppm over temperature range ±0.012 ppm ±0.001 ppm ±0.010 ppm ±0.001 ppm 1049 seconds 701 seconds after a reference rearrangement ±17 ppm from Free Run frequency 700 sec. 0.001 ppm (GR-1244-CORE 2.8) ±15 ppm from Free Run frequency 6.0 5.0 4.0 Notes NOTES: 1.0: Stresses beyond those listed under Absolute Maximum Rating may cause damage to the device. Operation beyond Recommended Conditons is not implied. 2.0: 3.0: Inputs are 3.3V CMOS,5V tolerant Logic is 3.3V CMOS 4.0: 5.0: 6.0: Hold Over stability is the cumulative fractional frequency offset as described by GR-1244-CORE, 5.2 Pull-in Range is the maximum frequency deviation from nominal clock rate on the reference inputs to the timing module that can be overcome to pull into sychronization with the reference After 700 seconds at stable temperature (±5° F) Preliminary Data Sheet #: TM012 © Copyright 2002 The Connor-Winfield Corp. Page 3 of 16 Rev: P06 Date: 05/20/ 02 All Rights Reserved Specifications subject to change without notice Pin Description Table 5 Pin # 1 2 3 4 5 6 7 internally. 8 internally. 9 10 11 12 13 freq. 14 15 16 17 18 19 20 21 22 23 24 Tri-State Hold Over Good Mode Alarm CNTL A CNTL B RFL GND Sync_Out Future Use GND Clock_Out Future Use GND External Reference 2 GND External Reference 1 +5 VDC Tri-State control for all outputs. 1 = Hi-Z condition, 0 = Normal operation. Pin is pulled low Indicates that the module has acquired enough data to provide an average Hold Over value. Alarm indicator output. 1 = Alarm condition, 0 = Normal operation. Mode control input. Pin is pulled low internally. Mode control input. Pin is pulled low internally. Reference frequency limit alarm for the phase locked loop. 1= Unit is ±15 ppm from Free Run Ground System clock output Reserved for future use. Do not assert this pin Ground An independent, Stratum 3 clock output with the required ±4.6 ppm accuracy. May be used as general purpose clock Reserved for future use. Do not assert this pin Ground External reference #2 input Ground External reference #1 input +5 Volt DC supply Connection Status 0 Status 1 LOR PBO GND 8 kHz Output Reset Description Mode indicator. Mode indicator. Loss of Reference indicator. 1 = active reference has been lost. Phase build out indicator. 1 = module is in a phase build out condition. Ground Derived from Sync_Out. Master reset for the module. A low pulse will reset the module. A logic low for a minimum of 1 µs is recommended to ensure a complete reset. This pin is pulled high Control Inputs Table 6 CNTL B 0 0 1 1 CTNL A 0 1 0 1 Mode Selected Free Run Reference 1 Reference 2 Hold Over Status Outputs Table 7 Status 1 0 0 1 1 Status 0 0 1 0 1 Mode Free Run Reference 1 Reference 2 Hold Over Preliminary Data Sheet #: TM012 Page 4 of 16 Rev: P06 Date: 05/20/ 02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Pin Assignment Figure 1 +5Vdc External Reference 1 GND External Reference 2 GND Future Use Clock_Out GND Future Use Sync_Out GND RFL 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 Status 0 Status 1 LOR PBO GND 8 kHz output Reset Tri-State Hold Over Good Mode Alarm CNTL A CNTL B Bottom View Typical Application Setup Figure 2 5 Vdc Power Supply +5Vdc External Reference 1 Network Timing Reference Input eg. BITS GND External Reference 2 GND Future Use Independent Free Run Clock_Out GND Future Use System Clock Sync_Out GND RFL Status 0 Status 1 LOR PBO GND 8 kHz output Reset Tri-State Hold Over Good Mode Alarm CNTL A CNTL B System Control State Machine Preliminary Data Sheet #: TM012 © Copyright 2002 The Connor-Winfield Corp. Page 5 of 16 Rev: P06 Date: 05/20/ 02 All Rights Reserved Specifications subject to change without notice Functional Truth Table Table 8 CNTLB CNTLA 0 0 0 0 0 0 0 0 1 1 1 1 Mode Free Run Free Run Reference #1 Reference #1 Reference #1 Reference #1 Status1Status0 Alarm 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 RFL 0 1 0 0 1 0 LOR 0 0 0 0 0 1 PBO 0 0 0 0 0 0 Condition Normal Operation Unit is in Fast Acquire mode Output freq. is 15 ppm or more from Free Run mode freq. Selected reference signal is not detected and unit is in pseudoHold Over* Phase build-out is occuring on selected reference Phase build-out is occuring and has continuously occurred for at least 0.4 seconds and the unit is in pseudo-Hold Over* Normal Operation Unit is in Fast Acquire mode Output freq. is 15 ppm or more from Free Run mode freq. Selected reference signal is not detected and unit is in pseudoHold Over* Phase build-out is occuring on selected reference Phase build-out is occuring and has continuously occurred for at least 0.4 seconds and the unit is in pseudo-Hold Over* 0 0 1 1 Reference #1 Reference #1 0 0 1 1 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 Reference #2 Reference #2 Reference #2 Reference #2 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 Reference #2 Reference #2 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 Hold Over Hold Over 1 1 1 1 1 1 0 1 0 0 0 0 *Psuedo-Hold Over is a condition when the module is no longer tracking a reference and is holding the last output that was sent to the Sync_Out pin. Variations in the output frequency are due only to the drift of the OCXO. Preliminary Data Sheet #: TM012 Page 6 of 16 Rev: P06 Date: 05/20/ 02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Functional Block Diagram Figure 3 CNTLA CNTLB Fast Acquire Free Run Hold Over PBO Mode Alarm RESET Status 1 Status 2 REF #1 REF #2 DSP LOR PBO RFL Hold Over Good DDS OCXO 1/N Voltage Regulation TCXO Sync_Out 8 kHz Output Clk_Out Preliminary Data Sheet #: TM012 © Copyright 2002 The Connor-Winfield Corp. Page 7 of 16 Rev: P06 Date: 05/20/ 02 All Rights Reserved Specifications subject to change without notice 3E Wander Generation TDEV Figure 4 100 GR-1244-CORE, Fig. 5-4, GR-253-CORE, Fig 5-8, Wander Generation-TDEV Wander Generation TDEV 10 TDEV (ns) 1 0.1 0.01 0.1 1 10 Integration Time (sec) 100 1000 10000 3E Wander Generation MTIE Figure 5 1000 GR-1244-CORE, Fig 5-5, Wander Generation-MTIE GR-253-CORE, Fig. 5-17, MTIE for SONET clock Wander Generation MTIE 100 MTIE (ns) 10 1 0.1 1 10 100 Observation Time (sec) 1000 10000 100000 Preliminary Data Sheet #: TM012 Page 8 of 16 Rev: P06 Date: 05/20/ 02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice 3E Wander Transfer TDEV Figure 6 10000 GR-1244-CORE, Fig5-6, Wander Transfer Calibrated 3E Wander Transfer TDEV 1000 TDEV (ns) 100 10 1 0.1 0.01 0.1 1 10 Integration Time (sec) 100 1000 10000 3E MTIE During Reference Rearrangement Figure 7 1000 GR-1244-CORE, Fig. 5-7, Phase Transient during Rearrangement Reference Switch MTIE 100 MTIE (ns) 10 1 0.01 0.1 1 Observation Time (sec) 10 100 1000 Preliminary Data Sheet #: TM012 © Copyright 2002 The Connor-Winfield Corp. Page 9 of 16 Rev: P06 Date: 05/20/ 02 All Rights Reserved Specifications subject to change without notice 3E Entry into Hold Over MTIE Figure 8 10000 GR-1244-C ORE , F ig. 5-8, P hase Transient MTIE Masks for E ntry into Hold Over E ntry in to Hold Over MTIE 1000 100 MTIE (ns) 10 1 0.1 0.01 0.1 1 10 Ob servation T ime (sec) 100 1000 10000 3E 1µs Phase Transient MTIE Figure 9 10000 GR-1244-CORE , Fig 5-9, M TIE m as k for I/O P hase Trans ient 1us P has e Trans ient M TIE 1000 MTIE (ns) 100 10 1 0.001 0.01 0.1 1 10 100 1000 10000 Obse rva tion Tim e (se c) Preliminary Data Sheet #: TM012 Page 10 of 16 Rev: P06 Date: 05/20/ 02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice 3E Jitter Attenuation Figure 10 1.0 Jitter attenuation (-dB) 5.715 dB 10.0 100.0 0.0001 0.001 0.01 0.1 1 10 INPU T Jitte r fre que ncy (H z) Hold Over Stability over Temperature Figure 11 4 .0 ∆ t = 3 0 d e g C /h o u r 3 .0 2 .0 1 .0 PPB 0 .0 - 1 .0 - 2 .0 - 3 .0 - 4 .0 70 60 50 40 30 20 10 0 T e m p e r a tu r e (d e g C ) Preliminary Data Sheet #: TM012 © Copyright 2002 The Connor-Winfield Corp. Page 11 of 16 Rev: P06 Date: 05/20/ 02 All Rights Reserved Specifications subject to change without notice Typical Current Consumption Over Temperature Figure 12 0.900 38.88MHz 19.44MHz 0.800 16.384MHz Current (Amps) 0.700 0.600 0.500 0.400 0 10 20 30 40 50 60 70 T emperature (°C) 3E Typical Phase Build Out MTIE Figure 13 Preliminary Data Sheet #: TM012 Page 12 of 16 Rev: P06 Date: 05/20/ 02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice 3E Phase Build Out > 34 ppm Frequency Change Figure 14 Mode Switch Timing Figure 15 Phase Buildout Indicator Change in Control Inputs Mode Alarm t1 t1 t2 t1 Operational Mode Indicator ∆ tm t1 = A transition period between 400 ms to 402.125 ms t2 = A transition period of 2.125 ms 2 msec