CPLL-018M-50-200.00

5X7 mm SMD, 3.3V, CMOS Frequency Range: Frequency Stability: Temperature Range: Operating: (Option M) (Option X) Storage: Input Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Logic: Load: Jitter: Aging: CPLL-018 Model ree dF ea oHS nt L R plia m Co 1.544MHz to 200MHz ±25ppm, ±50ppm, ±100ppm Programmable Clock Oscillator PLL Based Design 0°C to 70°C -20°C to 70°C -40°C to 85°C Designed to meet today's -55°C to 120°C requirements for economical 3.3V ± 0.3V 3.3V applications. Available 45mA Max on 16mm tape and reel in CMOS quantities of 1K. 40/60% Max @ 50% Vdd 10ns Max @ 20/% to 80% Vdd "0" = 80% Vdd Max "1" = 90% Vdd Min 15pF 150pS pk-pk Max