CPLL58-2450-2450

M I C of Crystek Corporation ROWAVE A Division CPLL58-2450-2450 0.582" × 0.800" SMD Features 2.450GHz Standard 3 Wire Interface Small layout 0.582" × 0.8" Applications Digital Radio Equipment Fixed Wireless Access Satellite Communications Systems Base Stations Personal Communications Systems Portable Radios Test Instruments Wireless Infrastructure The CPLL58 is a complete PLL/Synthesizer needing only an external frequency reference and supply voltages for the internal PLL (phase lock loop) and VCO (voltage controlled oscillator). The Crystek CPLL58 is programmed using a standard three line interface (Data, Clock and Load Enable). The CPLL58 family has been initially released to cover 1GHz to 5GHz in bands. It is housed in a compact 0.582-in. × 0.8-in. × 0.15-in. SMD package which saves board space. Typical phase noise at 4GHz is -90dBc/Hz at 10KHz offset with 0dBm minimum output power. Rev A Page 1 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com M I C of Crystek Corporation ROWAVE A Division PERFORMANCE SPECIFICATION Frequency Range: Step Size: Settling Time, to within ± 1kHz (Freq. step < 25MHz): Output Power: Output Phase Noise: (See Plot Below) @1KHz offset @10KHz offset @100KHz offset @1MHz offset Power Supply: V1=VCO Supply V2=PLL Supply Supply Current: I1=VCO Input Current I2=PLL Input Current Spurious Suppression PFDSpur Reference Feedthru Harmonic Suppression (2nd Harmonic): 2nd Reference Frequency RF Output Level Input Impedance RF Output Impedance Operating Temperature Range: MIN CPLL58-2450-2450 0.582" × 0.800" SMD TYP 2.450 100 1 +3.0 -75 -95 -120 -145 4.75 2.7 5.0 3.0 50 25 -70 -80 -15 10 0 100K 50 -60 -70 -10 +5 MAX UNITS GHz KHz msec dBm dBc/Hz dBc/Hz dBc/Hz dBc/Hz Volts Volts mA mA dBc dBc dBc dBc MHz dBm Ohm Ohm °C 0 +6.0 -70 -90 -115 -140 5.25 3.3 -5 -40 +85 Page 2 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com M I C of Crystek Corporation ROWAVE A Division CPLL58-2450-2450 0.582" × 0.800" SMD TOP VIEW 0.600 0.600 0.520 0.440 0.360 0.280 0.200 0.00 BOTTOM VIEW V2 [Pin1] GND GND 0.00 GND REF V1 CRYSTEK CPLL58 2450-2450 YYWW 0.171 0.251 0.331 0.411 GND GND GND GND GND GND GND GND LE = Load Enable, CMOS Input DATA = Serial Data Input CLK = Clock LD = Lock Detect REF = Reference Input V1 = Analog Supply Input (VCO) V2 = Digital Supply Input (PLL) RF = RF Output DATA 0.582 LE GND CLK TOP ORIENTATION MARK 0.150 0.000 0.052 0.000 0.000 Ramp-Up 3°C/Sec Max. 0.052 Pad Detail RECOMMENDED REFLOW SOLDERING PROFILE Critical Temperature Zone Ramp-Down 6°C/Sec. 260°C TEMPERATURE 217°C 200°C 150°C Preheat 180 Secs. Max. 8 Minutes Max. RF LD 90 Secs. Max. 260°C for 10 Secs. Max. Page 3 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com M I C of Crystek Corporation ROWAVE A Division CPLL58-2450-2450 0.582" × 0.800" SMD ENVIRONMENTAL COMPLIANCE Parameter Mechanical Shock Mechanical Vibration Solderability Resistance to Solvents Conditions MIL-STD-883, Method 2002 MIL-STD-883, Method 2007 MIL-STD-883, Method 1014 MIL-STD-883, Method 2016 Programming Guide for CPLL58-XXXX Introduction The CPLL58 uses a simple 3 wire interface to program four internal registers. See Figure 1. t3 CLOCK t4 t1 DATA DB23 (MSB) DB22 t2 DB2 DB1(CONTROL BIT C2) DB0(LSB) (CONTROL BIT C1) t6 LE t5 LE Figure 1. Timing Diagram There are four 24 bit registers that need to be programmed. Which register is written into is simply controlled by Control Bits C1 and C2. Table I summarizes the Truth Table for Control Bits C1 and C2. Control Bits C2 C1 0 0 1 1 0 1 0 1 R Counter N Counter (A and B) Function Latch (Including Prescaler) Initialization Latch Table I. C2, C1 Truth Table Data Latch Page 4 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com M I C of Crystek Corporation ROWAVE A Division Table II shows the details of the four 24 bit registers. CPLL58-2450-2450 0.582" × 0.800" SMD REFERENCE COUNTER LATCH LOCK DETECT PRECISION TEST MODE BITS ANTIBACKLASH WIDTH CONTROL BITS RESERVED 14-BIT REFERENCE COUNTER DB23 X DB22 0 DB21 0 DB20 LDP DB19 T2 DB18 T1 DB17 ABP2 DB16 ABP1 DB15 R14 DB14 R13 DB13 R12 DB12 R11 DB11 R10 DB10 R9 DB9 R8 DB8 R7 DB7 R6 DB6 R5 DB5 R4 DB4 R3 DB3 R2 DB2 R1 DB1 C2(0) DB0 C1(0) N COUNTER LATCH CP GAIN CONTROL BITS RESERVED 13-BIT COUNTER 6-BIT COUNTER DB23 DB22 DB21 G1 DB20 B13 DB19 B12 DB18 B11 DB17 B10 DB16 B9 DB15 B8 DB14 B7 DB13 B6 DB12 B5 DB11 B4 DB10 B3 DB9 B2 DB8 B1 DB7 A6 DB6 A5 DB5 A4 DB4 A3 DB3 A2 DB2 A1 DB1 C2(0) DB0 C1(1) FUNCTION LATCH POWER-DOWN 2 POWER-DOWN 1 PD POLARITY FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PRESCALER VALUE COUNTER RESET CONTROL BITS CURRENT SETTING2 CURRENT SETTING 1 TIMER COUNTER CONTROL MUXOUT CONTROL DB23 P2 DB22 P1 DB21 PD2 DB20 CP16 DB19 CP15 DB18 CP14 DB17 CP13 DB16 CP12 DB15 CP11 DB14 TC4 DB13 TC3 DB12 TC2 DB11 TC1 DB10 F5 DB9 F4 DB8 F3 DB7 F2 DB6 M3 DB5 M2 DB4 M1 DB3 PD1 DB2 F1 DB1 C2(1) DB0 C1(0) INITIALIZATION LATCH POWER-DOWN 2 POWER-DOWN 1 PD POLARITY FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PRESCALER VALUE COUNTER RESET CONTROL BITS CURRENT SETTING2 CURRENT SETTING 1 TIMER COUNTER CONTROL MUXOUT CONTROL DB23 P2 DB22 P1 DB21 PD2 DB20 CP16 DB19 CP15 DB18 CP14 DB17 CP13 DB16 CP12 DB15 CP11 DB14 TC4 DB13 TC3 DB12 TC2 DB11 TC1 DB10 F5 DB9 F4 DB8 F3 DB7 F2 DB6 M3 DB5 M2 DB4 M1 DB3 PD1 DB2 F1 DB1 C2(1) DB0 C1(1) Table II. Latch Summary When using the CPLL58 family in a synthesizer application, all four 24 bit registers need to be written into after power-up. After writing all four latches the first time, subsequent frequency step changes can be accomplished by changing the N Counter Latch only. Specifications subject to change without notice. Page 5 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com M I C of Crystek Corporation ROWAVE A Division CPLL58-2450-2450 0.582" × 0.800" SMD Programming Crystek p/n: CPLL58-2450-2450 The following is specific programming for CPLL58-2450-2450 (2.450GHz fixed freq. with 100KHz Step Size and 10MHz input reference frequency). Program all three registers with the following: R Counter Latch: 000190 H N Counter Latch: 02FD51 H Function Latch: 9F8083 H The above values will set the CPLL58-2450-2450 to 2.450GHz Page 1 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com