CTSLVEL16VRNLG

CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 FEATURES      BLOCK DIAGRAM Minimizes External Components Selectable Enable Polarity and Threshold (CMOS or PECL) High Bandwidth for 1GHz Similar Operation as CTS100EL16 -147 dBc/Hz Typical Noise Floor DESCRIPTION The CTSLVEL16VR is a specialized oscillator gain stage with a high gain output buffer including an enable function. The QHG/Q ¯ HG outputs have voltage gain several times greater than the Q/Q ¯ outputs. It provides a selectable QHG/Q ¯ HG enable that allows continuous oscillator operation via the Q/Q ¯ outputs. The CTSLVEL16VR provides adjustable internal pull-down current sources for the Q/Q ¯ outputs and optional 10mA current sources for the QHG/Q ¯ HG outputs. Internal input biasing further reduces the number of needed external components. ENGINEERING NOTES Functionality of MLP16 Package (CTSLVEL16VRNLG) The CTSLVEL16VRNLG provides a selectable QHG/Q ¯ HG enable that allows continuous oscillator operation via the Q/Q ¯ outputs. Table 1 shows the operating modes. Leaving EN-SEL open (NC) selects PECL/ECL operation for the EN pad/pin. In this mode the QHG/Q ¯ HG outputs are enabled when EN is left open (NC) or set to a PECL/ECL low. Connecting EN-SEL to VCC, VEE or VBB selects CMOS operation for the EN pad/pin. When EN-SEL is tied to VEE, the QHG/Q ¯ HG outputs are disabled when EN is left open (NC). When EN-SEL is tied to VCC or VBB, the QHG/Q ¯ HG outputs are enabled when EN is left open. This default logic condition can be overridden by a  20k resistor connected to the opposite supply. The CTSLVEL16VRNLG also provides a VBB and 470 internal bias resistors from D to VBB and D ¯ to VBB. The VBB pin supports 1.5mA sink/source current. VBB should be bypassed to ground or VCC with a 0.01 F capacitor. Outputs Q/Q ¯ each have a selectable on-chip pull-down current source. See Table 2 for the supported values. External resistors may also be used to increase pull-down current to a maximum total of 25mA for the Q/Q ¯ outputs. ¯ HG outputs has an optional on-chip pull-down current source of 10mA. When pad/pin Each of the QHG/Q VEEP is left open (NC), the output current sources are disabled and the QHG /Q ¯ HG operate as standard PECL/ECL. When VEEP is connected to VEE, the current sources are activated. The QHG /Q ¯ HG pull-down current can be decreased by using a resistor between VEEP and VEE. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 1 RevB0114 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 Table 1 - Enable Truth Table EN Q/Q ¯ EN-SEL NC VEE1 VCC or VBB1,2 QHG Q ¯ HG PECL Low, VEE or NC Data Data Data PECL High or VCC Data Low High CMOS Low, VEE or NC Data Low High CMOS High or VCC Data Data Data CMOS Low or VEE Data Low High CMOS High, VCC or NC Data Data Data 1 EN-SEL connections must be ≤1Ω. 2 Date codes prior to 0428 do not support this operating mode. Table 2 - Current Source Truth Table CS-SEL Q Q ¯ 1 NC 4mA typ 4mA typ VEE1 VCC1 8mA typ 8mA typ 0 4mA typ Connection must be less than 1Ω. Figure below illustrates the timing sequences for the CTSLVEL16VRNLG in the MLP 16 package. It is shown here with the enable operating in active Low mode with a PECL threshold. This mode is determined by leaving the EN-SEL open (NC). An active High enable with a CMOS/TTL threshold is also an option. CTSLVEL16VRNLG Timing Diagram North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 2 RevB0114 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 Functionality MLP8 Package (CTSLVEL16VRNNG) A CMOS enable input (EN) allows continuous oscillator operation. When the EN input is HIGH or left open (NC), the Q ¯ and QHG/Q ¯ HG outputs follow the data input. When EN is LOW, the QHG output is forced high and the Q ¯ HG output is forced low while Q ¯ continues to follow the data input. The Q ¯ output has an internal 4 mA current source to VEE, in most cases eliminating the need for an external pull-down resistor. The CTSLVEL16VRNNG also provides biasing. Data input D is tied to the VBB pin through a 470 internal bias resistor while the inverting input D ¯ is connected directly to VBB. The VBB pin supports 1.5mA sink/source current. VBB should be bypassed to ground with a 0.01 F capacitor. CTSLVEL16VRNNG Timing VOUTpp (mV) 1000 900 800 700 600 500 400 300 200 100 0 0 500 1000 1500 2000 2500 FREQUENCY (MHz) 3000 3500 4000 North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 3 RevB0114 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 AC Coupling Capacitor C2 R1 See table EL16VO Front End 3.3 or 5 V CMOS D R2 470 Ω D VBB C1 0.01 μF Application Circuit for CMOS Inputs Recommended Component Values for CMOS Single Ended Inputs R11 Value Input Type AC Coupled (C2 in DC Coupled (C2 circuit) shorted) 3.3V CMOS 1.1 kΩ 2.0 kΩ 5.0V CMOS 1.6 kΩ 3.3 kΩ 1 R1 should be chosen so that the input swing on the D input with respect to D ¯ is in the range of ±80 to ±1000 mV, per the AC Characteristics table and the D input is < ±750 mV with respect to VBB.   North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 4 RevB0114 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 S11 50Ω external AC, 4 & 8mA internal DC load       S12 50Ω external AC, 4 & 8mA internal DC load   North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 5 RevB0114 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 S21 50Ω external AC, 4 & 8mA internal DC load         S22 50Ω external AC, 4 & 8mA internal DC load     North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 6 RevB0114 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol Characteristic Condition Rating Unit VCC PECL Power Supply VEE = 0V 0 to + 6.0 V VD_PECL PECL D Input Voltage Referenced to VBB ±0.75 V VEN_PECL PECL D Input Voltage VEE = 0V 0 to + 6.0 V VEE ECL Power Supply VCC = 0V -6.0 to 0 V VD_ECL ECL D Input Voltage Referenced to VBB ±0.75 V VEN_ECL ECL D Input Voltage VCC = 0V -6.0 to 0 V Continuous Q 25 Surge Q 50 Continuous QHG 50 Surge QHG 100 Operating Temperature Range - -40 to +85 °C IOUT Output Current TA mA TSTG Storage Temperature Range - -65 to +150 °C ESDHBM Human Body Model Electro Static Discharge - 2500 V ESDMM Machine Model Electro Static Discharge - 200 V ESDCDM Charged Device Model Electro Static Discharge - 2000 V ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND) Symbol Characteristic VOH VOL -40°C Max Min Max Min Max Output HIGH Voltage1 -1045 -835 -1025 -835 -1025 -835 -1025 -835 mV 1 -1925 -1555 -1900 -1620 -1900 -1620 -1900 -1620 mV -1165 -740 -1165 -740 -1165 -740 -1165 -740 mV VEE +2000 VCC VEE +2000 VCC VEE +2000 VCC VEE +2000 VCC mV -1475 VEE +800 -1250 mV 150 µA IIH Input HIGH Current EN Input LOW Current EN (ECL) 1 Power Supply Current 1 2 3 -1900 VEE -1390 -1475 VEE +800 -1250 -1900 VEE -1390 150 2 Input LOW Current EN (CMOS) IEE Unit Min VBB IIL 85°C Max Input LOW Voltage D,EN (ECL)2 Input LOW Voltage EN (CMOS)3 Reference Voltage VIL 25°C Min Output LOW Voltage Input HIGH Voltage D,EN (ECL)2 Input HIGH Voltage EN (CMOS)3 VIH 0°C 3 -1475 VEE +800 -1250 -1900 VEE -1390 150 -1475 VEE +800 -1250 -1900 VEE -1390 150 0.5 0.5 0.5 0.5 -150 -150 -150 -150 48 48 48 mV mV µA 54 mA Specified with each output terminated through 50Ω resistors to VCC -2V. EN-SEL = NC. EN-SEL = VCC or VEE. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 7 RevB0114 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V) Symbol Characteristic -40°C Min Typ 0°C Max Min Typ 25°C Max Min 85°C Typ Max Min Typ Max Unit Propagation Delay tPLH/tPHL D toQ1 QHG1 tSKEW Vpp (AC) D to Duty Cycle Skew3 Input Swing4 Differential Output Rise/Fall1,2 (20% - 80%) tr/tf 1 2 3 5 400 400 400 400 ps 450 450 450 450 ps 20 ps 20 5 20 5 20 5 80 1000 80 1000 80 1000 80 1000 mV 100 240 100 240 100 240 100 240 ps Specified with CS-SEL connected to VEE, Q terminated with an AC coupled to 50Ω load. Specified with each output terminated through 50Ω resistors to VCC - 2V. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) Symbol Characteristic VOH VOL -40°C Max Min Max Min Max Output HIGH Voltage1,2 2255 2465 2275 2465 2275 2465 2275 2465 mV 1,2 1375 1745 1400 1680 1400 1680 1400 1680 mV 2135 2560 2135 2560 2135 2560 2135 2560 mV 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV 1400 1825 1400 1825 1400 1825 1400 1825 mV GND 800 GND 800 GND 800 GND 800 mV 1910 2050 1910 2050 1910 2050 1910 2050 mV 150 µA Input HIGH Current EN Input LOW Current EN (ECL) Input LOW Current EN (CMOS)4 Power Supply Current2 IEE 1 2 3 4 Unit Min IIH IIL 85°C Max VBB VIL 25°C Min Output LOW Voltage Input HIGH Voltage D,EN (ECL)3 Input HIGH Voltage EN (CMOS)4 Input LOW Voltage D,EN (ECL)3 Input LOW Voltage EN (CMOS)4 Reference Voltage1 VIH 0°C 150 3 150 150 0.5 0.5 0.5 0.5 -150 -150 -150 -150 48 48 48 µA 54 mA For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value. Specified with each output terminated through 50Ω resistors to VCC - 2V. EN-SEL = NC. EN-SEL = VCC or VEE. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 8 RevB0114 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 PECL DC Characteristics (VEE = GND, VCC = +5.0V) Symbol Characteristic VOH VOL -40°C 0°C 25°C 85°C Unit Min Max Min Max Min Max Min Max Output HIGH Voltage 3955 4165 3975 4165 3975 4165 3975 4165 mV Output LOW Voltage 3075 3445 3100 3380 3100 3380 3100 3380 mV Input HIGH Voltage D,EN (ECL) 3835 4260 3835 4260 3835 4260 3835 4260 mV Input HIGH Voltage EN (CMOS) 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV Input LOW Voltage D,EN (ECL) 3100 3525 3100 3525 3100 3525 3100 3525 mV Input LOW Voltage EN (CMOS) GND 800 GND 800 GND 800 GND 800 mV VBB Reference Voltage 3610 3750 3610 3750 3610 3750 3610 3750 mV IIH Input HIGH Current EN 150 µA VIH VIL IIL IEE 150 150 150 Input LOW Current EN (ECL) 0.5 0.5 0.5 0.5 Input LOW Current EN (CMOS) -150 -150 -150 -150 Power Supply Current 48 48 48 µA 54 mA North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 9 RevB0114 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 Pin Description and Configuration Pin Assignments CTSLVEL16VRNLG Pin Name Type Function 1 NC - 2 D Input N/A Data Input 3 D ¯ Input Inverting Data Input 4 VBB Output Reference Voltage 5 EN Input Output Enable 6 NC - N/A 7 VEE Power 8 VEEP Input 9 EN-SEL Input 10 Q ¯ HG Output 11 QHG Output Negative Supply High Gain Current Source Enable Enable Polarity Select High Gain Inverting PECL Output High Gain PECL Output 12 CS-SEL Input 13 VCC Power Current Source Select Positive Supply 14 NC - N/A 15 Q Output PECL Output 16 Q ¯ Output Inverting PECL Output Pin Configuration for CTSLVEL16VRNLG Pin Description CTSLVEL16VRNNG Pin Name Type Function 1 D Input Data Input 2 VBB Output Reference Voltage 3 EN Input 4 VEE Power 5 Q ¯ HG Output 6 QHG 7 8 D 1 Output Enable VBB 2 EN 3 Output Negative Supply High Gain Inverting PECL Output High Gain PECL Output VCC Power Positive Supply VEE 4 Q ¯ Output Inverting PECL Output Leave Pad open or connect to VEE 8 Q 7 VCC 6 QHG 5 QHG Pin Configuration for CTSLVEL16VRNNG PART ORDERING INFORMATION Part Number CTSLVEL16VRNLG CTSLVEL16VRNNG Package MLP16 MLP8 Marking 100G 16R YYWW R5G YYWW North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 10 RevB0114 CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 PACKAGE DIMENSIONS North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 11 RevB0114