CTSLVEL16VVRLG

CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable Not recommended for new designs MLP16 FEATURES     Minimizes External Components Similar Operation as CTSLVEL16VR except with Selectable Data Input Pairs High Bandwidth for 1GHz -147 dBc/Hz Typical Noise Floor BLOCK DIAGRAM DESCRIPTION The CTSLVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain output buffer including an enable. Selectable data input pairs permit switching between two different oscillator frequencies. The QHG/Q ¯HG outputs have a voltage gain several times greater than the Q/ Q ¯ outputs. An enable allows continuous oscillator operation by only controlling the QHG outputs. The CTSLVEL16VV also provides a reference voltage (VBB) with internal biasing resistors to each input to minimize external components. ENGINEERING NOTES The CTSLVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain output buffer including an enable. The QHG/Q ¯HG outputs have a voltage gain several times greater than the Q/Q ¯ outputs. The CTSLVEL16VV provides two selectable data input pairs that permit switching between two different oscillator frequencies. When the select pin (SEL) is LOW or open (NC) data from the D0/D ¯¯0 is selected. When the SEL pin is HIGH data from the D1/D ¯¯1 is selected. Allowing continuous oscillator operation, the (EN) enable works with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets of outputs. When EN is LOW, the QHG/Q ¯HG outputs will be forced LOW/HIGH respectively, while input ¯ outputs. The EN and SEL inputs can be driven with an data will continue to be passed to the Q/Q ECL/PECL signal or a full supply swing CMOS type logic signal. The CTSLVEL16VV also provides a VBB with a 1.5mA sink/source current. Each data input is separately connected to VBB with a 470Ω internal bias resistor. Bypassing VBB to ground with a 0.01µF capacitor is recommended. Each Q/Q ¯ output has a 4mA on-chip pull-down current source. External resistors may also be used to increase pull-down current of the Q/Q ¯ to a maximum of 25mA each (includes a 4mA on-chip current source). North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 1 RevA0215 CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable Not recommended for new designs MLP16 Truth Table EN High/Open CS-SEL Low/Open Q ¯ D0/D ¯¯0 QHG D0/D ¯¯0 Q ¯ HG D0/D ¯¯0 High/Open Low High Low/Open D1/D ¯¯1 D0/D ¯¯0 D1/D ¯¯1 Low D1/D ¯¯1 High Low High D1/D ¯¯1 Low High Timing Diagram North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 2 RevA0215 CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable MLP16 Not recommended for new designs S11   S12 North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 3 RevA0215 CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable MLP16   Not recommended for new designs   S21           S22 North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 4 RevA0215   CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable Not recommended for new designs MLP16 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol VCC Characteristic PECL Power Supply VD_PECL VEN_PECL VEE PECL D Input PECL D Input Voltage ECL Power VD_ECL ECL D Input Voltage VEN ECL D Input Voltage ECL Condition VEE = 0V Output Current IOUT Rating 0 to + 6.0 Unit V Referenced to VBB VEE = 0V ±0.75 0 to + 6.0 V V VCC = 0V -6.0 to 0 V Referenced to VBB V VCC = 0V ±0.75 -6.0 to 0 Continuous Q 25 Surge Q 50 Continuous QHG 50 Surge QHG 100 V mA TA Operating Temperature Range - -40 to +85 °C TSTG Storage Temperature Range - -65 to +150 °C ESDHBM Human Body Model Electro Static Discharge - 2500 V ESDMM Machine Model Electro Static Discharge - 200 V ESDCDM Charged Device Model Electro Static Discharge - 2000 V ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND) Symbol -40°C Characteristic Min 0°C Max Min 25°C Max Min 85°C Max Min Max Unit VOH Output HIGH Voltage1 -1045 -835 -1025 -835 -1025 -835 -1025 -835 mV VOL Output LOW Voltage1 -1925 -1555 -1900 -1620 -1900 -1620 -1900 -1620 mV Input HIGH Voltage D -1165 -740 -1165 -740 -1165 -740 -1165 -740 mV Input HIGH Voltage EN,SEL Input LOW Voltage D -1165 -1900 VCC -1475 -1165 -1900 VCC -1475 -1165 -1900 VCC -1475 -1165 -1900 VCC -1475 mV Input LOW Voltage EN,SEL VEE -1475 VEE -1475 VEE -1475 VEE -1475 Reference Voltage -1390 -1250 -1390 -1250 -1390 -1250 -1390 -1250 mV 150 µA VIH VIL VBB IIH Input HIGH Current EN,SEL IIL Input LOW Current EN,SEL 1 IEE Power Supply Current 1 150 -100 150 -100 47 150 -100 47 -100 47 µA 51 Specified with each output terminated through 50Ω resistors to VCC –2V. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 5 RevA0215 mA CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable MLP16 Not recommended for new designs LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) Symbol -40°C Characteristic 0°C 25°C 85°C Min Max Min Max Min Max Min Max Unit VOH Output HIGH Voltage1,2 2255 2465 2275 2465 2275 2465 2275 2465 mV VOL 1,2 1375 1745 1400 1680 1400 1680 1400 1680 mV Input HIGH Voltage D 2135 2560 2135 2560 2135 2560 2135 2560 mV Input HIGH Voltage EN,SEL Input LOW Voltage D 2135 1050 VCC 1825 2135 1400 VCC 1825 2135 1400 VCC 1825 2135 1400 VCC 1825 mV Input LOW Voltage EN,SEL Reference Voltage1 VEE 1825 2050 VEE 1825 2050 VEE 1825 2050 VEE 1825 2050 mV 150 µA 51 µA mA Output LOW Voltage VIH VIL VBB IIH 1910 Input HIGH Current EN 3 IIL Input LOW Current EN 150 -400 Power Supply Current 1 2 3 1910 150 -400 2 IEE 1910 47 1910 150 -400 47 -400 47 Voltage levels vary 1:1 with VCC. Specified with each output terminated through 50Ω resistors to VCC -–2V. Specified with EN and SEL forced to VEE. PECL DC Characteristics (VEE = GND, VCC = +5.0V) Symbol -40°C Characteristic 0°C 25°C 85°C Min Max Min Max Min Max Min Max Unit VOH Output HIGH Voltage1,2 3955 4165 3975 4165 3975 4165 3975 4165 mV VOL Output LOW Voltage1,2 3075 3445 3100 3380 3100 3380 3100 3380 mV Input HIGH Voltage D Input HIGH Voltage EN,SEL Input LOW Voltage D 3835 4260 3835 4260 3835 4260 3835 4260 mV VIH 3835 3100 VCC 3525 3835 3100 VCC 3525 3835 3100 VCC 3525 3835 3100 VCC 3525 mV Input LOW Voltage EN,SEL Reference Voltage1 VEE 3610 3750 3610 3750 3610 3750 3610 3750 mV 150 µA 51 µA mA VIL VBB IIH Input HIGH Current EN 3 IIL Input LOW Current EN 150 -1000 2 Power Supply Current IEE 1 2 3 150 -1000 47 150 -1000 47 -1000 47 Voltage levels vary 1:1 with VCC. Specified with each output terminated through 50Ω resistors to VCC -–2V. Specified with EN and SEL forced to VEE. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 6 RevA0215 CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable MLP16 Not recommended for new designs LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) Symbol -40°C Characteristic Unit Min Max Min Max Min Max Propagation Delay 2255 2465 2275 2465 2275 2465 2275 2465 mV D to Q/Qb 1375 1745 1400 1680 1400 1680 1400 1680 mV D to QHG/QbHG 2135 2560 2135 2560 2135 2560 2135 2560 mV Duty Cycle Skew1 Input Swing2 2135 1050 VCC 1825 2135 1400 VCC 1825 2135 1400 VCC 1825 2135 1400 VCC 1825 mV Output Rise and Fall (20% - 80%) VEE 1825 VEE 1825 VEE 1825 VEE 1825 VPP (AC) 2 85°C Max tSKEW 1 25°C Min tPLH/tPHL tR/tF 0°C Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. VPP is the peak-to-peak differential input swing for which AC parameters are guaranteed. The device has a voltage gain of ≈20 to Q/Q ¯ outputs and a voltage gain of ≈100 to QHG/Q ¯ HG outputs. Pin Description and Configuration Pin Assignments Pin Name Type Function 1 D0 Input Data Input 2 D ¯¯0 Input Inverting Data Input 3 Input Input Data Input 4 D1 D ¯¯1 5 VBB Reference Voltage 6 NC Output Power Negative Supply Inverting Data Input N/A 7 VEE 8 NC - 9 EN Input 10 Q ¯ HG Output 11 QHG Output High Gain Inverting PECL Output High Gain PECL Output 12 SEL Input Data Input Select 13 VCC 14 NC 15 Q Output PECL Output 16 Q ¯ Output Inverting PECL Output Power - N/A Output Enable Positive Supply N/A North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 7 RevA0215 CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable MLP16 Not recommended for new designs PACKAGE DIMENSIONS PART ORDERING INFORMATION Part Number Package Marking CTSLVEL16VVRLG MLP16 CTSG 16K YYWW North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 8 RevA0215