ACM100

PRELIMINARY INFORMATION ACM100 ACM100 Automotive Camera Module Features • Complete camera solution for automotive camera applications • Monochrome, wide dynamic range camera (>120 dB intrascene) • Excellent visible and near IR sensitivity • 640 by 480 resolution • Choice of M-12 lens • Noise correction and image enhancement processing • NTSC interface • Fully programmable and configurable • Multiple output options: interlaced or progressive scan • Multiple lens options • I2C port for camera control • Fully parameterized processing and camera control • Region of interest Autobrite® and exposure control • Fully qualified automotive component • Normal Operating Temperature: – 40 to +85 ° C • Degraded Operating Temperature: – 40 to +115 ° C • Meets interior/in-cabin environmental requirements • Contact factory for complete qualification plans and reports • Other features • Low power (1200 mW @ 4.0V& 30 fps) • Single supply with voltage protection • Built-in temperature measurement Functional Description Cypress ACM100 Automotive Camera Module is the first fully-integrated imaging solution designed specifically for automotive vision systems. Built with Cypress CMOS imager, Autobrite® technology and video processing, the module produces crisp, clear video in any range (up to 120 dB) and excellent visible and near-IR sensitivity ensures detail rich scene information regardless of lighting conditions. This highly accurate image reproduction is required for automotive applications such as lane departure warning, night vision, adaptive cruise control, driver monitoring and intelligent airbag deployment. System Block Diagram The figure below shows a block diagram of the ACM100 module. The module includes an imager, with focusing optics, a processing chip and a NTSC video interface. Figure 1. System Block Diagram Cypress Semiconductor Corporation Document Number: 001-05325 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 06, 2006 ACM100 Interface Description The ACM100 module is intended to support a variety of automotive applications, so the module has been designed with flexible mechanical and electrical interfaces. Each of the interfaces is described in one of the following sections. Mechanical Interface The ACM100 module provides a flexible, fastener based mounting feature. The mounting holes on the ACM100 are sized for M5 screws. In addition, a variety of planar surfaces are provided to facilitate the alignment of the camera to the desired orientation in the vehicle. Figure 2 below defines the mechanical interfaces and envelope. Figure 2. Preliminary Envelope Drawing Analog Video Interface The ACM100 module offers an analog video interface. The camera supports both progressive scan and interlaced modes as described in the following sections. Interlaced Video Output Option It uses a 60 fps imager scan and the pseudo-interlace scanning option (defined in a later section) to generate 30 frame per second, or 60 field per second video. Figure 3 defines the timing of the video output and the voltage levels for the 1.4 Vpp waveform. Figure 3. Horizontal Line Timing H = 64 us / line (15.63 kHz, 768*T) 8.33 us (100*T) (White) +1.000V 53.33 us (640*T) 4.7 us (56*T) Active video (Black) +0.075V (Blank) 0.000V Horizontal Sync (Sync) -0.400V Sync rise & fall time 140 ± 20 ns 4.2 us (50*T) 1.8 us (22*T) Document Number: 001-05325 Rev. ** Page 2 of 20 ACM100 Progressive Scan Output Option Figure 4. Progressive Scan Output Option Vertical Blanking Interval Field 1 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Field 2 262 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 284 Serial Control Interface The ACM100 utilizes the I2C bus to control and provide status from an application. The I2C bus is a standard two wire serial bus with data rates up to 400,000 bits per second. The two interface signals are called SCLK and SDAT. SCLK provides a clock for asserting and sampling the SDAT signal. SCLK is unidirectional from the bus master, typically an image processing chip, to the ACM100. SDAT is the data bus and is bi-directional. Both signals are open-drain and require a pullup resistor of 1.5K Ohms. Data is always transmitted with the Most-Significant-Bit (MSB) first. Eight bits of data are always transferred and are followed by a single ACKnowledge bit which is driven by the receiver of the previous 8 data bits. Data transfer is initiated with a START condition. The START condition is indicated when the SDAT signal goes low while SCLK remains high. The START condition may be initiated at anytime during a transfer and the ACM100 will restart the transfer to begin accepting the DEVICE ADDRESS which must immediately follow the START. The SDAT line must only transition when SCLK is low when data is being transferred. If SDAT transitions while SCLK is high, then it will be interpreted as either a START or a STOP condition. Sufficient timing margins must be provided around the rising and falling edges of SCLK to insure that a START or STOP condition is not mistakenly recognized. Figure 5 START ACK 7 6 5 4 3 2 1 0 A STOP SDAT SCLK The DEVICE ADDRESS is a sequence of 7 bits, a READ/WRITE bit and an ACKnowledge bit. Data is always transmitted MSB first and LSB last as shown in Figure 6. The DEVICE ADDRESS is 7 bits long and must be 1110_011 (0xE6). The LSB of the first byte is the READ/WRITE bit where a high (1) indicates that a READ cycle will follow and a low (0) indicates that a write cycle will follow. After the READ/WRITE bit, the ACM100 will assert SDAT low shortly after SCLK goes low to acknowledge that the DEVICE ADDRESS has been recognized and the ACM100 is ready to process the command that follows. If the I2C bus master does not receive an acknowledge bit, it should restart the transaction as the ACM100 did not recognize its DEVICE ADDRESS If a read transaction has been requested (READ/WRITE is high), then the ACM100 will begin driving SDAT with the register data at the current address. If a write transaction has been requested then the bus master should send the REG ADDRESS byte. The REG ADDRESS byte specifies which register in the ACM100 is to be accessed. The next two bytes of data are the write data where the MSB is sent first and the LSB second. Upon completion of all data being transferred, the master should issue a STOP command to place the I2C interface in an idle state. A STOP command is initiated by first driving SDAT low and SCLK high, then bringing SDAT high while SCLK remains high. Figure 6 START 1 7 1 6 DEVICE ADDRESS 1 0 0 5 4 3 1 2 1 1 R/W 0 ACK A SDAT SCLK Document Number: 001-05325 Rev. ** Page 3 of 20 ACM100 Normal Write Cycle A normal write cycle is shown in Figure 7 below. The transaction begins with a START condition and then the DEVICE ADDRESS and then the READ/WRITE bit which must be 0. The ACM100 will acknowledge that it is ready for the transaction by asserting ACK low shortly after the falling edge of SCLK during the READ/WRITE bit. The ACM100 will tristate SDAT so the pullup can bring SDAT high shortly after the next falling edge of SCLK. The 2nd byte of a transaction is the REGISTER ADDRESS byte which is the address of the register within the ACM100 that is being written to. The ACM100 will assert ACK indicating that the address has been accepted. The 3rd byte of the transaction are the most significant bits (MSB) of the register being written to (bits 15:8). The 4th byte is the least significant bits (LSBs) of the register being written to (bits 7:0). The command is terminated with a STOP condition. Alternatively, another START command can be initiated at this point. Note that the register is updated when the STOP (or another START) condition is recognized. All 16 bits of the register are updated at the same time Figure 7. Normal Write Cycle S DEVICE ADDR 0 A REG ADDR A DATA MSB A DATA LSB AP Normal Write S START Noise Immune Write The I2C bus is susceptible to noise when run on a cable or even across a long distance on a PCB. To protect the camera operation in potentially noisy environments, the ACM100 has a feature that insures that I2C writes are only performed if the data is correct. A normal write cycle is performed as in the previous section but an additional byte of data is transferred which is a checksum of the REGISTER ADDRESS and the two data bytes. The checksum is easily computed on a microcontroller using the following formula: CHECKSUM = 0xFF + REGISTER_ADDRESS + DATA_MSB + DATA_LSB TFigure 8 below shows the sequence of bytes to insure a valid register write in the presence of noise on the I2C bus. Note that register REG9 bit 0 will enable the mode that requires the P STOP A ACKnowledge from SLAVE checksum byte be included for all write transactions. This mode is off by default which makes I2C writes compatible with previous versions of the ACM100. The register is updated during the ACK bit of the CHECKSUM byte if the checksum is correct. The ACM100 will not acknowledge the CHECKSUM byte if the transaction has been corrupted and the checksum does not match the computed checksum. The lack of the ACK in this case can be used as an indicator by the I2C bus master that the transaction has been corrupted and should be retried. When the checksum mode is enabled (REG9[0]=1) then the checksum is required and writes will no longer be compatible with previous versions of the ACM100. This mode insures that all writes have a good checksum. When the backwards compatible mode is disabled, the checksum byte is optional. Figure 8. Noise Immune Write S DEVICE ADDR 0 A REG ADDR A DATA MSB A DATA LSB A CHECKSUM AP Noise Immune Write S START P STOP A ACKnowledge from SLAVE Document Number: 001-05325 Rev. ** Page 4 of 20 ACM100 Normal Read Cycle A normal read cycle begins with a write cycle which is terminated after the REG_ADDR byte. This partial transaction is required to properly set the REGISTER ADDRESS to the register being read. Following the new START command and the DEVICE ADDRESS, the ACM100 will drive the MSBs of the register onto the SDA line. The I2C bus master must then provide an ACK bit for that byte. If the I2C master does not provide ACK the readback data, then the ACM100 I2C interface will return to the IDLE state and wait for a new START. The ACM100 will then drive the LSBs onto the SDA line and then the I2C bus master can either issue a STOP command or just not ACK the byte to end the transaction. The REGISTER ADDRESS is not automatically incremented after each byte so only one register can be read during each transaction. The register being read is sampled during the ACK bit of the DEVICE ADDRESS where the R/W bit is a 1. This insures that the two halves of the register being read are consistent as many registers are volatile and can update at any time - including the time between when the MSBs are being read out onto the I2C bus and when the LSBs are being read. The REGISTER ADDRESS remains loaded with whatever the last value was sent. Thus, a write followed by a read of the same register does not require reloading the REGISTER ADDRESS. Instead, a START and the DEVICE ADDRESS with R/W set 1 can immediately follow the DATA LSB of the write transaction. Note that there is no noise immunity protection on setting the REGISTER ADDRESS. Figure 9. Normal Read Cycle S DEVICE ADDR 0 A REG ADDR A S DEVICE ADDR 1 A DATA MSB A DATA LSB P Normal Read S START P STOP A ACKnowledge from SLAVE A ACKnowledge from MASTER Noise Immune Reads Noise immune reads are supported by reading the data bytes multiple times within the same I2C transaction. Figure 10 shows that the data in the register is sampled during the ACK bit of the DEVICE ADDRESS. The data is then read out during the DATA MSB and DATA LSB cycles. If additional bytes are read out, the ones-complement of the data can be read in sequence. The data can be compared by the I2C bus master to insure that the data is correct and that noise has not corrupted the I2C transaction. Note that the register data is always consistent as long as the bytes are read out without initiating a new I2C transaction (IE: a new START/STOP). If the bytes have been corrupted, the DATA MSB and DATA LSB fields can simply be read again as the register is not re-read unless a new DEVICE ADDRESS is issued. Note that this mode is backwards compatible with older versions of the ACM100 as reading the ones-complement of the register data is optional. Figure 10. Noise Immune Reads SAMPLE S DEVICE ADDR 0 A REG ADDR A S DEVICE ADDR 1 A DATA MSB A DATA LSB A DATA MSB A DATA LSB P Noise Immune Read S START P STOP A ACKnowledge from SLAVE A ACKnowledge from MASTER Connector Definition The standard camera comes with a pigtail connector terminated with a Hirose GT17VSN-6DP-HU. Please inquire Number 1 2 3 4 5 6 Signal I2C_SDAT PWR_IN_A GND I2C_SCLK GND NTSC_OUT as to the availability of other connectors should your application require a different connector. The following table defines the connector pins for the Hirose connector. Pins Required 1 1 1 1 1 1 Wire Color Green Red Blue Gray Yellow White Document Number: 001-05325 Rev. ** Page 5 of 20 ACM100 Functional Specification The Figure 11 below illustrates the processing contained in the ACM100 camera. Some of the key features of the processing are described in the following sections Figure 11. Processing Block Diagram I M A G E R Imager Control Autobrite Serial Interface Input Control Noise Removal Image Enhancement Output Control Fixed Pattern Noise Correction Dark Current Removal Defective Pixel Removal Merge Bins Sharpen Non Linear Gain Interlace NTSC Format Analog Conversion Pseudo Interlace In the progressive scan mode, the imager is scanned at 30 Hz and fed directly to the pipeline and video output. In the interlaced version, the camera employes a technique referred to as Pseudo Interlacing. Pseudo interlace provides a data stream capable of RS-170 (NTSC) compatibility. Pseudo interlace provides a benefit over standard interlacing by reducing motion artifacts. The way pseudo-interlace is generated in this system is that the sensor is read at 60fps. Each frame read out of the sensor is used to generate one field of the output image. When frame N is used to generate field 0, frame N+1 is used to generate field 1. Adjacent pairs of rows are averaged and output as a single row in order to not lose any sensitivity even though the sensor is integrating for only half as long (60 fps vs 30 fps). For field 0 the rows are summed in pairs starting with row 0 of the sensor. For field 1 the rows are summed in pairs starting with row 1 of the sensor. Figure 12 illustrates the generation of one field; the generation of the other field is essentially the same, with an offset of 1 input row at the beginning. Figure 12. Progressive Row Generation Diagram Row in N Pixel 0 Pixel 1 ... Pixel 638 Pixel 639 N.Pix 0 + N+1.Pix 0 N.Pix 1 + N+1.Pix 1 ... N.Pix 3 + N+1.Pix 3 N.Pix 4 + N+1.Pix 4 Row Out For Even Field start output at row N=1 For Odd field start output at row N=2 Row in N+1 Pixel 0 Pixel 1 ... Pixel 638 Pixel 639 Document Number: 001-05325 Rev. ** Page 6 of 20 ACM100 Autobrite ® The ACM100 module includes both automatic and manual control of both the integration period and the dynamic range. The automatic control may be based on the entire contents of the image, or on a user specified region of interest. The following sections describe the control in more detail. Region of Interest The camera includes a region of interest feature that can be used to influence the automatic control of the dynamic range and the integration period. The user designates a region of interest (of programmable size and position) within the full frame. The camera automatically optimizes the exposure and dynamic range for this region (alternatively, the region can be ignored for exposure and dynamic range setting). The region is defined by specifying the upper left and lower right corners of a rectangle using pixel row and column numbers. Tint Control The camera provides for both automatic and manual control of the integration period (exposure time). This can be specified independently of the gamma control – that is either can be fixed or set automatically. The Tint control algorithm attempts to set the camera to an integration period that places the average pixel value at a default or user specified level. In addition to setting the desired image average, the user may bound the integration period that is available to the automatic control. This can prevent the integration from exceeding motion blur limits in dark environments. Gamma Control The camera provides for both automatic and manual control of the dynamic range by selecting one of 29 response, or gamma, curves. This can be specified independently of the Tint control – that is either can be fixed or set automatically. Autobrite tracks two parameters to control the selection of a gamma code: the number of saturated pixels (those at the maximum digital value) and the number of pixels in the top histogram bin of the image. These parameters are tracked on a per image basis using binary counters. The algorithm can be tuned by setting the number of bits active in each counter. The logic responds to the overflow of the counter. Therefore the maximum number of saturated pixels and minimum number of top bin pixels desired are both set as a power of two. The algorithm works by increasing the dynamic range when the number of saturated pixels (max gray level) exceeds the saturation setting. The dynamic range is reduced when the number of pixels in the top bin of a histogram (of programmable size) falls below the specified value. In addition to setting the target values, the user may limit the maximum gamma setting available to the algorithm. This may be useful to applications that respond poorly to extremely high gamma values. Transition Control The camera includes features that allow the user to influence the response of the camera to dynamic lighting conditions. Human vision applications may desire a slow, smooth response to changes in lighting for aesthetic reasons. Machine vision application, not being influenced by aesthetic concerns, may desire a faster response. The camera includes features to allow the user to adjust the dynamic response of the camera to suit the application. Image Processing Fetaures The camera includes a number of features that improve or remove artifacts from the image. These features are described in the following sections. Dark Current Removal The camera automatically senses the dark current using inactive, or dark, columns in the sensor. The current is measured for each row and subtracted from the image. This feature may be disabled by the user. Column Fixed Pattern Noise Correction During the vertical retrace period of scanning the imager, a fixed voltage is applied to all of the columns of the imager. This voltage is sampled by the ADC and used to calculate offset errors on a column basis. These errors are then removed from the next frame. This feature may be disabled by the user. Defective Pixel Correction The camera includes a feature to compensate for defective pixels. A 3x3 non-linear filter is used to screen out defective pixels. The center pixel is compared against the average of its neighbors and if it is too high or low, the average is substituted for the defective pixel. This feature may be disabled by the user. Sharpening Filter The camera includes a 3X3 sharpening filter. The user may disable or specify the strength of the filter. Detailed Specifications The following sections outline some of the detailed specifications of the module. Document Number: 001-05325 Rev. ** Page 7 of 20 ACM100 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature .................................–40° to +125° C C Operating Temperature .............................. –40° to +115° C C Symbol VCC PACT I2C Levels VOH VOL VIH VIL ILOAD CIN COUT tr,tf Output Level [high] Output Level [low] Input Level [high] Input Level [low] Input Leakage Current Input Capacitance Output Capacitance Rise/Fall Time VI = 0V to 3.3V IOH = –4.0 mA IOL = 4.0 mA Parameter Supply Voltage Active power consumption 300 mA @ 4V Full frame 30 fps Conditions Electrical Characteristics (The following specifications apply for TA = –40ºC to +85ºC.) Input Voltage.......................................... –0.3V to VCC +0.3V ESD Susceptibility ....................................................... 2000V Operating Conditions Supply Voltage .....................................................4.0V +/-5% Operating Temperature ................................ –40° to +85° C C Reduced Performance................................ +85° to +115° C C Min. 3.8 Typ 4.0 1200 Max. 4.2 Unit V mW 2.0 GND 2.3 -0.5 8 0.01 8 10 VCC 0.8 5.5 10 10 10 12 5 V V V V mA pF pF ns VIN = 0V, f=1.0 MHz VIN = 0V, f=1.0 MHz Composite Video Signals Drive Impedance Video Signal White Level Black Level Blank Level Sync Level Vertical Frequency Horizontal Frequency Data Format Pixel Output Rate 75 Ohm 1.4 V p-p into a 75 - ohm load 1.000 V + 5% 0.075 V + 5% 0.000 V –0.400 V + 5% 59.93 Hz + 5% 15.75 kHz + 5% Interlaced/Progressive 12 Mhz Document Number: 001-05325 Rev. ** Page 8 of 20 ACM100 Register Description 0x00 User Tint Bit Definition 15 0 14 1 AB_K 13 0 12 0 TINT_EN 11 0 10 0 9 1 8 0 7 0 6 0 TINT 5 0 4 0 3 1 2 1 1 0 0 0 The User Tint register is used when manual control of the integration period is required by the application. The bits are defined as follows: [15:13] AB_K : This bit field can be used to slow down the response of the automatic Tint control to changes in the scene. This may be desirable if smooth changes between camera settings are preferable to rapid response. New Tint values are calculated based on the assumption that the image average will scale linearly with the Tint setting. The algorithm works by calculating the difference between the current and target image average and then based on that difference calculating what change in Tint is required to attain the desired image average. The algorithm then multiplies the change in Tint by the AB_K value and then adds the result to the current Tint value. Therefore, smaller values of AB_K will cause the Tint value to adjust in smaller increments, although the size of the steps will remain proportional to the lighting change for a fixed AB_K. The following table shows some examples of how AB_K affects the Tint calculations for a desired image average of 128. (Calculated Tint = Tint(128/Image Average)) Image Average 50 50 50 150 150 150 Tint 100 100 100 250 250 250 Calculated Tint 256 256 256 213 213 213 Tint Difference 156 156 156 -37 -37 -37 AB_K 1 0.5 0.25 1 0.5 0.25 New Tint 256 178 139 213 231 241 The operation of this field is defined by the following table. Other values are not defined and should not be used AB_K 4 3 2 1 [12] TINT_EN: Description Normal Response 75% of Normal Speed 50% of Normal Speed 25% of Normal Speed Writing a ‘1’ to this bit will enable manual control of the integration period. When enabled, the TINT value specified in this register will be used and automatic control of the integration period is disabled. Writing a ‘0’ to this location will disable manual control and enable the automatic control of the integration period. Changes to this bit will take affect on the next full frame of video. This field specifies the integration period as a number of rows. The maximum integration is 525 rows. At a frame rate of 30 fps, writing a value of 0X20D would result in a 33 msec integration period. Changes to this parameter will take affect on the next full frame of video. [11:0] TINT: Document Number: 001-05325 Rev. ** Page 9 of 20 ACM100 0x01 Min Tint Bit Definition 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 1 TINT_SKIP MIN_TINT The Min Tint register is used to specify the minimum integration period available to the algorithm controlling Autobrite as well as controlling several other features. The bits are defined as follows: [15:12] TINT_SKIP: This field specifies the frequency at which Tint updates made when automatic control of Tint is enabled. This field is set to a 2 frames by default to accommodate the one frame latency between calculation of a new Tint value and its taking effect. Note that the Tint will settle in the same number and size of steps, but will take longer to settle. To change the size of steps that Tint will use to adjust, use the AB_K parameter. [11:0] MIN_TINT: This field is used to specify the minimum integration period that the Autobrite algorithm will use to control the camera. It is only valid when manual control of the integration period is disabled. It is specified as the number of row periods you wish to have the sensor integrate. The maximum integration is 525 rows. Changes to this parameter will take affect on the next full frame of video. 0x02 Max Tint Bit Definition 15 1 Reserved 14 1 13 0 Reserved 12 0 11 0 10 0 9 1 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 0 0 0 MAX_TINT The Max Tint register is used to specify the maximum integration period available to the algorithm controlling Autobrite as well as controlling several other features. The bits are defined as follows: [15:12] Reserved: These bits are reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of this bit. [11:0] MAX_TINT: This field is used to specify the maximum integration period that the Autobrite algorithm will use to control the camera. It is only valid when manual control of the integration period is disabled. It is specified as the number of row periods you wish to have the sensor integrate. Changes to this parameter will take affect on the next full frame of video. 0x03 Merge Bins Control 1 Bit Definition 15 0 Reserved 14 0 13 1 Q_Slope 12 0 11 0 10 0 9 1 8 0 7 0 6 0 Max_Q 5 0 4 0 3 0 2 0 1 0 0 0 The Merge Bins Control register is used to enable and control the behavior of the merge bins contrast enhancement algorithm. The merge bins algorithm can be controlled by specifying a Q function that indicates how strongly gray levels should be affected by the algorithm. The Q function can be specified in one of two methods. The first method assumes that a maximum Q is specified for gray level zero and that this value is reduced for increasing gray levels at a specified slope until a minimum Q value is reached. The alternative is to manually load a table which will specify a unique Q value for each gray level. The bits are defined as follows: [15] Reserved: [14:12] Q_Slope: This bit is reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of this bit. The Q Slope field specifies the rate at which the Q value is reduced for increasing gray shades. This field is cumulatively subtracted from the initial, maximum value Document Number: 001-05325 Rev. ** Page 10 of 20 ACM100 [11:0] Max_Q: The Max Q field specifies the Q value for gray level zero. This forms the starting point for the Q function. Note: if the Min_Q value is set to be higher than the Max_Q value, the result will be a flat threshold at the Min_Q value. 0x04 Gain/Gamma Control Bit Definition 15 0 Reserved 14 0 13 0 12 0 11 1 10 0 9 1 8 1 7 1 6 1 5 0 4 0 3 0 GAMMA 2 1 1 1 0 0 GAMMA_EN GAMMA_SKIP MAX_GAMMA The Gain/Gamma Control register is used to specify parameters that affect the gamma control of the camera as well as the digital gain. The bits are defined as follows: [15] Reserved: [14:11]GAMMA_SKIP: This bit is reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of this bit. This field specifies the frequency at which gamma may be updated by the automatic control algorithm (when enabled.) The default is set to 2 to account for a one frame latency between the calculation of a new value and its effect. Lower values may result in an overshoot in the response to a step change in image lighting. These bits define the maximum gamma code that will be available to the algorithm controlling the dynamic range of the sensor. Changes to this parameter will take affect on the next full frame of video. These bits specify the value of gamma to be used when user gamma is enabled. Increasing values of gamma represent increasing amounts of signal compression – resulting in increased dynamic range. Values of 3 and below are linear and the maximum value of 31 represents the maximum dynamic range of the sensor. Changes to this field take affect immediately – even in the middle of a frame. This may result in a frame with the top and bottom portions of the image being taken with different gamma settings. Writing a ‘1’ to this bit will enable the use of the gamma value specified in the GAMMA field of this register to be used in place of the value calculated by the Autobrite algorithm. This may result in a frame with the top and bottom portions of the image being taken with different gamma settings [10:6]MAX_GAMMA: [5:1] GAMMA: [0] GAMMA_EN: 0x05 Merge Bins Control 2 Bit Definition 15 0 Reserved 14 0 13 1 User_Curve_En 12 1 Draw_Enable 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 Min_Q The Merge Bins Control register is used to enable and control the behavior of the merge bins contrast enhancement algorithm. The merge bins algorithm can be controlled by specifying a Q function that indicates how strongly gray levels should be affected by the algorithm. The Q function can be specified in one of several methods as shown in Figure 13. Document Number: 001-05325 Rev. ** Page 11 of 20 ACM100 Figure 13. Q Threshold Selection draw_en Default: 1 0 User_curve_en Default: 1 1 Note polarity of this mux Fixed Slope Settings Max Q = 512 Min Q = 16 Slope = -2 MUX Drawing Engine Defaults: Max Q = 512 Min Q = 16 Slope = -2 1 MUX 0 User Table Loaded over I2C Register 0x0C Defaults: Unknown The first two methods assume that the Q function has a specific shape defined by Max Q, Min Q and Slope parameters resulting in a Q function as shown in Figure 14. Figure 14. Standard Threshold Shape Max Q Slope Min Q 0 Gray Shade 511 The alternative is to manually load a table which will specify a unique Q value for each gray level. The bits are defined as follows: [15:14] Reserved: [13]User_Curve_En: These bits are reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of these bits. Writing a ‘0’ to this bit will enable the use of a user loaded curve. This must be loaded via register 0x15 prior to enabling this function. [12] Draw_En Writing a ‘1’ to this bit will enable a Q function based on the parameters programmed in registers 0x3 and 0x5. The Min Q field specifies the Q value at which the function will level off. The Q value for gray shade zero is set to the max Q value and then decremented by the Q Slope until this value is reached. Note: if the Min_Q value is set to be higher than the Max_Q value, the result will be a flat threshold at the Min_Q value. Page 12 of 20 [11:0] Min_Q Document Number: 001-05325 Rev. ** ACM100 0x06 ROI 1 Bit Definition 15 0 14 1 13 0 12 1 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 ROI_XOFF[15:8] ROI_XON[7:0] The ROI 1 register is used to specify the size and location of the region of interest box in the x axis (imager columns). The bits are defined as follows: [15:8] ROI_XOFF: [7:0] ROI_XON : 0x07 ROI 2 Bit Definition 15 0 14 1 13 0 12 1 11 1 10 1 9 1 8 1 7 0 6 0 5 1 4 0 3 1 2 1 1 1 0 0 This field specifies the 8 most significant bits of the ending X coordinate. The least significant bits are fixed at “000”. Therefore, the resolution of this coordinate is limited to multiples of 8. This field specifies the 8 most significant bits of the starting X coordinate. The least significant bits are fixed at “000”. Therefore, the resolution of this coordinate is limited to multiples of 8. ROI_YOFF[15:8] ROI_YON[7:0] The ROI 2 register is used to specify the size and location of the region of interest box in the x axis (imager rows). The bits are defined as follows: [15:8] ROI_YOFF: [7:0] ROI_XON : This field specifies the 8 most significant bits of the ending Y coordinate. The least significant bits are fixed at “00”. Therefore, the resolution of this coordinate is limited to multiples of 4. This field specifies the 8 most significant bits of the starting Y coordinate. The least significant bits are fixed at “00”. Therefore, the resolution of this coordinate is limited to multiples of 4. 0x08 Video Control Bit Definition 15 0 Reserved 14 1 TINT_HYST_EN 13 1 Reserved 12 1 DARK_OFFSET_EN 11 1 SHARP_STRENGTH 10 1 SHARP_EN 9 1 Rseserved 8 1 FPN_OFFSET_EN 7 0 FULL_FRAME_FPN 6 1 AGC_MODE 5 1 MB_EN 4 0 MB_ROI_EN 3 1 SK_EN 2 0 Reserved 1 0 NTSC_TEST_ENABLE 0 1 NTSC__EN The Video control register is used to enable various features that affect the output video signal. [15] Reserved: This bit is reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of this bit. Writing a ‘1’ to this bit will cause the automatic control of the Tint settings to have additional hysteresis. This added hysteresis will cause changes of less than two lines to be suppressed. This is useful in eliminating the appearance of flickering in very bright scenes where a change of one line of integration time represents a significant change in image brightness. [14] TINT_HYST: Document Number: 001-05325 Rev. ** Page 13 of 20 ACM100 [13] Reserved: [12] DARK_OFFSET_EN: [11] SHARP_STRENGTH: [10] SHARP_EN: [9] Reserved: [8] FPN_OFFSET_EN: This bit is reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of this bit. Writing a ‘1’ to this location will enable dark current correction. Writing a ‘0’ will disable dark current correction. Writing a ‘1’ to this bit will cause the sharpening filter to be at the stronger setting. Writing a ‘0’ to this bit will cause the sharpening filter to be at a weaker setting. Writing a ‘1’ to this bit will enable the 3X3 FIR, sharpening filter. This filter has two default strengths. This bit is reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of this bit. Writing a ‘1’ to this location will enable the automatic correction of column fixed pattern offset errors in the hardware. FPN coefficients are calculated by placing known voltages on the columns when imager data is not being read. Writing a ‘0’ to this location will disable FPN offset correction. Note that on power up or after a system reset, this may require as much as two minutes to reach full performance. This is a result of filtering on the correction values to remove the affects of non-fixed pattern noise. Writing a ‘1’ to this location will cause FPN data to be collected over the entire frame. This is a test feature and it will cause the video to be overwritten. Writing a ‘0’ to this bit will enable normal operation. Writing a ‘0’ to this bit will disable all gain stages in the processing pipeline including merge bins. This mode is intended to be used to measure the SNR of the imager. Writing a ‘1’ to this bit will enable normal operation of the processing pipeline. Writing a ’1’ to this bit will enable Merge Bins contrast enhancement block in the processing pipeline. This block applies an adjustable non-linear function to ensure the video is mapped efficiently to 8 bits Writing a ’1’ to this bit will enable the ROI feature for the merge bins algorithm. Enabling this feature causes the algorithm to generate a non-linear transform that optimizes the portion of the image in the region of interest. The same transform is applied to the entire image, but the transform is calculated to optimize the region of interest. Writing a ‘1’ to this location will enable the starkiller, non-linear filter. This filter detects and corrects for single pixel defects in the imager. This bit is reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of this bit. Writing a ‘1’ to this bit will cause the camera to generate a test pattern on the NTSC output. Writing a ‘0’ will enable normal operation. Writing a ‘0’ to this bit will turn off the NTSC output of the camera. Writing a ‘1’ to this bit will enable the NTSC output. [7] FULL_FRAME_FPN: [6] AGC_MODE: [5] MB_EN: [4] MB_ROI_EN : [3] SK_EN: [2] Reserved: [1] NTSC_TEST_ENABLE: [0]NTSC_EN: Document Number: 001-05325 Rev. ** Page 14 of 20 ACM100 0x09 Video Control 2 Bit Definition 15 0 14 0 13 0 NLG_EN 12 0 NLG_Strength 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 Data format 3 0 2 0 1 0 0 0 CHKSUM PIX_RPLC Reserved Reserved The Video control register is used to enable various features that affect the output video signal. The bits are defined as follows: This field can be used to replace the active video with either all white or all black pixels. This is a feature that can be used to test/troubleshoot the camera. The field is defined by the following table: [15:14] PIX_RPLC: PIX_RPLC 00 01 10 11 PIX_RPLC Normal Video Video is all black Video is all white Video is a counting value [13] NLG_EN: [12] NLG_Strength: [11:5] Reserved: Writing a ‘1’ to this field will enable a non-linear gain to be applied which will boos the signal strength of darker regions of the image without saturating the bright images. Writing a ‘1’to this field will enable the stronger setting of the non-linear gain function. Writing a ‘0’ will enable the weaker setting. These bits are reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of these bits. When this bit is set to 0 it sets to Interlaced mode and when this bit is set to 1 it sets to Progressive mode These bits are reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of these bits. Writing a 1 to this bit puts the I2C bus interface into a mode where the CHECKSUM byte is required for all I2C register writes. The default for this bit is 0 which enables I2C writes to be terminated at the end of the 2nd data byte which is compatible with older versions of the ACM100. For more details See “Noise Immune Write” on page 4. [4] Data Format [3:0] Reserved [0] CHKSUM 0x0A Autobrite Control Bit Definition 15 0 Reserved 14 0 Reserved [15] Reserved: [14] Reserved: 13 0 SHOW_ROI_BOX 12 0 ROI_EN 11 1 ROI_Polarity 10 1 9 1 8 1 7 1 6 0 Reserved 5 1 4 0 3 0 2 1 1 1 0 1 The Autobrite Control register is used to specify parameters that influence the automatic selection of a gamma code (dynamic range control.) The bits are defined as follows: This bit is reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of this bit. This bit is reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of this bit. Document Number: 001-05325 Rev. ** Page 15 of 20 ACM100 [13] SHOW_ROI_BOX: Writing a ‘1’ to this location will enable the generation of a line around the region of interest that has been defined using registers 6 and 7. This is useful for checking to ensure the region of interest has been set correctly. Writing a ‘0’ to this location will disable this feature. Writing a ‘1’ to this location will enable the ROI feature. Writing a ‘0’ to this location will disable the feature and cause the entire frame to be used for automated control of the Tint and Gamma Writing a ‘1’ to this location will cause the area inside the region of interest to be used to calculate Gamma, Tint and linear remap settings. Writing a ‘0’ to this location will cause the area outside the region of interest to be used. These bits are reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of these bits. [12] ROI_EN: [11] ROI_POLARITY: [10:0] Reserved: 0x0B FOD Control Bit Definition 15 0 14 0 13 0 12 1 11 0 10 0 9 0 8 0 7 0 6 1 5 1 4 1 3 1 2 1 1 1 0 0 Reserved The FOD Control register is used to specify the frame on demand mode desired for the application. Please refer to ECK100 Detailed Product Specification for detailed information on the operation of Frame on Demand and Strobe control features. [15:0] Reserved: These bits are reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of these bits. 0x0C Dark Current (Read Only) Bit Definition 15 14 13 12 11 10 9 8 7 DARK_CURRENT 6 5 4 3 2 1 0 Reserved The Dark Current register can be used to read back the average dark current correction value. This value is related to temperature. The bits are defined as follows: [15:12] Reserved: [11:0] DARK_CURRENT: These bits are reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of these bits. This field reads back the dark current correction factor which can be used to determine to current temperature of the sensor. 0x0C Merge Bins Table Load (Write Only) Bit Definition 15 14 13 12 11 10 9 8 7 6 Q 5 4 3 2 1 0 Reserved The Table load register is used to load an arbitrary Q function. The merge bins algorithm can be controlled by specifying a Q function that indicates how strongly gray levels should be affected by the algorithm. The Q function can be specified in one of two methods. The first method assumes that a maximum Q is specified for gray level zero and that this value is reduced for increasing gray levels at a specified slope until a minimum Q value is reached. The alternative is to manually load a table which will specify a unique Q value for each gray level. Document Number: 001-05325 Rev. ** Page 16 of 20 ACM100 The bits are defined as follows: [15:12] Reserved: Reserved for future use The first time this field is written after a power on or reset (including a soft reset initiated by writing to register 0xF) the Q value will be stored in the table at the location for gray code 0. The second write will store the Q value into location 1 and subsequent writes will continue to increment the storage location. The algorithm uses 512 locations. [11:0] Q: 0x0D Video Status (Read Only) Bit Definition 15 14 Reserved 13 12 11 10 CUR_GAMMA 9 8 7 6 5 4 3 2 1 0 IMAG_AV The Video Status register is a read only register that provides the status of the current image to the user. The bits are defined as follows: [15:13] Reserved: [12:8] CUR_GAMMA: These bits are reserved for future use and should not be set. To ensure compatibility with future releases, we recommend using a read/modify/write operation to preserve the status of these bits. This bit field represents the current gamma code most recently calculated by the Autobrite algorithm. This value is updated as soon as the new value is calculated and there is a two frame latency before they take effect. This bit field represents the current image average most recently calculated by the Autobrite algorithm. [7:0] IMAG_AV: 0x0F Firmware Version/Soft Reset Bit Definition 15 14 13 12 11 10 HW_Ver Definition When Written Reserved When read, the Firmware Version/Soft Reset register is used to determine the revision status of the camera. When written, the register is used to reset the camera. The following defines the fields of this register: Read [15:12] PCB_Ver: [11:8] HW_Ver: [7:4] RTL_Maj_Ver: [3:0] RTL_Min_Ver: Write [15:1] Reserved: [0] RST: These bits are reserved for future use and should not be set. Write ‘0’s to this field. Writing a ‘1’ to this bit will return all registers to the power on state. This field reads back the revision level of the PCB. It is incremented each time the artwork is changed on the PCB in the camera. This field reads back the hardware version of the camera. It starts at zero with each PCB version and is incremented as changes are made to the hardware that do not affect the PCB artwork. This field reads back the major revision code for the firmware in the FPGA. This field is independent of the PCB and HW versions and is incremented each time a major change to the functionality of the FPGA is implemented. This field is reset each time the RTL_Maj_Ver field changes and is incremented each time the firmware is changed. 9 8 7 6 5 4 3 2 1 0 Definition When Read PCB_Ver RTL_Maj_Ver RTL_Min_Ver Document Number: 001-05325 Rev. ** Page 17 of 20 ACM100 Environmental Specifications Specification Value – 40° to +85° C C – 40° to +115 ° C C – 40° to +130 ° C C 100% relative humidity Passenger compartment compliant 3 Passenger compartment compliant 100 mg/m Leather wax, anti-mist spray, cleaning soap, deodorizPassenger compartment compliant er spray, coffee, tea, soft drinks Comment See General Specifications for sensitivity de-rating over temperature. Video performance guaranteed from –40° to +85 ° C C Normal Operating Temperature Degraded Operating Temperature Storage Temperature Humidity Salt Mist Atmosphere Dust Chemical Resistance Performance Specifications The ACM100 module is intended to support a variety of applications, many with differing optical field of view requirements. To facilitate the differences, the ACM100 module is available with a selection of lenses. The following table summarizes the general performance of the camera and at 25oC. Data are for imager (IM103) performance. Performance specifications will vary based on lens selection. Specifications of available lenses are described in later sections. Parameter Value 640H X 480V