B9946CA

B9946 3.3V, 160-MHz, 1:10 Clock Distribution Buffer Product Features • • • • • • • • • 160-MHz Clock Support LVCMOS/LVTTL Compatible Inputs 10 Clock Outputs: Drive up to 20 Clock Lines 1X or 1/2X Configurable Outputs Output Three-state Control 250 ps Maximum Output-to-Output Skew Pin Compatible with MPC946 Industrial Temp. Range: –40°C to +85°C 32-Pin TQFP Package Description The B9946 is a low-voltage clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 10 outputs are 3.3V LVCMOS or LVTTL compatible and can drive two series terminated 50Ω transmission lines. With this capability the B9946 has an effective fanout of 1:20. The B9946 is capable of generating 1X and 1/2X signals from a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:C) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs. The B9946 outputs can also be three-stated via MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs. Block Diagram TCLK_SEL TCLK0 TCLK1 0 1 R 0 1 /1 /2 Pin Configuration MR/OE# VSS QA0 VDDC QA1 VSS QA2 VDDC TCLK_SEL VDD TCLK0 TCLK1 DSELA DSELB DSELC VSS 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 3 QA0:2 DSELA 0 1 3 B9946 9 10 11 12 13 14 15 16 QB0:2 DSELB 0 1 VSS QB0 VDDC QB1 VSS QB2 VDDC VDDC 4 QC0:3 VDDC QC0 VSS QC1 VDDC QC2 VSS QC3 DSELC MR/OE# Cypress Semiconductor Corporation Document #: 38-07077 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 22, 2002 B9946 Pin Description[1] Pin 3, 4 26, 28, 30 19, 21, 23 10, 12, 14, 16 5, 6, 7 1 32 Name TCLK(0,1) QA(2:0) QB(2:0) QC(0:3) DSEL(A:C) TCLK_SEL MR/OE# VDDC VDDC VDDC PWR I/O I, PU O O O I, PD I, PD I, PD Clock Outputs Clock Outputs Clock Outputs Divider Select Inputs. When HIGH, selects ÷2 input divider. When LOW, selects ÷1 input divider. TCLK Select Input. When LOW, TCLK0 clock is selected and when HIGH TCLK1 is selected. Output Enable Input. When asserted LOW, the outputs are enabled and when asserted HIGH, internal flip-flops are reset and the outputs are three-stated. 3.3V Power Supply for Output Clock Buffers 3.3V Power Supply Common Ground Description External Reference/Test Clock Input 9, 13, 17, 18, 22, 25, 29 2 8, 11, 15, 20, 24, 27, 31 VDDC VDD VSS Note: 1. PD = Internal Pull-Down, PU = Internal Pull-Up. Document #: 38-07077 Rev. *C Page 2 of 5 B9946 Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD Protection.............................................. 2 KV Maximum Power Supply: ................................................5.5V Maximum Input Current:..................................................±20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters: VDDC = 3.3V ±10%, VDD = 3.3V ±10%, TA = –40°C to +85°C Parameter VIL VIH IIL IIH VOL VOH IDD Cin Description Input Low Voltage Input High Voltage Input Low Current (@VIL = VSS) Input High Current (@VIL =VDD) Output Low Voltage Output High Voltage Quiescent Supply Current Input Capacitance IOL = 20 mA, Note 4 IOH = –20 mA, VDDC = 3.3V, Note 4 All VDDC and VDD 2.5 1 2 4 Note 3 Conditions Min. VSS 2.0 Typ. Max. 0.8 VDD –100 100 0.4 Unit V V µA µA V V mA pF AC Parameters[5]: VDDC = 3.3V ±10%, VDD = 3.3V ±10%, TA = –40°C to +85°C Parameter Fmax Tpd FoutDC tpZL, tpZH tpLZ, tpHZ Tskew Tskew(pp) Tr/Tf Description Maximum Input Frequency TTL_CLK to Q Delay[6] Output Duty Cycle [6,7] [6] Conditions Min. 160 5.0 Typ. - Max. 11.5 TCYCLE/2 + 1 10 10 250 Unit MHz ns ns ns ns ps ns ns Measured at VDDC/2 TCYCLE/2 – 1 2 2 2.0 Output enable time (all outputs) Output disable time (all outputs) Output-to-Output Skew[6,8] Part-to-Part Skew [9] [8] 4.5 1.0 Output Clocks Rise/Fall Time 0.8V to 2.0V 0.10 Notes: 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 6. Outputs driving 50Ω transmission lines. 7. 50% input duty cycle. 8. Outputs loaded with 30 pF each 9. Part-to-Part skew at a given temperature and voltage. Document #: 38-07077 Rev. *C Page 3 of 5 B9946 Package Drawing and Dimensions 32-Pin TQFP Outline Dimensions Inches Symbol A A1 D Millimeters Max. 0.047 0.006 0.041 0.018 0.030 Min. 0.05 0.95 0.30 0.45 Nom. 9.00 7.00 0.80 BSC 0 0.75 Max. 1.20 0.15 1.05 0.45 Min. 0.002 0.037 0.012 0.018 Nom. 0.354 0.276 0.031 BSC - A2 D D1 b e D1 10° A1 A2 A L e b L Ordering Information Part Number[10] B9946CA Package Type 32-Pin TQFP Production Flow Industrial, –40°C to +85°C Note: 10. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress B9946CA Date Code, Lot # B9946CA Package A = TQFP Revision Device Number Document #: 38-07077 Rev. *C Page 4 of 5 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. B9946 Document Title: B9946 3.3V, 160-MHz, 1:10 Clock Distribution Buffer Document Number: 38-07077 REV. ** *A *B *C ECN NO. 107113 108057 109803 122762 Issue Date 06/06/01 07/03/01 01/31/02 12/22/02 Orig. of Change IKA NDP DSG RBI Description of Change Convert from IMI to Cypress Changed Commercial to Industrial (See page 4) Convert from Word to Frame Add power up requirements to maximum ratings information Document #: 38-07077 Rev. *C Page 5 of 5