B9949
3.3V 160-MHz 1:15 Clock Distribution Buffer
Features
• • • • • • • • • • 160MHz Clock Support LVPECL or LVCMOS/LVTTL Clock Input LVCMOS/LVTTL Compatible Inputs 15 Clock Outputs: Drive up to 30 Clock Lines 1X and 1/2X Configurable Outputs Output Three-state Control 350 ps Maximum Output-to-Output Skew Pin Compatible with MPC949 Industrial Temp. Range: –40°C to +85°C 52-Pin TQFP Package
Description
The B9949 is a low-voltage clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 15 outputs are 3.3V LVCMOS or LVTTL compatible and can drive two series terminated 50Ω transmission lines. With this capability the B9949 has an effective fan-out of 1:30. The B9949 is capable of generating 1X and 1/2X signals from a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:D) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs. The B9949 outputs can also be three-stated via MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs.
Block Diagram
TCLK_SEL TCLK0 (LVTTL) TCLK1 (LVTTL) PECL_CLK PECL_CLK# PCLK_SEL DSELA
0 1
0 0 1 1 /2 R 0 1 /1
2
QA0:1
3
QB0:2
DSELB
0 1
4
QC0:3
DSELC
0 1
6
QD0:5
DSELD MR/OE#
Cypress Semiconductor Corporation Document #: 38-07081 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600 Revised December 21, 2002
B9949
Pin Configuration
52 51 50 49 48 47 46 45 44 43 42 41 40 MR/OE# TCLK_SEL VDD TCLK0 TCLK1 PECL_CLK PECL_CLK# PCLK_SEL DSELA DSELB DSELC DSELD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 NC VSS QC0 VDDC QC1 VSS QC2 VDDC QC3 VSS VSS QD5 NC
14 15 16 17 18 19 20 21 22 23 24 25 26
NC VDDC QB2 VSS QB1 VDDC QB0 VSS VSS QA1 VDDC QA0 VSS
B9949
NC VDDC QD4 VSS QD3 VDDC QD2 VSS QD1 VDDC QD0 VSS NC
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B9949
Pin Description [1]
Pin 6 7 4, 5 49, 51 42, 44, 46 31, 33, 35, 37 16, 18, 20, 22, 24, 28 9, 10, 11, 12 2 Name PECL_CLK PECL_CLK# TCLK(0,1) QA(1,0) QB(2:0) QC(3:0) QD(5:0) DSEL(A:D) TCLK_SEL PCLK_SEL MR_OE# VDDC VDDC VDDC VDDC PWR I/O I, PD I, PU I, PU O O O O I, PD I, PD I, PD I, PD PECL Input Clock. PECL Input Clock. External Reference/Test Clock Input. Clock Outputs. Clock Outputs. Clock Outputs. Clock Outputs. Divider Select Inputs. When HIGH, selects ÷2 input divider. When LOW, selects ÷1 input divider. TCLK Select Input. When LOW, TCLK0 clock is selected and when HIGH TCLK1 is selected. PECL Select Input. When HIGH, PECL clock is selected and when LOW TCLK(0,1) is selected Output Enable Input. When asserted LOW, the outputs are enabled and when asserted HIGH, internal flip-flops are reset and the outputs are three-stated. 3.3V Power Supply for Output Clock Buffers. 3.3V Power Supply Common Ground Description
8
1
17, 21, 25, 32, 36, 41, 45, 50 3 13, 15, 19, 23, 29, 30, 34, 38, 43, 47, 48, 52 14, 26, 27, 39, 40,
VDDC VDD VSS
NC
Not Connected
Note: 1. PD = Internal Pull-Down, PU = Internal Pull-Up.
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B9949
Maximum Ratings[2]
Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD protection ............................................... 2KV Maximum Power Supply: ................................................5.5V Maximum Input Current:...................................................±20mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
DC Parameters: VDDC = 3.3V ±5%, VDD = 3.3V ±5%, TA = –40°C to +85°C
Parameter VIL VIH IIL IIH VPP VCMR VOL VOH IDD Cin Description Input Low Voltage Conditions PECL_CLK, Single Ended All other inputs Input High Voltage PECL_CLK, Single Ended All other inputs Input Low Current (@VIL = VSS) Note 3 Input High Current (@VIL = VDD) Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Output Low Voltage Output High Voltage Quiescent Supply Current Input Capacitance IOL = 20 mA, Note 5 IOH = –20 mA, VDDC = 3.3V, Note 5 All VDDC and VDD 2.5 1 2 4 Note 4 300 VDD – 2.0 Min. 1.49 VSS 2.135 2.0 Typ. Max. 1.825 0.8 2.42 VDD –100 100 1000 VDD – 0.6 0.4 µA µA mV V V V mA pF V Unit V
Notes: 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 5. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
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B9949
AC Parameters[6]: VDDC = 3.3V ±5%, VDD = 3.3V ±5%, TA = –40°C to +85°C
Parameter Fmax Tpd Description Maximum Input Frequency PECL_CLK to Q Delay TCLK to Q FoutDC tpZL, tpZH tpLZ, tpHZ Tskew Tskew (pp) Delay[7] Cycle[7, 8] Measured at VDDC/2
[7] [7]
Conditions
Min. 160 4.0 4.2 TCYCLE/2 –1 2 2
Typ.
Max.
Unit MHz
-
8.6 10.5 TCYCLE/2 + 1 10 10 350
ns
Output Duty
ns ns ns ps ns
Output Enable Time (all outputs) Output Disable Time (all outputs) Output-to-Output Skew Part-to-Part Skew
[10] [7, 9]
Fin
