Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CYW20736S
Bluetooth Low Energy
System-in-Package (SiP) Module
The CYW20736S is a compact, highly integrated Bluetooth Low Energy (BLE) system-in-package (SiP) module. The CYW20736S
SiP includes an embedded BLE antenna, 24 MHz clock, and 512 Kb EEPROM, so only a minimal set of external components is
needed to create a standalone BLE device.
The CYW20736S is designed to accelerate time to market. The Bluetooth stack and several application profiles are built into the
module, allowing customers to focus on their core applications. To further reduce application development time, the CYW20736S
includes integrated software support, with one-click installation of the complete environment and a one-click compile/build/link/load
cycle. All this, coupled with an ultrasmall form factor and support for a wide voltage range, makes the CYW20736S well suited for
virtually any Bluetooth Smart application.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
Cypress Part Number
BCM20736S
CYW20736S
Features
Applications
■
ARM Cortex-M3 microcontroller unit (MCU)
The following profiles are supported in CYW20736S ROM:
■
Embedded 512 Kb EEPROM
■
Battery status
■
Broadcom Serial Control (BSC), SPI, and UART interfaces
■
Blood pressure monitor
■
FCC and CE compliant
■
Find me
■
RoHS compliant, certified lead- and halogen-free
■
Heart rate monitor
■
Moisture Sensitivity Level (MSL) 3 compliant
■
Proximity
■
6.5 mm × 6.5 mm × 1.2 mm Land Grid Array (LGA) 48-pin
package
■
Thermometer
■
Weight scale
■
Time
■
Blood glucose monitor
Additional profiles that can be supported in CYW20736S RAM
include:
Cypress Semiconductor Corporation
Document Number: 002-15224 Rev. *E
•
■
Blood glucose monitor
■
Temperature alarm
■
Location
■
Other custom profiles
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 15, 2017
CYW20736S
Figure 1. CYW20736S BLE SiP Block Diagram
VBAT/VDDIO
CYW20736S
BCM20736S
Antenna
Bandpass
Filter
24 MHz
XTAL
UART
CYW20736S
BCM20736
SPI/I2C
Bluetooth Low Energy
System-on-Chip with
ARM ® Cortex™ M3-based
Microprocessor Core
Infrared
ADC
GPIOs
PWM
EEPROM
512 Kb I2C
32.768 kHz
Oscillator
(optional)
IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website
(http://community.cypress.com/).
Document Number: 002-15224 Rev. *E
Page 2 of 24
CYW20736S
Contents
1. Functional Description................................................. 4
1.1 External Reset....................................................... 4
1.2 32.768 kHz Oscillator ............................................ 4
2. Pin Map and Signal Descriptions................................ 5
3. Electrical Specifications ............................................ 10
4. RF Specifications ....................................................... 11
5. ADC Specifications .................................................... 12
6. Timing and AC Characteristics ................................. 13
6.1 SPI Timing........................................................... 13
Document Number: 002-15224 Rev. *E
6.2 BSC Interface Timing .......................................... 14
6.3 UART Timing....................................................... 15
7. PCB Design and Manufacturing Recommendations 16
7.1 Pad and Solder Mask Opening Dimensions........ 16
7.2 PCB Stencil ......................................................... 17
8. Packaging and Storage Information ......................... 18
9. Mechanical Information ............................................. 20
10. Ordering Information................................................ 22
Document History.......................................................... 23
Page 3 of 24
CYW20736S
1. Functional Description
1.1 External Reset
External reset timing for the CYW20736S is illustrated in Figure 2.
Figure 2. External Reset Timing
Pulse width
>20 µs
RESET_N
Crystal
warm‐up
delay:
~ 5 ms
Baseband Reset
Start reading EEPROM and
firmware boot
Crystal Enable
1.2 32.768 kHz Oscillator
The CYW20736S includes a standard Pierce oscillator. The oscillator circuit includes a comparator with hysteresis on the output to
create a single-ended digital output. The hysteresis eliminates chatter when the input is near the comparator threshold (~100 mV).
The oscillator circuit can is designed for a 32 kHz or 32.768 kHz crystal oscillator, and can also be driven by an external clock input
with a similar frequency. Characteristics for a 32 kHz oscillator are defined in Table 2.
Table 2. 32 kHz Crystal Oscillator Characteristics
Parameter
Output frequency
Frequency tolerance
Start-up time
Symbol
Foscout
Ftol
Tstartup
Conditions
–
Crystal-dependent
–
Min.
Typ.
Max.
Unit
–
32.768
–
kHz
–
100
–
ppm
–
–
500
µs
0.5
–
–
µW
Pdrv
For crystal selection
Crystal series resistance
Rseries
For crystal selection
–
–
70
kΩ
Crystal shunt capacitance
Cshunt
For crystal selection
–
–
1.3
pF
Crystal drive level
Document Number: 002-15224 Rev. *E
Page 4 of 24
CYW20736S
2. Pin Map and Signal Descriptions
The CYW20736S pin map is shown in Figure 3.
Figure 3. CYW20736S (TOP View)
The signal name, type, and description of each pin in the CYW20736S is listed in Table 3 on page 6. The symbols shown under I/O
Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak
internal pull-up resistor and PD = weak internal pull-down resistor), if any.
Document Number: 002-15224 Rev. *E
Page 5 of 24
CYW20736S
Table 3. Pin Descriptions
Pin
Name
I/O Type
1
GPIO: P27
PWM1
I
2
GND
GND
3
VBAT
I
4
GND
GND
GND
5
GND
GND
GND
6
GND
GND
GND
7
GND
GND
GND
8
GND
GND
GND
9
GND
GND
GND
10
Reserved
–
11
GND
GND
GND
12
GND
GND
GND
13
GND
GND
GND
14
GND
GND
GND
15
GND
GND
GND
16
GND
GND
GND
17
GND
GND
GND
18
UART_RX
I
19
UART_TX
O, PU
UART_TX
20
GND
GND
GND
21
SCL
I/O, PU
SCL I/O, PU clock signal for an external I2C device
22
SDA
I/O, PU
SDA I/O, PU data signal for an external I2C device
23
GND
GND
GND
24
GND
GND
GND
25
GPIO: P1
I
Default direction: Input.
After POR state: Input floating.
This pin is tied to the WP pin of the embedded EEPROM.
Requires an external 10K pull-up
26
TMC
I
Test mode control. Pull this pin high to invoke test mode; leave it floating if not used.
This pin is connected to GND through an internal 10 kΩ resistor.
27
RESET_N
I/O PU
Document Number: 002-15224 Rev. *E
Description
Default direction: Input.
After POR state: Input floating.
Drain current: 16 mA
Alternate function: MOSI (master and slave) for SPI_2
GND
Battery supply input.
Leave floating
UART_RX. This pin is pulled low through an internal 10 kΩ resistor.
Active-low system reset with open-drain output
Page 6 of 24
CYW20736S
Table 3. Pin Descriptions (Cont.)
Pin
Name
I/O Type
Description
Default direction: Input.
After POR state: Input floating.
Alternate functions:
28
29
30
GPIO: P0
GND
GPIO: P3
I
GND
I
■
A/D converter input
■
Peripheral UART TX (PUART_TX)
■
MOSI (master and slave) for SPI_2
■
IR_RX
■
60Hz_main
GND
Default direction: Input.
After POR state: Input floating.
Alternate functions:
■
Peripheral UART CTS (PUART_CTS)
■
SPI_CLK (master and slave) for SPI_2
Default direction: Input.
After POR state: Input floating.
Alternate functions:
31
GPIO: P2
I
■
Peripheral UART RX (PUART_RX)
■
SPI_CS (slave only) for SPI_2
■
SPI_MOSI (master only) for SPI_2
Default direction: Input.
After POR state: Input floating.
Alternate functions:
32
33
GPIO: P4
GPIO: P8
I
I
■
Peripheral UART RX (PUART_RX)
■
MOSI (master and slave) for SPI_2.
■
IR_TX
Default direction: Input.
After POR state: Input floating.
Alternate functions: A/D converter input.
Default direction: Input.
After POR state: Input floating.
Alternate functions:
34
GPIO: P33
I
Document Number: 002-15224 Rev. *E
■
A/D converter input
■
MOSI (slave only) for SPI_2
■
Auxiliary clock output (ACLK1)
■
Peripheral UART RX (PUART_RX)
Page 7 of 24
CYW20736S
Table 3. Pin Descriptions (Cont.)
Pin
Name
I/O Type
Description
Default direction: Input.
After POR state: Input floating.
Alternate functions:
35
36
37
38
GPIO: P32
GPIO: P25
GPIO: P24
I
I
I
NC
NC
GPIO: P13
PWM3
I
39
GPIO: P28
PWM2
GPIO: P14
PWM2
I
I
■
A/D converter input
■
SPI_CS (slave only) for SPI_2.
■
Auxiliary clock output (ACLK0)
■
Peripheral UART TX (PUART_TX)
Default direction: Input.
After POR state: Input floating.
Alternate functions:
■
MISO (master and slave) for SPI_2
■
Peripheral UART RX (PUART_RX)
Default direction: Input.
After POR state: Input floating.
Alternate functions:
■
SPI_CLK (master and slave) for SPI_2
■
Peripheral UART TX (PUART_TX)
No Connection (N/C).
Default Direction: Input
After POR State: Input Floating
Drain current: 16 mA
Alternate function: A/D converter input
Default direction: Input.
After POR state: Input floating.
Drain current: 16 mA
Alternate functions:
■
A/D converter input
■
LED1
■
IR_TX
Default direction: Input.
After POR state: Input floating.
Alternate function: A/D converter input
Default direction: Input.
After POR state: Input floating.
Alternate functions:
40
GPIO: P38
I
■
A/D converter input
■
MOSI (master and slave) for SPI_2
■
IR_TX
Default direction: Input.
After POR state: Input floating.
Alternate functions:
41
GPIO: P15
I
Document Number: 002-15224 Rev. *E
■
A/D converter input
■
IR_RX
■
60 Hz_main
Page 8 of 24
CYW20736S
Table 3. Pin Descriptions (Cont.)
Pin
Name
42
GPIO: P26
PWM0
GPIO: P12
I/O Type
I
I
43
XTALO32K
GPIO: P11
O
I
44
Description
Default direction: Input.
After POR state: Input floating.
Drain current: 16 mA
Alternate function: SPI_CS (slave only) for SPI_2
Default direction: Input.
After POR state: Input floating.
Alternate functions:
■
A/D converter input
■
XTALO32K
Low-power oscillator (LPO) output.
Alternate functions:
P12
P26
Default direction: Input.
After POR state: Input floating.
Alternate functions:
■
A/D converter input
■
XTALI32K
Low-power oscillator (LPO) input.
Alternate functions:
XTALI32K
I
■
P11
■
P27
45
GND
GND
GND
46
GND
GND
GND
47
GND
GND
GND
48
GND
GND
GND
Document Number: 002-15224 Rev. *E
Page 9 of 24
CYW20736S
3. Electrical Specifications
Absolute maximum ratings are defined in Table 4.
Table 4. Absolute Maximum Ratings
Min.
Max.
Unit
Supply power
Parameter
NA
3.63
V
Storage temperature
–40
125
°C
0
±2
%
1.62
3.63
V
Voltage ripple
Power supply (VBAT absolute maximum rating)
Power for the CYW20736S module is provided by the host through the power pins.
Table 5. Voltage
Symbol
Parameter
VBAT
Battery voltage
Min.
Typ.
Max.
Unit
1.62
–
3.63
V
Table 6. Current Consumption
Nominal
Maximum
Unit
Receive
Operating Mode
Receiver and baseband are both operating, 100%
Condition
24
28
mA
Transmit
Transmitter and baseband are both operating, 100%
24
28
mA
Sleep
Wake in < 5 ms
55
60
µA
Deep Sleep
Wake on interrupt
2.0
2.5
µA
Note: All measurements taken at 25°C.
Based on the current measurements in Table 6 on page 10, CYW20736S peak power values are:
■
RX: 101.6 mW
■
TX: 101.6 mW
■
Sleep mode: 217.8 µW
■
Deep Sleep mode: 9.1 µW
Document Number: 002-15224 Rev. *E
Page 10 of 24
CYW20736S
4. RF Specifications
CYW20736S receiver specifications are defined in Table 7.
Table 7. Receiver Specifications
Parameter
Mode and Conditions
Min.
Typ.
Max.
Unit
–
2402
–
2480
MHz
–
–94
–
dBm
–10
–
–
dBm
Frequency range
RX sensitivity (standard)
Packets: 200
Payload: PRBS 9
Length: 37 Bytes
Dirty Transmitter: off.
PER: 30.8%
Maximum input
–
Note: All measurements taken at 3.0V (default voltage).
RF transmitter specifications are defined in Table 8.
Table 8. Transmitter Specifications
Parameter
Min.
Typ.
Max.
Unit
Transmitter
a
Frequency range
2402
–
2480
MHz
Output power adjustment range
–20
–
4
dBm
Output power
–
2
–
dBm
Output power variation
–
2.5
–
dB
–
–
±150
kHz
–
–
±50
kHz
–
–
20
kHz/50 µs
Average deviation in payload
(sequence: 00001111)
225
–
275
kHz
Average deviation in payload
(sequence: 10101010)
185
–
–
kHz
–
2
–
MHz
LO Performance
Initial carrier frequency tolerance
Frequency Drift
Frequency drift
Drift rate
Frequency Deviation
Channel spacing
a.
This parameter is taken from the Bluetooth 4.0 specification.
Document Number: 002-15224 Rev. *E
Page 11 of 24
CYW20736S
5. ADC Specifications
CYW20736S ADC specifications are defined in Table 9.
Table 9. ADC Specifications
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Number of input channels
–
–
–
9
–
-
Channel switching rate
fch
–
–
–
133.33
Kch/s
Input signal range
Reference settling time
–
Vinp
–
Charging refsel
Effective, single-ended
0
–
3.63
V
7.5
–
–
µs
–
500
–
kΩ
5
pF
Input resistance
Rinp
Input capacitance
Cinp
–
–
–
Conversion rate
Fc
–
5.859
–
187
kHz
Conversion time
Tc
–
5.35
–
170.7
µs
Resolution
R
–
Absolute voltage measurement error
–
Using on–chip ADC
firmware driver
–
±2
–
%
Current
I
Iavdd1p2 + Iavdd3p3
–
–
1
mA
Power
P
–
1.5
–
mW
–
–
100
nA
–
–
200
µs
Leakage Current
Ileakage
Power-up time
Tpowerup
–
T = 25°C
–
16
Bits
Integral nonlinearity
INL
In the guaranteed
performance range
–1
–
1
LSBa
Differential nonlinearity
DNL
In the guaranteed
performance range
–1
–
1
LSBa
a.
LSBs are expressed at the 10-bit level.
Document Number: 002-15224 Rev. *E
Page 12 of 24
CYW20736S
6. Timing and AC Characteristics
6.1 SPI Timing
SPI interface timing is illustrated in Figure 4 and Figure 5 and defined in Table 10 on page 14.
Figure 4. SPI Timing—Modes 0 and 2
6
SPI_CSN
SPI_CLK
(Mode 0)
1
SPI_CLK
(Mode 2)
2
‐
SPI_MOSI
First Bit
3
Second Bit
4
SPI_MISO
Not Driven
First Bit
Last bit
‐
Last bit
Not Driven
5
Second Bit
Figure 5. SPI Timing—Modes 1 and 3
6
SPI_CSN
SPI_CLK
(Mode 1)
1
SPI_CLK
(Mode 3)
2
SPI_MOSI
‐
Invalid bit
3
First bit
4
SPI_MISO
Not Driven
Invalid bit
Document Number: 002-15224 Rev. *E
First bit
Last bit
‐
Last bit
Not Driven
5
Page 13 of 24
CYW20736S
Table 10. SPI Interface Timing Specifications
Reference
Characteristics
Min.
Typ.
Max.
1
Time from CSN asserted to first clock edge
1 SCK
100
∞
2
Master setup time
–
1/2SCK
–
3
Master hold time
1/2SCK
-
–
4
Slave setup time
–
1/2 SCK
–
5
Slave hold time
1/2 SCK
–
–
6
Time from last clock edge to CSN deasserted
SCK
10 SCK
100
6.2 BSC Interface Timing
BSC interface timing is illustrated in Figure 6 and is defined in Table 11.
Figure 6. BSC Interface Timing
Table 11. BSC Interface Timing Specifications
Reference
Characteristics
Min.
Max.
Unit
–
100, 400, 800, 1000
kHz
650
–
ns
1
Clock frequency
2
START condition setup time
3
START condition hold time
280
–
ns
4
Clock low time
650
–
ns
5
Clock high time
280
–
ns
6
Data input hold time
0
–
ns
7
Data input setup time
100
–
ns
8
STOP condition setup time
280
–
ns
9
Output valid from clock
–
400
ns
10
Bus free time
650
–
ns
Document Number: 002-15224 Rev. *E
Page 14 of 24
CYW20736S
6.3 UART Timing
UART timing is illustrated in Figure 7 and defined in Table 12.
Figure 7. UART Timing
Table 12. UART Timing Specifications
Reference
Characteristics
Min.
Max.
Unit
1
Delay time, UART_CTS_N low to UART_TXD valid
–
24
Baudout cycles
2
Setup time, UART_CTS_N high before midpoint of stop bit
–
10
ns
3
Delay time, midpoint of stop bit to UART_RTS_N high
–
2
Baudout cycles
Document Number: 002-15224 Rev. *E
Page 15 of 24
CYW20736S
7. PCB Design and Manufacturing Recommendations
7.1 Pad and Solder Mask Opening Dimensions
CYW20736S pad and solder mask opening dimensions are defined in Table 13.
Table 13. Pad and Solder Mask Dimensions
Pad Type
Pad Dimensions
Solder Mask Opening Dimensions
Type A
0.6 × 0.25
0.7 × 0.35
Type B
0.55 × 0.3
0.65 × 0.4
Type C
0.4 × 0.4
0.5 × 0.5
Unit
mm
7.1.1 PCB Layout Recommendations
The following layout recommendations are referenced to Figure 8 on page 16.
■
Connect to system ground from side D of the module (pins 13–22).
■
The L-shaped ground plane is required for the embedded BLE antenna. Keep the GND continuous. Do not cut off the GND shape
to accommodate trace routes.
■
An L-shaped ground plane is required. If the L-shaped GND plane is located on the top layer of the PCB, do not place components
on the ground plane. If this cannot be avoided, move the L-shaped ground plane to another layer.
■
Antenna efficiency of 31–41% can be achieved based on the layout in Figure 8 on page 16 and the dimensions listed below. Following
these layout recommendations is expected to yield 50+ meters of usable range; deviating from these recommendations may reduce
the range of the antenna.
❐ D: 4.5 mm (typical)
❐ G, H, S: 3 mm (typical)
❐ L: 3 mm (minimum)
❐ W: 0.4 mm (typical)
■
Route signal traces out of the module from side C (between pins 27 and 30) or side D (between pins 16 and 19) of the module.
Traces can be overlapped to avoid routing through the keep-out area.
■
Do not route traces from side A or side B.
Figure 8. PCB Layout Example
Document Number: 002-15224 Rev. *E
Page 16 of 24
CYW20736S
7.2 PCB Stencil
The recommended PCB stencil is shown in Figure 9 (all measurements in mm). Use an unsolder mask to set the module footprint.
Figure 9. CYW20736S Stencil (Bottom View)
7.2.1 Solder Reflow
The recommended solder reflow profile for the CYW20736S is defined in Figure 10.
Figure 10. Solder Reflow Profile
245°C
Temperature
217°C
200°C
150°C
Pre‐Heating: 90~120 sec.
Soldering: 60~90 sec.
Time
Document Number: 002-15224 Rev. *E
Page 17 of 24
CYW20736S
8. Packaging and Storage Information
The CYW20736S is available in a tape and reel package and is shipped in an ESD-protected moisture-resistant (MSL-3) bag as shown
in Figure 11. The storage temperature range is –40°C to +125°C.
Figure 11. CYW20736S ESD/Moisture Packaging
The moisture sensitivity label on the CYW20736S shipping bag is shown in Figure 12 on page 19.
Document Number: 002-15224 Rev. *E
Page 18 of 24
CYW20736S
Figure 12. CYW20736S Moisture Sensitivity Label
Figure 13 shows the location of pin 1 on the CYW20736S relative to its orientation on the tape packaging.
Figure 13. CYW20736S Tape and Reel Pin 1 Location
Document Number: 002-15224 Rev. *E
Page 19 of 24
CYW20736S
9. Mechanical Information
Package dimensions for the CYW20736S are shown in Figure 14.
Figure 14. CYW20736S Package Dimensions
Additional CYW20736S package dimensions are shown in Figure 15 on page 21.
Document Number: 002-15224 Rev. *E
Page 20 of 24
CYW20736S
Figure 15. CYW20736S Pin Dimensions (Bottom View)
Document Number: 002-15224 Rev. *E
Page 21 of 24
CYW20736S
10. Ordering Information
Table 14. Ordering Information
Part Number
CYW20736S
Document Number: 002-15224 Rev. *E
Package
Operating Temperature
Humidity
48-pin LGA
–40°C to +85°C
95% max., noncondensing
Page 22 of 24
CYW20736S
Document History
Document Title: CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module
Document Number: 002-15224
Revision
ECN
**
–
*A
–
Orig. of
Change
Submission
Date
04/18/2014
Description of Change
MMP20736E-TRM100-R
Initial release.
MMP20736S-TRM101-R
–
07/15/2014
Updated:
• Pin 33 and pin 38 descriptions; see Table 3: “Pin Descriptions,” on page 7and 8.
MMP20736S-TRM102-R
Updated:
*B
–
–
09/11/2014
Table 3: “Pin Descriptions,” on page 8: Pin 37.
Removed:
•
Appendix A: “Acronyms and Abbreviations,” on page 28.
MMP20736S-TRM103-R
*C
–
UTSV
04/11/2016
Updated:
*D
5445386
UTSV
09/23/2016
Updated to Cypress Template.
*E
5967849
AESATMP9
11/15/2017
Updated logo and copyright.
•
Document Number: 002-15224 Rev. *E
Table 6: “Current Consumption,” on page 10.
Page 23 of 24
CYW20736S
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
®
®
ARM Cortex Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
cypress.com/pmic
Touch Sensing
Cypress Developer Community
Forums | WICED IoT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
cypress.com/usb
cypress.com/wireless
24
© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-15224 Rev. *E
Revised November 15, 2017
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