BCM43353LIUBGT

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com PRELIMINARY CYW43353 Single-Chip 5G MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and Industrial Applications General Description The Cypress® CYW43353 single-chip device provides the highest level of integration for Automotive and Industrial connectivity systems with integrated single-stream IEEE 802.11ac MAC/baseband/radio, Bluetooth 4.1. In IEEE 802.11ac mode, the WLAN operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz channels for data rates up to 433.3 Mbps. In addition, all the rates specified in IEEE 802.11a/b/g/n are supported. Included on-chip are 2.4 GHz and 5 GHz transmit amplifiers, and receive low-noise amplifiers. Optional external PAs, LNAs, and antenna diversity are also supported. The CYW43353 offers an SDIO v3.0 interface for high speed 802.11ac connectivity. The Bluetooth host controller is interfaced over a 4-wire high speed UART and includes PCM for audio. The CYW43353 brings the latest mobile connectivity technology to automotive infotainment, telematics, rear seat entertainment, and industrial applications. Offering automotive Grade 3 (-40C to +85C) temperature performance, the CYW43353 is tested to AECQ100 environmental stress guidelines and manufactured in ISO9001 and TS16949 certified facilities. The CYW43353 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. In addition, coexistence support for external radios (such as LTE cellular, GPS, and WiMAX) is provided via an external interface. As a result, enhanced overall quality for simultaneous voice, video, and data transmission is achieved. Features IEEE 802.11x Key Features ■ IEEE 802.11ac compliant. ■ Single-stream spatial multiplexing up to 433.3 Mbps data rate. ■ Supports 20, 40, and 80 MHz channels with optional SGI (256 QAM modulation). ■ Full IEEE 802.11a/b/g/n legacy compatibility with enhanced performance. ■ Supports Rx space-time block coding (STBC) ■ Supports IEEE 802.11ac/n beamforming. ■ On-chip power amplifiers and low-noise amplifiers for both bands. ■ ■ Support for optional front-end modules (FEM) with external PAs and LNAs ■ Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN. ■ ■ Internal fractional nPLL allows support for a wide range of reference clock frequencies Supports IEEE 802.15.2 external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as LTE, GPS, or WiMAX ■ Supports standard SDIO v3.0 (including DDR50 mode at 50 MHz and SDR104 mode at 208 MHz, 4-bit and 1-bit), and gSPI (48 MHz) host interfaces. ■ Backward compatible with SDIO v2.0 host interfaces. Cypress Semiconductor Corporation Document Number: 002-14949 Rev. *H • ■ Integrated ARMCR4™ processor with tightly coupled memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field upgrade with future features. On-chip memory includes 768 KB SRAM and 640 KB ROM. OneDriver™ software architecture for easy migration from existing embedded WLAN and Bluetooth devices as well as future devices. Bluetooth Key Features ■ Complies with Bluetooth Core Specification Version 4.1 for automotive and industrial applications with provisions for supporting future specifications. ■ Bluetooth Class 1 or Class 2 transmitter operation. ■ Supports extended synchronous connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets. ■ Adaptive frequency hopping (AFH) for reducing radio frequency interference. ■ Interface support, host controller interface (HCI) using a high-speed UART interface and PCM for audio data. ■ Supports multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound. ■ Automatic frequency detection for standard crystal and TCXO values. 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 24, 2021 PRELIMINARY CYW43353 ■ Supports low energy host wake-up for long term system sleep capability. ■ Security: ❐ General Features ■ Supports battery voltage range from 3.0V to 4.8 supplies with internal switching regulator. ❐ ■ Programmable dynamic power management ❐ ■ OTP: 502 bytes of user-accessible memory ■ Nine GPIOs ■ Package options: ❐ ❐ ■ 145 ball WLBGA (4.87 mm × 5.413 mm, 0.4 mm pitch) WPA™ and WPA2™ (Personal) support for powerful encryption and authentication AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility Reference WLAN subsystem provides Cisco® Compatible Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0) Reference WLAN subsystem provides Wi-Fi Protected Setup (WPS) Worldwide regulatory support: Global products supported with worldwide homologated design. Figure 1: Functional Block Diagram VIO VBAT WLAN Host I/F External Coexistence I/F 5 GHz WLAN TX WL_REG_ON 5 GHz WLAN RX SDIO*/SPI 2.4 GHz WLAN TX COEX 2.4 GHz WLAN/BT RX CLK_REQ FEM or T/R Switch CYW43353 Bluetooth TX FEM or T/R Switch CBF BT_REG_ON UART Bluetooth Host I/F I2S PCM BT_DEV_WAKE BT_HOST_WAKE Document Number: 002-14949 Rev. *H Page 2 of 112 PRELIMINARY CYW43353 Contents 1. Overview ............................................................ 5 1.1 Overview ............................................................. 5 1.2 Features .............................................................. 7 1.3 Standards Compliance ........................................ 7 1.4 Automotive and Industrial Usage Model ............. 8 2. Power Supplies and Power Management ....... 9 2.1 Power Supply Topology ...................................... 9 2.2 PMU Features ..................................................... 9 2.3 WLAN Power Management ............................... 11 2.4 PMU Sequencing .............................................. 11 2.5 Power-Off Shutdown ......................................... 12 2.6 Power-Up/Power-Down/Reset Circuits ............. 12 3. Frequency References ................................... 13 3.1 Crystal Interface and Clock Generation ............ 13 3.2 External Frequency Reference ......................... 14 3.3 Frequency Selection ......................................... 15 3.4 External 32.768 kHz Low-Power Oscillator ....... 16 4. Bluetooth Subsystem Overview .................... 17 5.8 Fast Connection (Interlaced Page and Inquiry Scans) ................................................................25 6. Microprocessor and Memory Unit for Bluetooth ......................................................... 26 6.1 RAM, ROM, and Patch Memory .........................26 6.2 Reset ..................................................................26 7. Bluetooth Peripheral Transport Unit............. 27 7.1 PCM Interface ....................................................27 7.1.1 Slot Mapping ...........................................27 7.1.2 Frame Synchronization ...........................27 7.1.3 Data Formatting ......................................27 7.1.4 Wideband Speech Support .....................27 7.1.5 Multiplexed Bluetooth Over PCM ...........27 7.1.6 PCM Interface Timing .............................29 7.2 UART Interface ..................................................33 7.3 I2S Interface .......................................................35 7.3.1 I2S Timing ...............................................35 8. WLAN Global Functions................................. 38 8.1 WLAN CPU and Memory Subsystem ................38 8.2 One-Time Programmable Memory .....................38 4.1 Features ............................................................ 17 8.3 GPIO Interface ...................................................38 4.2 Bluetooth Radio ................................................. 18 4.2.1 Transmit ................................................. 18 4.2.2 Digital Modulator .................................... 18 4.2.3 Digital Demodulator and Bit Synchronizer 18 4.2.4 Power Amplifier ..................................... 18 4.2.5 Receiver ................................................ 18 4.2.6 Digital Demodulator and Bit Synchronizer 18 4.2.7 Receiver Signal Strength Indicator ........ 19 4.2.8 Local Oscillator Generation ................... 19 4.2.9 Calibration ............................................. 19 8.4 External Coexistence Interface ..........................39 8.5 UART Interface ..................................................39 8.6 JTAG Interface ...................................................39 5. Bluetooth Baseband Core.............................. 20 5.1 Bluetooth 4.1 Features ...................................... 20 5.2 Bluetooth Low Energy ....................................... 20 5.3 Link Control Layer ............................................. 21 5.4 Test Mode Support ............................................ 21 5.5 Bluetooth Power Management Unit .................. 22 5.5.1 RF Power Management ......................... 22 5.5.2 Host Controller Power Management ..... 22 5.5.3 BBC Power Management ...................... 23 5.5.4 Wideband Speech ................................. 24 5.5.5 Packet Loss Concealment ..................... 24 5.5.6 Audio Rate-Matching Algorithms ........... 25 5.5.7 Codec Encoding .................................... 25 5.5.8 Multiple Simultaneous A2DP Audio Streams ................................................. 25 5.6 Adaptive Frequency Hopping ............................ 25 5.7 Advanced Bluetooth/WLAN Coexistence .......... 25 Document Number: 002-14949 Rev. *H 9. WLAN Host Interfaces .................................... 40 9.1 SDIO v3.0 ...........................................................40 9.1.1 SDIO Pins ...............................................40 9.2 Generic SPI Mode ..............................................41 9.2.1 SPI Protocol ............................................42 9.2.2 gSPI Host-Device Handshake ................46 9.2.3 Boot-Up Sequence .................................46 10. Wireless LAN MAC and PHY.......................... 49 10.1 IEEE 802.11ac MAC ..........................................49 10.1.1 PSM ........................................................50 10.1.2 WEP .......................................................50 10.1.3 TXE .........................................................50 10.1.4 RXE ........................................................50 10.1.5 IFS ..........................................................51 10.1.6 TSF .........................................................51 10.1.7 NAV ........................................................51 10.2 IEEE 802.11ac PHY ...........................................51 11. WLAN Radio Subsystem ............................... 53 11.1 Receiver Path .....................................................53 11.2 Transmit Path .....................................................53 11.3 Calibration ..........................................................53 Page 3 of 112 PRELIMINARY CYW43353 12. Pinout and Signal Descriptions..................... 55 16.5 LNLDO ...............................................................90 12.1 Ball Maps .......................................................... 55 17. System Power Consumption ......................... 91 12.2 Signal Descriptions ........................................... 56 17.1 WLAN Current Consumption ..............................91 12.3 WLAN GPIO Signals and Strapping Options .... 61 12.3.1 Multiplexed Bluetooth GPIO Signals ..... 62 17.2 Bluetooth Current Consumption .........................93 12.4 GPIO/SDIO Alternative Signal Functions .......... 64 12.5 I/O States .......................................................... 65 13. DC Characteristics.......................................... 68 13.1 Absolute Maximum Ratings .............................. 68 13.2 Environmental Ratings ...................................... 68 13.3 Electrostatic Discharge Specifications .............. 69 13.4 Recommended Operating Conditions and DC Characteristics .................................................. 69 18. Interface Timing and AC Characteristics ..... 94 18.1 SDIO/gSPI Timing ..............................................94 18.1.1 SDIO Default Mode Timing .....................94 18.1.2 SDIO High-Speed Mode Timing .............95 18.1.3 SDIO Bus Timing Specifications in SDR Modes .....................................................96 18.1.4 SDIO Bus Timing Specifications in DDR50 Mode 99 18.1.5 gSPI Signal Timing ...............................102 18.2 JTAG Timing ....................................................102 14. Bluetooth RF Specifications .......................... 71 19. Power-Up Sequence and Timing ................. 103 15. WLAN RF Specifications ................................ 77 15.2 2.4 GHz Band General RF Specifications ......... 77 19.1 Sequencing of Reset and Regulator Control Signals .............................................................103 19.1.1 Description of Control Signals ..............103 19.1.2 Control Signal Timing Diagrams ...........103 15.3 WLAN 2.4 GHz Receiver Performance Specifications .................................................... 78 20. Package Information .................................... 106 15.1 Introduction ....................................................... 77 15.4 WLAN 2.4 GHz Transmitter Performance Specifications .................................................... 81 20.1 Package Thermal Characteristics ....................106 20.2 Junction Temperature Estimation and PSIJT Versus THETAJC ..............................................106 15.5 WLAN 5 GHz Receiver Performance Specifications .................................................... 82 20.3 Environmental Characteristics .........................106 15.6 WLAN 5 GHz Transmitter Performance Specifications .................................................... 85 21. Mechanical Information................................ 107 15.7 General Spurious Emissions Specifications ...... 86 22. Ordering Information.................................... 109 16. Internal Regulator Electrical Specifications. 86 23. Additional Information ................................. 109 16.1 Core Buck Switching Regulator ........................ 86 23.1 Acronyms and Abbreviations ...........................109 16.2 3.3V LDO (LDO3P3) ......................................... 87 16.3 2.5V LDO (BTLDO2P5) ..................................... 88 16.4 CLDO ................................................................ 89 Document Number: 002-14949 Rev. *H 23.2 References .......................................................109 23.3 IoT Resources ..................................................109 Document History Page ............................................... 110 Sales, Solutions, and Legal Information .................... 112 Page 4 of 112 PRELIMINARY CYW43353 1. Overview 1.1 Overview The Cypress CYW43353 single-chip device provides the highest level of integration for automotive and industrial wireless connectivity systems, with integrated IEEE 802.11 a/b/g/n/ac MAC/baseband/radio, and Bluetooth 4.1 + enhanced data rate (EDR). It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for platform flexibility in size, form, and function. The following figure shows the interconnect of all the major physical blocks in the CYW43353 and their associated external interfaces, which are described in greater detail in the following sections. Document Number: 002-14949 Rev. *H Page 5 of 112 PRELIMINARY CYW43353 Figure 1. CYW43353 Block Diagram SECI UART and GCI-GPIOs TCM RAM768KB ROM640KB SDIOD I2S PCM ARMCM3 Registers WLAN Master Slave JTAG Master GPIO Timers WD Pause ARMCR4 WLAN BT Access AXI2AHB AHB2AXI Chip Common OTP RX/TX BLE AHB2APB PMU WLAN RAM Sharing WL_HOST_WAKE WL_DEV_WAKE JTAG Other GPIOs LCU APU BlueRF SDIO 3.0 NIC-301 AXI Backplane UART DMA WL_REG_ON BT_REG_ON VBAT RAM ROM AHB Bus Matrix BT_HOST_WAKE BT_DEV_WAKE UART PCM I2S Other GPIOs Port Control GCI AXI2APB DOT11MAC (D11) GCI Coex I/F Shared LNA Control and Other Coex I/Fs RF Switch Controls 1 x 1 802.11ac PHY 2.4 GHz/5 GHz 802.11ac Dual-Band Radio Modem XTAL Bluetooth RF 32 kHz External LPO BT PA WLAN Bluetooth CLB FEM or SP3T 2.4 GHz FEM or SPDT 5 GHz Diplexer Document Number: 002-14949 Rev. *H Page 6 of 112 PRELIMINARY CYW43353 1.2 Features The CYW43353 supports the following features: ■ IEEE 802.11a/b/g/n/ac dual-band radio with virtual-simultaneous dual-band operation ■ Bluetooth v4.1 + EDR with integrated Class 1 PA ■ Concurrent Bluetooth and WLAN operation ■ On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality ■ WLAN host interface options: ❐ ❐ ■ SDIO v3.0 (1-bit/4-bit)—up to 208 MHz clock rate in SDR104 mode gSPI—up to 48 MHz clock rate BT host digital interface (which can be used concurrently with the above interfaces): ❐ UART (up to 4 Mbps) ■ ECI—enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN receptions ■ I2S/PCM for BT audio ■ HCI high-speed UART (H4, H4+, H5) transport support ■ Wideband speech support (16 bits linear data, MSB first, left justified at 4K samples/s for transparent air coding, both through I2S and PCM interface) ■ Bluetooth SmartAudio® technology improves voice and music quality for automotive and industrial applications ■ Bluetooth low-power inquiry and page scan ■ Bluetooth Low Energy (BLE) support ■ Bluetooth Packet Loss Concealment (PLC) ■ Bluetooth Wide Band Speech (WBS) ■ Audio rate-matching algorithms 1.3 Standards Compliance The CYW43353 supports the following standards: ■ Bluetooth 2.1 + EDR ■ Bluetooth 3.0 ■ Bluetooth 4.1 (Bluetooth Low Energy) ■ IEEE802.11ac single-stream mandatory and optional requirements for 20 MHz, 40 MHz, and 80 MHz channels ■ IEEE 802.11n—Handheld Device Class (Section 11) ■ IEEE 802.11a ■ IEEE 802.11b ■ IEEE 802.11g ■ IEEE 802.11d ■ IEEE 802.11h ■ IEEE 802.11i Document Number: 002-14949 Rev. *H Page 7 of 112 PRELIMINARY CYW43353 ■ Security: ❐ WEP ❐ WPA™ Personal ❐ ❐ ❐ ❐ ❐ ❐ ❐ ■ Proprietary Protocols: ❐ ❐ ❐ ❐ ■ WPA2™ Personal WMM WMM-PS (U-APSD) WMM-SA AES (Hardware Accelerator) TKIP (HW Accelerator) CKIP (SW Support) CCXv2 CCXv3 CCXv4 CCXv5 IEEE 802.15.2 Coexistence Compliance—on silicon solution compliant with IEEE 3 wire requirements The CYW43353 will support the following future drafts/standards: ■ IEEE 802.11r—Fast Roaming (between APs) ■ IEEE 802.11w—Secure Management Frames ■ IEEE 802.11 Extensions: ❐ ❐ ❐ ❐ IEEE 802.11e QoS Enhancements (as per the WMM® specification is already supported) IEEE 802.11h 5 GHz Extensions IEEE 802.11i MAC Enhancements IEEE 802.11k Radio Resource Measurement 1.4 Automotive and Industrial Usage Model The CYW43353 incorporates a number of unique features to simplify integration into automotive and industrial platforms. Its flexible PCM and UART interfaces enable it to transparently connect with existing platform circuits. In addition, the TCXO and LPO inputs allow the use of existing automotive and industrial features to further minimize the size, power, and cost of the complete system. ■ The PCM interface provides multiple modes of operation to support both master and slave as well as hybrid interfacing to single or multiple external codec devices. ■ The UART interface supports hardware flow control with tight integration to power-control sideband signaling to support the lowest power operation. ■ The crystal oscillator interface accommodates any of the typical reference frequencies used by mobile platform architectures. ■ The highly linear design of the radio transceiver ensures that the device has the lowest spurious emissions output regardless of the state of operation. It has been fully characterized in the global cellular bands. ■ The transceiver design has excellent blocking and intermodulation performance in the presence of a cellular transmission (LTE, GSM®, GPRS, CDMA, WCDMA, or iDEN). The CYW43353 is designed to directly interface with new and existing automotive and industrial platform designs. Document Number: 002-14949 Rev. *H Page 8 of 112 PRELIMINARY CYW43353 2. Power Supplies and Power Management 2.1 Power Supply Topology One buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43353. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs. A single VBAT (3.0V to 4.8 DC maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the CYW43353. Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective section out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off and on based on the dynamic demands of the digital baseband. The CYW43353 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 and LPLDO2 (which are low-power linear regulators that are supplied by the system VIO supply) provide the CYW43353 with all the voltages it requires, further reducing leakage currents. 2.2 PMU Features ■ VBAT to 1.35V (275 mA nominal, 600 mA maximum) Core-Buck (CBUCK) switching regulator ■ VBAT to 3.3V (200 mA nominal, 450 mA maximum) LDO3P3 ■ VBAT to 2.5V (15 mA nominal, 70 mA maximum) BTLDO2P5 ■ 1.35V to 1.2V (100 mA nominal, 150 mA maximum) LNLDO ■ 1.35V to 1.2V (175 mA nominal, 300 mA maximum) CLDO with bypass mode for deep-sleep ■ Additional internal LDOs (not externally accessible) The following figure shows the regulators and a typical power topology. Document Number: 002-14949 Rev. *H Page 9 of 112 PRELIMINARY CYW43353 Figure 2. Typical Power Topology for CYW43353 Shaded areas are internal to the BCM 43353 Internal LNLDO 80 mA Internal LNLDO 80 mA Internal VCOLDO 80 mA Internal LNLDO 80 mA 1.2V XTAL LDO 30 mA 1.2V WL RF – AFE 1.2V WL RF – TX (2.4 GHz, 5 GHz) 1.2V WL RF – LOGEN (2.4 GHz, 5 GHz) 1.2V WL RF – RX/LNA (2.4 GHz, 5 GHz) WL RF – XTAL WL RF – RFPLL PFD/MMD LNLDO 100 mA 1.2V BT RF DFE/DFLL WL_REG_ON BT_REG_ON VBAT PLL/RXTX Core Buck  Regulator CBUCK Peak 600 mA Average 275 mA WLAN BBPLL/DFLL 1.35V WLAN/BT/CLB/Top, always on WL OTP VDDIO LPLDO1 3 mA 1.1V CLDO Peak 300 mA Average 175 mA (Bypass in deep  sleep) WL PHY 1.2V– 1.1V WL DIGITAL BT DIGITAL WL/BT SRAMs VDDIO BTLDO2P5 Peak 70 mA Average 15 mA 2.5V MEMLPLDO 3 mA 0.9V BT CLASS 1 PA WL PA/PAD (2.4 GHz, 5 GHz) VDDIO_RF Internal LNLDO 25 mA Internal LNLDO 8 mA Document Number: 002-14949 Rev. *H 2.5V 3.3V 2.5V LDO3P3 Peak 800–450 mA Average 200 mA WL OTP 3.3V WL RF – VCO WL RF – CP Page 10 of 112 PRELIMINARY CYW43353 2.3 WLAN Power Management All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW43353 integrated RAM is a high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the CYW43353 includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43353 into various power management states appropriate to the current environment and activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock frequency) in the PMU sequencer are used to turn on and turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible. The CYW43353 WLAN power states are described as follows: ■ Active mode— All WLAN blocks in the CYW43353 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. ■ Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43353 remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are shut down to reduce active power consumption to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current. ■ Deep-sleep mode—Most of the chip, including both analog and digital domains, and most of the regulators are powered off. Logic states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is powered off. Upon a wake-up event triggered by the PMU timers, an external interrupt, or a host resume through the SDIO bus, logic states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization. ■ Power-down mode—The CYW43353 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic reenabling the internal regulators. 2.4 PMU Sequencing The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system resources based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Resource requests may come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. Each resource is in one of four states (enabled, disabled, transition_on, and transition_off) and has a timer that contains 0 when the resource is enabled or disabled and a nonzero value in the transition states. The timer is loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. Document Number: 002-14949 Rev. *H Page 11 of 112 PRELIMINARY CYW43353 During each clock cycle, the PMU sequencer performs the following actions: ■ Computes the required resource set based on requests and the resource dependency table. ■ Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource and inverts the ResourceState bit. ■ Compares the request with the current resource status and determines which resources must be enabled or disabled. ■ Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents. ■ Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. 2.5 Power-Off Shutdown The CYW43353 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. When the CYW43353 is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the CYW43353 to be effectively off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected to the I/O. During a low-power shut-down state, the provided VDDIO remains applied to the CYW43353, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the CYW43353 to be fully integrated in an embedded device and take full advantage of the lowest power-savings modes. When the CYW43353 is powered on from this state, it is the same as a normal power-up, and the device does not retain any information about its state from before it was powered down. 2.6 Power-Up/Power-Down/Reset Circuits The CYW43353 has two signals (see Table 1) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 19.: “Power-Up Sequence and Timing”. Table 1. Power-Up/Power-Down/Reset Control Signals Signal Description WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal CYW43353 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal CYW43353 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 k pulldown resistor that is enabled by default. It can be disabled through programming. Document Number: 002-14949 Rev. *H Page 12 of 112 PRELIMINARY CYW43353 3. Frequency References An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference may be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. 3.1 Crystal Interface and Clock Generation The CYW43353 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator, including all external components, is shown in Figure 3. Consult the reference schematics for the latest configuration and recommended components. Figure 3. Recommended Oscillator Configuration C * WRF_XTAL_IN 37.4 MHz C * X ohms * WRF_XTAL_OUT * Values determined by crystal drive level. See reference schematics for details.  A fractional-N synthesizer in the CYW43353 generates the radio frequencies, clocks, and data/packet timing, enabling the CYW43353 to operate using a wide selection of frequency references. For SDIO applications, the recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal interface are listed in Table 2. Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Cypress for details. Document Number: 002-14949 Rev. *H Page 13 of 112 PRELIMINARY CYW43353 3.2 External Frequency Reference As an alternative to a crystal, an external precision frequency reference can be used. The recommended default frequency is 37.4 MHz. This must meet the phase noise requirements listed in Table 2. If used, the external clock should be connected to the WRF_XTAL_IN pin through an external 1000 pF coupling capacitor, as shown in Figure 4. The internal clock buffer connected to this pin will be turned off when the CYW43353 goes into sleep mode. When the clock buffer turns on and off, there will be a small impedance variation. Power must be supplied to the WRF_XTAL_BUCK_VDD1P5 pin. Figure 4. Recommended Circuit to Use with an External Reference Clock 1000 pF Reference  Clock WRF_XTAL_IN NC WRF_XTAL_OUT Table 2. Crystal Oscillator and External Clock—Requirements and Performance External Frequency Reference2 3 Crystal1 Parameter Conditions/Notes Min. Typ. Max. Min. Typ. Max. Frequency 2.4 GHz and 5 GHz bands, IEEE 802.11ac operation 35 37.4 38.4 – 37.4 – Frequency 5 GHz band, IEEE 802.11n operation only 19 37.4 38.4 35 37.4 38.4 Frequency 2.4 GHz band IEEE 802.11n operation, and both bands legacy 802.11a/b/g operation only Frequency tolerance over the lifetime of the equipment, including Without trimming –20 – Crystal load capacitance – – ESR – – Drive level External crystal must be able to tolerate this drive level. Input impedance (WRF_XTAL_IN) Units MHz Ranges between 19 MHz and 38.4 MHz MHz 4 20 –20 – 20 ppm 12 – – – – pF – 60 – – – Ω 200 – – – – – µW Resistive – – – 30k 100k – Ω Capacitive – – 7.5 – – 7.5 pF WRF_XTAL_IN input low level DC-coupled digital signal – – – 0 – 0.2 V WRF_XTAL_IN input high level DC-coupled digital signal – – – 1.0 – 1.26 V WRF_XTAL_IN input voltage (see Figure 4) AC-coupled analog signal – – – 1000 – 1200 mVp-p temperature5 Duty cycle Phase noise6 (IEEE 802.11b/g) 37.4 MHz clock – – – 40 50 60 % 37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz Document Number: 002-14949 Rev. *H Page 14 of 112 PRELIMINARY CYW43353 Table 2. Crystal Oscillator and External Clock—Requirements and Performance (Cont.) External Frequency Reference2 3 Crystal1 Parameter Conditions/Notes Min. Typ. Max. Min. Typ. Max. Units Phase noise6 37.4 MHz clock at 10 kHz offset – – – – – –137 dBc/Hz (IEEE 802.11a) 37.4 MHz clock at 100 kHz offset – – – – – –144 dBc/Hz Phase noise6 37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz (IEEE 802.11n, 2.4 GHz) 37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz 37.4 MHz clock at 10 kHz offset – – – – – –142 dBc/Hz (IEEE 802.11n, 5 GHz) 37.4 MHz clock at 100 kHz offset – – – – – –149 dBc/Hz Phase noise6 37.4 MHz clock at 10 kHz offset – – – – – –148 dBc/Hz (IEEE 802.11ac, 5 GHz) 37.4 MHz clock at 100 kHz offset – – – – – –155 dBc/Hz Phase noise6 1. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT. 2. See External Frequency Reference for alternative connection methods. 3. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. 4. The frequency step size is approximately 80 Hz. 5. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications. 6. Assumes that external clock has a flat phase-noise response above 100 kHz. 3.3 Frequency Selection Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard mobile platform reference frequencies of 19.2, 19.8, 24, 26, 33.6, 37.4, and 38.4 MHz, but also other frequencies in this range with an approximate resolution of 80 Hz. The CYW43353 must have the reference frequency set correctly in order for any of the UART or PCM interfaces to function correctly, since all bit timing is derived from the reference frequency. Note: he fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default require support to be added in the driver plus additional, extensive system testing. Contact Cypress for details. The reference frequency for the CYW43353 may be set in the following ways: ■ Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency. ■ Autodetect any of the standard handset reference frequencies using an external LPO clock. For applications where the reference frequency is one of the standard frequencies commonly used, the CYW43353 automatically detects the reference frequency and programs itself to the correct reference frequency. In order for automatic frequency detection to work correctly, the CYW43353 must have a valid and stable 32.768 kHz LPO clock that meets the requirements listed in Table 3 and is present during power-on reset. Document Number: 002-14949 Rev. *H Page 15 of 112 PRELIMINARY CYW43353 3.4 External 32.768 kHz Low-Power Oscillator The CYW43353 uses a secondary low-frequency clock for low-power-mode timing. An external 32.768 kHz precision oscillator is required. Use a precision external 32.768 kHz clock that meets the requirements listed in Table 3. Table 3. External 32.768 kHz Sleep Clock Specifications Parameter LPO Clock Units Nominal input frequency 32.768 kHz Frequency accuracy ±200 ppm Duty cycle 30–70 % Input signal amplitude 200–1800 mV, p-p Signal type Square-wave or sine-wave – >100k 0.35T VH = 2.0V SCK thtr > 0 VL = 0.8V totr < 0.8T SD and WS T = Clock period Ttr = Minimum allowed clock period for transmitter T = Ttr * tRC is only relevant for transmitters in slave mode. Document Number: 002-14949 Rev. *H Page 36 of 112 PRELIMINARY CYW43353 Figure 15. I2S Receiver Timing T tLC > 0.35T tHC > 0.35 VH = 2.0V SCK VL = 0.8V tsr > 0.2T thr > 0 SD and WS T = Clock period Tr = Minimum allowed clock period for transmitter T > Tr Document Number: 002-14949 Rev. *H Page 37 of 112 PRELIMINARY CYW43353 8. WLAN Global Functions 8.1 WLAN CPU and Memory Subsystem The CYW43353 WLAN section includes an integrated ARM Cortex-R4™ 32-bit processor with internal RAM and ROM. The ARM Cortex-R4 is a low-power processor that features low gate count, low interrupt latency, and low-cost debug capabilities. It is intended for deeply embedded applications that require fast interrupt response features. Delivering more than 30% performance gain over ARM7TDMI, the ARM Cortex-R4 implements the ARM v7-R architecture with support for the Thumb®-2 instruction set. At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit devices on MIPS/µW. It supports integrated sleep modes. Using multiple technologies to reduce cost, the ARM Cortex-R4 offers improved memory utilization, reduced pin overhead, and reduced silicon area. It supports independent buses for Code and Data access (ICode/DCode and System buses), and extensive debug features including real time trace of program execution. On-chip memory for the CPU includes 768 KB SRAM and 640 KB ROM. 8.2 One-Time Programmable Memory Various hardware configuration parameters may be stored in an internal One-Time Programmable (OTP) memory, which is read by the system software after device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC address can be stored, depending on the specific board design. Customer accessible OTP memory is 502 bytes. The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with the Cypress WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. 8.3 GPIO Interface The following number of general-purpose I/O (GPIO) pins are available on the WLAN section of the CYW43353 that can be used to connect to various external devices: ■ WLBGA package – 9 GPIOs Upon power up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via the GPIO control register. In addition, the GPIO pins can be assigned to various other functions (see Table 21, “CYW43353 GPIO/ SDIO Alternative Signal Functions,”). Document Number: 002-14949 Rev. *H Page 38 of 112 PRELIMINARY CYW43353 8.4 External Coexistence Interface An external handshake interface is available to enable signaling between the device and an external co-located wireless device, such as GPS, WiMAX, LTE, or UWB, to manage wireless medium sharing for optimum performance. Figure 16 shows the LTE coexistence interface. See Table 21, “CYW43353 GPIO/SDIO Alternative Signal Functions,” for details on multiplexed signals such as the GPIO pins. See Table 9, “Example of Common Baud Rates,” for UART baud rates. Figure 16. Cypress GCI or BT-SIG Mode LTE Coexistence Interface for CYW43353 BCM43353 WLAN GCI SECI_OUT/BT_TXD SECI_IN/BT_TXD LTE\IC UART_IN UART_OUT BTFM NOTES: SECI_OUT/BT_TXD and SECI_IN/BT_RXD, on the BCM43353, are multiplexed on the GPIOs. The 2-wire LTE coexistence interface is intended for future compatibility with the BT SIG 2-wire interface that is being standardized for Core 4.1. ORing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by setting the GPIO mask registers appropriately. 8.5 UART Interface One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins (see Table 21, “CYW43353 GPIO/ SDIO Alternative Signal Functions,”). Provided primarily for debugging during development, this UART enables the CYW43353 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART, and provides a FIFO size of 64 × 8 in each direction. 8.6 JTAG Interface The CYW43353 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and characterization test tools during board bringup. Therefore, it is highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs. See Table 21, “CYW43353 GPIO/SDIO Alternative Signal Functions,” for JTAG pin assignments. Document Number: 002-14949 Rev. *H Page 39 of 112 PRELIMINARY CYW43353 9. WLAN Host Interfaces 9.1 SDIO v3.0 The CYW43353 WLAN section supports SDIO version 3.0, including the new UHS-I modes: ■ DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling). ■ HS: High speed up to 50 MHz (3.3V signaling). ■ SDR12: SDR up to 25 MHz (1.8V signaling). ■ SDR25: SDR up to 50 MHz (1.8V signaling). ■ SDR50: SDR up to 100 MHz (1.8V signaling). ■ SDR104: SDR up to 208 MHz (1.8V signaling). ■ DDR50: DDR up to 50 MHz (1.8V signaling). Note: The CYW43353 is backward compatible with SDIO v2.0 host interfaces. The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an interrupt different from the one provided by the SDIO interface. The ability to force control of the gated clocks from within the device is also provided. SDIO mode is enabled by strapping options. Refer to Table 16 WLAN GPIO Functions and Strapping Options. The following three functions are supported: ■ Function 0 Standard SDIO function (Max. BlockSize/ByteCount = 32B) ■ Function 1 Backplane Function to access the internal system-on-chip (SoC) address space (Max. BlockSize/ByteCount = 64B) ■ Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max. BlockSize/ByteCount = 512B) 9.1.1 SDIO Pins Table 12. SDIO Pin Description SD 4-Bit Mode SD 1-Bit Mode gSPI Mode DATA0 Data line 0 DATA Data line DO Data output DATA1 Data line 1 or Interrupt IRQ Interrupt IRQ Interrupt DATA2 Data line 2 or Read Wait RW Read Wait NC Not used DATA3 Data line 3 N/C Not used CS Card select CLK Clock CLK Clock SCLK Clock CMD Command line CMD Command line DI Data input Figure 17. Signal Connections to SDIO Host (SD 4-Bit Mode) CLK CMD SD Host CYW43353 DAT[3:0] Document Number: 002-14949 Rev. *H Page 40 of 112 PRELIMINARY CYW43353 Figure 18. Signal Connections to SDIO Host (SD 1-Bit Mode) CLK CMD SD Host DATA CYW43353 IRQ RW Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four DATA lines and the CMD line. This requirement must be met during all operating states either through the use of external pull-up resistors or through proper programming of the SDIO host’s internal pull-ups 9.2 Generic SPI Mode In addition to the full SDIO mode, the CYW43353 includes the option of using the simplified generic SPI (gSPI) interface/protocol. Characteristics of the gSPI mode include: ■ Supports up to 48 MHz operation ■ Supports fixed delays for responses and data from device ■ Supports alignment to host gSPI frames (16 or 32 bits) ■ Supports up to 2 KB frame size per transfer ■ Supports little endian (default) and big endian configurations ■ Supports configurable active edge for shifting ■ Supports packet transfer through DMA for WLAN gSPI mode is enabled using the strapping option pins strap_host_ifc_[3:1]. Figure 19. Signal Connections to SDIO Host (gSPI Mode) SCLK DI SD Host DO CYW43353 IRQ CS Document Number: 002-14949 Rev. *H Page 41 of 112 PRELIMINARY CYW43353 9.2.1 SPI Protocol The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianness is supported in both modes. Figure 20 and Figure 21 show the basic write and write/read commands. Figure 20. gSPI Write Protocol Figure 21. gSPI Read Protocol Document Number: 002-14949 Rev. *H Page 42 of 112 PRELIMINARY CYW43353 9.2.1.1. Command Structure The gSPI command structure is 32 bits. The bit positions and definitions are as shown in Figure 22. Figure 22. gSPI Command Structure BCM_SPID Command Structure 31 30 29 28 C A F0 F1 27 11 10 Ad dres s – 17 bits 0 P acket length - 11b its * * 11’ h0 = 204 8 by tes F unction N o: 00 01 10 11 – – – – F unc F unc F unc F unc 0 Ϭ͗ůů^W/ƐƉĞĐŝĮĐƌĞŐŝƐƚĞƌƐ 1 1: Registers and meories belonging to other blocks in the chip (64 bytes max) 2 2: DMA channel 1. WLAN packets up to 2048 bytes. 3 ϯ͗DĐŚĂŶŶĞůϮ;ŽƉƟŽŶĂůͿ͘WĂĐŬĞƚƐƵƉƚŽϮϬϰϴďLJƚĞƐ͘ A cce ss : 0 – F ixed add ress 1 – Incremental add res s C ommand : 0 – R ead 1 – W rite 9.2.1.2. Write The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The following bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge. 9.2.1.3. Write/Read The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising clock edge of the clock burst for the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data word. This allows data to be ready for the first clock edge without relying on asynchronous delays. 9.2.1.4. Read The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read command in the following respects: a) chip selects go high between the command/address and the data and b) the time interval between the command/address is not fixed. Document Number: 002-14949 Rev. *H Page 43 of 112 PRELIMINARY CYW43353 9.2.1.5. Status The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information about any packet errors, protocol errors, information about available packet in the RX queue, etc. The status information helps in reducing the number of interrupts to the host. The status-reporting feature can be switched off using a register bit, without any timing overhead. The gSPI bus timing for read/write transactions with and without status notification are as shown in Figure 23 and Figure 24. See Table 13 for information on status field details. Figure 23. gSPI Signal Timing Without Status (32-bit Big Endian) Write cs sclk mosi C31 C31 C30 C30 C1 C1 C0 C0 D31 D31 D30 D30 Command 32 bits Write‐Read D1 D1 D0 D0 Write Data 16*n bits cs sclk mosi C31 C31 C30 C30 C0 C0 miso D31 D31 D30 D30 Response Delay Command 32 bits Read D1 D1 D0 D0 Read Data 16*n bits cs sclk mosi C31 C31 C30 C30 C0 C0 miso D31 D31 D30 D30 Command 32 bits Document Number: 002-14949 Rev. *H Response Delay D0 D0 Read Data 16*n bits Page 44 of 112 PRELIMINARY CYW43353 Figure 24. gSPI Signal Timing with Status (Response Delay = 0; 32-bit Big Endian) cs Write sclk mosi C31 C31 C1 C1 C0 C0 D31 D31 D1 D1 D0 D0 S31 S31 miso Command 32 bits Write‐Read Write Data 16*n bits S1 S1 S0 S0 Status 32 bits cs sclk mosi C31 C31 C0 C0 miso D31 D31 D0 D0 S31 S31 Read Data 16*n bits Command 32 bits Read D1 D1 S0 S0 Status 32 bits cs sclk mosi C31 C31 C0 C0 miso D31 D31 Command 32 bits D1 D1 D0 D0 S31 S31 Read Data 16*n bits S0 S0 Status 32 bits Table 13. gSPI Status Field Details Bit Name Description 0 Data not available The requested read data is not available 1 Underflow FIFO underflow occurred due to current (F2, F3) read command 2 Overflow FIFO overflow occurred due to current (F1, F2, F3) write command 3 F2 interrupt F2 channel interrupt 4 F3 interrupt F3 channel interrupt 5 F2 RX Ready F2 FIFO is ready to receive data (FIFO empty) 6 F3 RX Ready F3 FIFO is ready to receive data (FIFO empty) 7 Reserved – 8 F2 Packet Available Packet is available/ready in F2 TX FIFO 9:19 F2 Packet Length Length of packet available in F2 FIFO 20 F3 Packet Available Packet is available/ready in F3 TX FIFO 21:31 F3 Packet Length Length of packet available in F3 FIFO Document Number: 002-14949 Rev. *H Page 45 of 112 PRELIMINARY CYW43353 9.2.2 gSPI Host-Device Handshake To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW43353 is ready for data transfer. The device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be followed for waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any information to pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of interrupt and then take necessary actions. 9.2.3 Boot-Up Sequence After power-up, the gSPI host needs to wait 150 ms for the device to be out of reset. For this, the host needs to poll with a read command to F0 addr 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct register content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wakeup-WLAN bit (F0 reg 0x00 bit 7). The wakeup-WLAN issues a clock request to the PMU. For the first time after power-up, the host must wait for the availability of low power clock inside the device. Once that is available, the host must write to a PMU register to set the crystal frequency, which turns on the PLL. After the PLL is locked, the chipActive interrupt is issued to the host. This interrupt indicates the device awake/ready status. See Table 14 for information on gSPI registers. In Table 14, the following notation is used for register access: ■ R: Readable from host and CPU ■ W: Writable from host ■ U: Writable from CPU Table 14. gSPI Registers Address x0000 Register Word length Bit Access 0 R/W/U Default 0 Description 0: 16 bit word length 1: 32 bit word length Endianness 1 R/W/U 0 0: Little Endian High-speed mode 4 R/W/U 1 0: Normal mode. RX and TX at different edges. Interrupt polarity 5 R/W/U 1 0: Interrupt active polarity is low 1: Big Endian 1: High speed mode. RX and TX on same edge (default). 1: Interrupt active polarity is high (default) Wake-up 7 R/W 0 A write of 1 will denote a wake-up command from the host to the device. This will be followed by an F2 Interrupt from the gSPI device to the host, indicating device awake status. x0001 Response delay 7:0 R/W/U 8‘h04 Configurable read response delay in multiples of 8 bits x0002 Status enable 0 R/W 1 0: no status sent to host after read/write Interrupt with status 1 R/W 0 0: do not interrupt if status is sent 1: status sent to host after read/write 1: interrupt host even if status is sent Response delay for all 2 R/W 0 Reserved – – – 0: response delay applicable to F1 read only 1: response delay applicable to all function read x0003 Document Number: 002-14949 Rev. *H – Page 46 of 112 PRELIMINARY CYW43353 Table 14. gSPI Registers (Cont.) Address x0004 x0005 Register Interrupt register Interrupt register Bit Access Default Description 0 R/W 0 Requested data not available; Cleared by writing a 1 to this location 1 R 0 F2/F3 FIFO underflow due to last read 2 R 0 F2/F3 FIFO overflow due to last write 5 R 0 F2 packet available 6 R 0 F3 packet available 7 R 0 F1 overflow due to last write 5 R 0 F1 Interrupt 6 R 0 F2 Interrupt 7 R 0 F3 Interrupt x0006– x0007 Interrupt enable register 15: 0 R/W/U 16'hE0E7 Particular Interrupt is enabled if a corresponding bit is set x0008– x000B Status register 31: 0 R 32'h0000 Same as status bit definitions x000C– x000D F1 info register 0 R 1 F1 enabled 1 R 0 F1 ready for data transfer 13: 2 R/U 12'h40 F1 max packet size 0 R/U 1 F2 enabled 1 R 0 F2 ready for data transfer 15: 2 R/U 14'h800 F2 max packet size 0 R/U 1 F3 enabled 1 R 0 F3 ready for data transfer 15: 2 R/U 14'h800 F3 max packet size x000E– x000F x0010– x0011 F2 info register F3 info register x0014– x0017 Test–Read only register 31: 0 R 32'hFEED BEAD This register contains a predefined pattern, which the host can read and determine if the gSPI interface is working properly. x0018– x001B Test–R/W register 31: 0 R/W/U 32'h00000 000 This is a dummy register where the host can write some pattern and read it back to determine if the gSPI interface is working properly. Figure 25 shows the WLAN boot-up sequence from power-up to firmware download. Document Number: 002-14949 Rev. *H Page 47 of 112 PRELIMINARY CYW43353 Figure 25. WLAN Boot-Up Sequence VBAT* VDDIO WL_REG_ON 1.9 μF, ESL 1.35V, Co= 2.2 µF, Vo = 1.2V 20 – – dB LDO turn-on time LDO turn-on time when rest of chip is up – 140 180 µs External output capacitor, Co Total ESR (trace/capacitor): 5 mΩ–240 mΩ 0.5 2.2 4.7 µF External input capacitor Only use an external input capacitor at the VDD_LDO pin if it is not supplied from CBUCK output. Total ESR (trace/capacitor): 30 mΩ–200 mΩ – 1 2.2 µF 1. 1 Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Document Number: 002-14949 Rev. *H Page 90 of 112 PRELIMINARY CYW43353 17. System Power Con sumption Note: Unless otherwise stated, these values apply for the conditions specified in Table 26, “Recommended Operating Conditions and DC Characteristics,”. 17.1 WLAN Current Consumption Table 42 shows the typical, total current consumed by the CYW43353. To calculate total-solution current consumption for designs using external PAs, LNAs, and/or FEMs, add the current consumption of the external devices to the numbers in Table 42. All values in Table 42 are with the Bluetooth core in reset (that is, with Bluetooth off). Table 42. Typical WLAN Current Consumption (CYW43353 Current Only) Bandwidth (MHz) Mode VBAT = 3.6V, VDDIO = 1.8V, TA 25°C Band (GHz) Vio1, μA Vbat, mA Sleep Modes – – 0.005 5 SLEEP3 – – 0.005 150 IEEE Power Save, DTIM 14 – 2.4 0.850 150 IEEE Power Save, DTIM 34 – 2.4 0.350 150 4 – 5 0.550 150 34 – 5 0.300 150 50 5 OFF 2 IEEE Power Save, DTIM 1 IEEE Power Save, DTIM Active Modes Receive5,6 MCS8 (SGI) 20 20 2.4 46 5 MCS7 (SGI) 20 5 66 5 20 5 56 5 40 5 79.5 5 CRS7 Receive CRS 5,6 7 Receive5,6 MCS7 (SGI) CRS7 Receive CRS 5,6 MCS9 (SGI) 7 Document Number: 002-14949 Rev. *H 2.4 40 5 67 5 80 5 110 5 80 5 103 5 Page 91 of 112 PRELIMINARY CYW43353 Table 42. Typical WLAN Current Consumption (CYW43353 Current Only) (Cont.) Bandwidth (MHz) Mode VBAT = 3.6V, VDDIO = 1.8V, TA 25°C Band (GHz) Vio1, μA Vbat, mA Active Modes with External PAs (TX Output Power is –5 dBm at the Chip Port) Transmit, CCK 20 2.4 88 5 20 2.4 76 5 Transmit, MCS7, SGI5, 8 20 5 111 5 Transmit, MCS75, 8 Transmit, MCS8, HT20, SGI 5, 8 40 5 125 5 Transmit, MCS9, SGI 5, 8 40 5 125 5 Transmit, MCS9, SGI 5, 8 80 5 147 5 Active Modes with Internal PAs (TX Output Power Measured at the Chip Port) TX CCK 11 Mbps at 21.7 dBm 20 2.4 325 5 TX OFDM MCS8 (SGI) at 17.2 dBm 20 2.4 240 5 TX OFDM MCS7 (SGI) at 18.5 dBm 20 5 280 5 TX OFDM MCS7 at 18.7 dBm 40 5 340 5 TX OFDM MCS9 (SGI) at 16.2 dBm 40 5 270 5 TX OFDM MCS9 (SGI) at 15.7 dBm 80 5 270 5 1. VIO is specified with all pins idle (not switching) and not driving any loads. 2. WL_REG_ON, BT_REG_ON low. 3. Idle, not associated, or inter-beacon. 4. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @1 Mbps. Average current over the specified DTIM intervals. 5. Measured using packet engine test mode. 6. Duty cycle is 100%. Carrier sense (CS) detect/packet receive. 7. Carrier sense (CCA) when no carrier present. 8. Duty cycle is 100%. Excludes external PA contribution. Document Number: 002-14949 Rev. *H Page 92 of 112 PRELIMINARY CYW43353 17.2 Bluetooth Current Consumption The Bluetooth BLE current consumption measurements are shown in Table 43. Note: ■ The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 43. ■ The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm. Table 43. Bluetooth BLE Current Consumption Operating Mode VBAT (VBAT = 3.6V) Typical VDDIO (VDDIO = 1.8V) Typical Units Sleep 10 225 μA Standard 1.28s Inquiry Scan 180 235 μA 320 235 μA 500 ms Sniff Master 170 250 μA 500 ms Sniff Slave 120 250 μA DM1/DH1 Master 22.81 0.034 mA DM3/DH3 Master 28.06 0.044 mA DM5/DH5 Master 29.01 0.047 mA 3DH5 Master 27.09 0.100 mA SCO HV3 Master 7.9 0.123 mA HV3 + Sniff + Scan 11.38 0.180 mA BLE Scan2 175 235 μA BLE Scan 10 ms 14.09 0.022 mA BLE Adv – Unconnectable 1.00 sec 69 245 μA BLE Adv – Unconnectable 1.28 sec 67 235 μA BLE Adv – Unconnectable 2.00 sec 42 240 μA BLE Connected 7.5 ms 4.30 0.020 mA P and I Scan 2 1 BLE Connected 1 sec 53 240 μA BLE Connected 1.28 sec 48 240 μA 1. At maximum class 1 TX power, 500 ms sniff, four attempts (slave), P = 1.28s, and I = 2.56s. 2. No devices present. A 1.28 second interval with a scan window of 11.25 ms. Document Number: 002-14949 Rev. *H Page 93 of 112 PRELIMINARY CYW43353 18. Interface Ti ming and AC Characteristics 18.1 SDIO/gSPI Timing 18.1.1 SDIO Default Mode Timing SDIO default mode timing is shown by the combination of Figure 32 and Table 44. Figure 32. SDIO Bus Timing (Default Mode) fPP tWL tWH SDIO_CLK tTHL tTLH tISU tIH Input Output tODLY tODLY (max) (min) Table 44. SDIO Bus Timing1 Parameters (Default Mode) Parameter Symbol Minimum Typical Maximum Unit SDIO CLK (All values are referred to minimum VIH and maximum VIL2) Frequency – Data Transfer mode fPP 0 – 25 MHz Frequency – Identification mode fOD 0 – 400 kHz Clock low time tWL 10 – – ns Clock high time tWH 10 – – ns Clock rise time tTLH – – 10 ns Clock fall time tTHL – – 10 ns Inputs: CMD, DAT (referenced to CLK) Input setup time tISU 5 – – ns Input hold time tIH 5 – – ns Outputs: CMD, DAT (referenced to CLK) Output delay time – Data Transfer mode tODLY 0 – 14 ns Output delay time – Identification mode tODLY 0 – 50 ns 1. Timing is based on CL  40pF load on CMD and Data. 2. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO. Document Number: 002-14949 Rev. *H Page 94 of 112 PRELIMINARY CYW43353 18.1.2 SDIO High-Speed Mode Timing SDIO high-speed mode timing is shown by the combination of Figure 33 and Table 45. Figure 33. SDIO Bus Timing (High-Speed Mode) fPP tWL tWH 50% VDD SDIO_CLK tTHL tISU tTLH tIH Input Output tODLY tOH Table 45. SDIO Bus Timing1 Parameters (High-Speed Mode) Parameter Symbol Minimum Typical Maximum Unit SDIO CLK (all values are referred to minimum VIH and maximum VIL2) Frequency – Data Transfer Mode fPP 0 – 50 MHz Frequency – Identification Mode fOD 0 – 400 kHz Clock low time tWL 7 – – ns Clock high time tWH 7 – – ns Clock rise time tTLH – – 3 ns Clock fall time tTHL – – 3 ns Inputs: CMD, DAT (referenced to CLK) Input setup time tISU 6 – – ns Input hold time tIH 2 – – ns Outputs: CMD, DAT (referenced to CLK) Output delay time – Data Transfer Mode tODLY – – 14 ns Output hold time tOH 2.5 – – ns Total system capacitance (each line) CL – – 40 pF 1. Timing is based on CL  40pF load on CMD and Data. 2. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO. Document Number: 002-14949 Rev. *H Page 95 of 112 PRELIMINARY CYW43353 18.1.3 SDIO Bus Timing Specifications in SDR Modes 18.1.3.1. Clock Timing Figure 34. SDIO Clock Timing (SDR Modes) tCLK SDIO_CLK tCR tCF tCR Table 46. SDIO Bus Clock Timing Parameters (SDR Modes) Parameter – – Symbol tCLK tCR, tCF Minimum Maximum Unit Comments 40 – ns SDR12 mode 20 – ns SDR25 mode 10 – ns SDR50 mode 4.8 – ns SDR104 mode – 0.2 × tCLK ns tCR, tCF < 2.00 ns (max.) @100 MHz, CCARD = 10 pF tCR, tCF < 0.96 ns (max.) @208 MHz, CCARD = 10 pF Clock duty cycle – 30 Document Number: 002-14949 Rev. *H 70 % – Page 96 of 112 PRELIMINARY CYW43353 18.1.3.2. Device Input Timing Figure 35. SDIO Bus Input Timing (SDR Modes) SDIO_CLK tIS tIH CMD input DAT[3:0] input Table 47. SDIO Bus Input Timing Parameters (SDR Modes) Symbol Minimum Maximum Unit Comments SDR104 Mode tIS 1.4 – ns CCARD = 10 pF, VCT = 0.975V tIH 0.8 – ns CCARD = 5 pF, VCT = 0.975V SDR50 Mode tIS 3.0 – ns CCARD = 10 pF, VCT = 0.975V tIH 0.8 – ns CCARD = 5 pF, VCT = 0.975V SDR25 Mode tIS 3.0 – ns CCARD = 10 pF, VCT = 0.975V tIH 0.8 – ns CCARD = 5 pF, VCT = 0.975V SDR12 Mode tIS 3.0 – ns CCARD = 10 pF, VCT = 0.975V tIH 0.8 – ns CCARD = 5 pF, VCT = 0.975V Document Number: 002-14949 Rev. *H Page 97 of 112 PRELIMINARY CYW43353 18.1.3.3. Device Output Timing Figure 36. SDIO Bus Output Timing (SDR Modes up to 100 MHz) tCLK SDIO_CLK tODLY tOH CMD output DAT[3:0] output Table 48. SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz) Symbol Minimum Maximum Unit Comments tODLY – 7.5 ns tCLK ≥ 10 ns CL= 30 pF using driver type B for SDR50 tODLY – 14.0 ns tCLK ≥ 20 ns CL= 40 pF using for SDR12, SDR25 tOH 1.5 – ns Hold time at the tODLY (min) CL= 15 pF Figure 37. SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz) tCLK SDIO_CLK tOP tODW CMD output DAT[3:0] output Document Number: 002-14949 Rev. *H Page 98 of 112 PRELIMINARY CYW43353 Table 49. SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz) Symbol Minimum Maximum Unit Comments tOP 0 2 UI Card output phase ΔtOP –350 +1550 ps Delay variation due to temp change after tuning tODW 0.60 – UI tODW=2.88 ns @208 MHz ■ ΔtOP = +1550 ps for junction temperature of ΔtOP = 90 degrees during operation ■ ΔtOP = –350 ps for junction temperature of ΔtOP = –20 degrees during operation ■ ΔtOP = +2600 ps for junction temperature of ΔtOP = –20 to +125 degrees during operation Figure 38. ΔtOP Consideration for Variable Data Window (SDR 104 Mode) Data valid window Sampling point after tuning ȴtOP = 1550 ps ȴtOP = –350 ps Data valid window Sampling point after card junction heating by +90°C from tuning temperature Data valid window Sampling point after card junction cooling by –20°C from tuning temperature 18.1.4 SDIO Bus Timing Specifications in DDR50 Mode Figure 39. SDIO Clock Timing (DDR50 Mode) tCLK SDIO_CLK tCR Document Number: 002-14949 Rev. *H tCF tCR Page 99 of 112 PRELIMINARY CYW43353 Table 50. SDIO Bus Clock Timing Parameters (DDR50 Mode) Parameter Symbol Minimum Maximum Unit Comments – tCLK 20 – ns DDR50 mode – tCR,tCF – 0.2 × tCLK ns tCR, tCF < 4.00 ns (max) @50 MHz, CCARD = 10 pF Clock duty cycle – 45 55 % – 18.1.4.4. Data Timing, DDR50 Mode Figure 40. SDIO Data Timing (DDR50 Mode) FPP SDIO_CLK tISU2x DAT[3:0]  input Invalid tIH2x Data tISU2x Invalid tIH2x Data Invalid tODLY2x (max) DAT[3:0]  output tODLY2x  (min) (min) Data In DDR50 mode, DAT[3:0] lines are sampled on both edges of  the clock (not applicable for CMD line) Document Number: 002-14949 Rev. *H Invalid tODLY2x (max) tODLY2x  Data Data Available timing  window for card  output transition Data Available timing  window for host to  sample data from card Page 100 of 112 PRELIMINARY CYW43353 Table 51. SDIO Bus Timing Parameters (DDR50 Mode) Parameter Symbol Minimum Maximum Unit Comments Input CMD Input setup time tISU 6 – ns CCARD < 10pF (1 Card) Input hold time tIH 0.8 – ns CCARD < 10pF (1 Card) Output CMD Output delay time tODLY – 13.7 ns CCARD < 30pF (1 Card) Output hold time tOH 1.5 – ns CCARD < 15pF (1 Card) Input setup time tISU2x 3 – ns CCARD < 10pF (1 Card) Input hold time tIH2x 0.8 – ns CCARD < 10pF (1 Card) Input DAT Output DAT Output delay time tODLY2x – 7.0 ns CCARD < 25pF (1 Card) Output hold time tODLY2x 1.5 – ns CCARD < 15pF (1 Card) Document Number: 002-14949 Rev. *H Page 101 of 112 PRELIMINARY CYW43353 18.1.5 gSPI Signal Timing The gSPI host and device always use the rising edge of clock to sample data. Figure 41. gSPI Timing Table 52. gSPI Timing Parameters Parameter Clock period Symbol Minimum Maximum Units Note T1 20.8 – ns T2/T3 (0.45 × T1) – T4 (0.55 × T1) – T4 ns – T4/T5 – 2.5 ns Measured from 10% to 90% of VDDIO Input setup time T6 5.0 – ns Setup time, SIMO valid to SPI_CLK active edge Input hold time T7 5.0 – ns Hold time, SPI_CLK active edge to SIMO invalid Clock high/low Clock rise/fall time1 Fmax = 48 MHz Output setup time T8 5.0 – ns Setup time, SOMI valid before SPI_CLK rising Output hold time T9 5.0 – ns Hold time, SPI_CLK active edge to SOMI invalid CSX to clock2 – 7.86 – ns CSX fall to 1st rising edge Clock to CSXa – – – ns Last falling edge to CSX high 1. Limit applies when SPI_CLK = Fmax. For slower clock speeds, longer rise/fall times are acceptable provided that the transitions are monotonic and the setup and hold time limits are complied with. 2. SPI_CSx remains active for entire duration of gSPI read/write/write-read transaction (overall words for multiple-word transaction). 18.2 JTAG Timing Table 53. JTAG Timing Characteristics Signal Name Output Maximum Period Output Minimum Setup Hold TCK 125 ns – – – TDI – – – 20 ns 0 ns TMS – – – 20 ns 0 ns TDO – 100 ns 0 ns – – JTAG_TRST 250 ns – – – – Document Number: 002-14949 Rev. *H – Page 102 of 112 PRELIMINARY CYW43353 19. Power-Up Sequence and Timing 19.1 Sequencing of Reset and Regulator Control Signals The CYW43353 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure 42, Figure 43, and Figure 44 and Figure 45). The timing values indicated are minimum required values; longer delays are also acceptable. 19.1.1 Description of Control Signals ■ WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal CYW43353 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. ■ BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal CYW43353 regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT section is in reset. Note: ■ For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start. ■ The CYW43353 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold. Wait at least 150 ms after VDDC and VDDIO are available before initiating SDIO accesses. ■ VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Ensure that BT_REG_ON is driven high at the same time as or before WL_REG_ON is driven high. BT_REG_ON can be driven low 100 ms after WL_REG_ON goes high 19.1.2 Control Signal Timing Diagrams Figure 42. WLAN = ON, Bluetooth = ON 32.678 kHz  Sleep Clock VBAT* 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high  before VBAT is high. Document Number: 002-14949 Rev. *H Page 103 of 112 PRELIMINARY CYW43353 Figure 43. WLAN = OFF, Bluetooth = OFF 32.678 kHz  Sleep Clock VBAT* VDDIO WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Figure 44. WLAN = ON, Bluetooth = OFF 32.678 kHz  Sleep Clock VBAT* 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON 100 ms BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. 3. Ensure that BT_REG_ON is driven high at the same time as or before WL_REG_ON is driven high.  BT_REG_ON can be driven low 100 ms after WL_REG_ON goes high. Document Number: 002-14949 Rev. *H Page 104 of 112 PRELIMINARY CYW43353 Figure 45. WLAN = OFF, Bluetooth = ON 32.678 kHz  Sleep Clock VBAT* 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.  2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first or be held high before VBAT is high . Document Number: 002-14949 Rev. *H Page 105 of 112 PRELIMINARY CYW43353 20. Package Information 20.1 Package Thermal Characteristics Table 54. Package Thermal Characteristics1 Characteristic WLBGA JA (°C/W) (value in still air) JB (°C/W) JC (°C/W) 32.9 JT (°C/W) 3.30 JB (°C/W) 9.85 Maximum Junction Temperature Tj (°C) Maximum Power Dissipation (W) 1. 2.56 0.98 125 1.119 No heat sink, TA = 70°C. This is an estimate, based on a 4-layer PCB that conforms to EIA/JESD51–7 (101.6 mm × 101.6 mm × 1.6 mm) and P = specified power maximum continuous power dissipation. 20.2 Junction Temperature Estimation and PSIJT Versus THETAJC Package thermal characterization parameter PSI–JT (JT) yields a better estimation of actual junction temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta–JC (JC). The reason for this is that JC assumes that all the power is dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is: TJ = TT + P x JT Where: ■ TJ = Junction temperature at steady-state condition (°C) ■ TT = Package case top center temperature at steady-state condition (°C) ■ P = Device power dissipation (Watts) ■ JT = Package thermal characteristics; no airflow (°C/W) 20.3 Environmental Characteristics For environmental characteristics data, see Table 24, “Environmental Ratings,”. Document Number: 002-14949 Rev. *H Page 106 of 112 PRELIMINARY CYW43353 21. Mechanical Info rmation Figure 46. 145-Ball WLBGA Package Mechanical Information 002-13196 Rev. *A Document Number: 002-14949 Rev. *H Page 107 of 112 PRELIMINARY CYW43353 Figure 47. WLBGA Keep-out Areas for PCB Layout—Bottom View with Balls Facing Up Note: No top-layer metal is allowed in keep-out areas. Document Number: 002-14949 Rev. *H Page 108 of 112 PRELIMINARY CYW43353 22. Ordering Information Part Number Package CYW43353LIUBG 145 ball WLBGA (4.87 mm × 5.413 mm, 0.4 mm pitch) Operating Ambient Temperature Description Dual-band 2.4 GHz and 5 GHz WLAN + BT 4.1 for Automotive and Industrial Applications –40°C to +85°C 23. Additional Information 23.1 Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined upon first use. For a more complete list of acronyms and other terms used in Cypress documents, go to: http://www.cypress.com/glossary. 23.2 References The references in this section may be used in conjunction with this document. Note: Cypress provides customer access to technical documentation and software through its https://community.cypress.com and Downloads & Support site (see Additional Information). For Cypress documents, replace the “xx” in the document number with the largest number available in the repository to ensure that you have the most current version of the document. Document (or Item) Name [1] Bluetooth MWS Coexistence 2-wire Transport Interface Specification Number – Source wiced-smart 23.3 IoT Resources Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website (https://community.cypress.com/) Document Number: 002-14949 Rev. *H Page 109 of 112 PRELIMINARY CYW43353 Document History Page Document Title: CYW43353 Single-Chip 5G MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and Industrial Applications Document Number: 002-14949 Revision ** ECN Submission Date - 07/02/2013 Description of Change 43353-DS100-R Initial release *A - 04/02/2014 43353-DS101-R Updated: • The cover page and the general features . • By deleting the HSIC interface throughout, leaving pin and signal names unchanged. • By changing the VBAT maximum voltage to 4.8V throughout. • “External Frequency Reference”. • Table 2: “Crystal Oscillator and External Clock — Requirements and Performance” . • “Frequency Selection”. • Figure 10: “Startup Signaling Sequence”. • Figure 22: “UART Timing”. • “One-Time Programmable Memory”. • Table 20: “FCFBGA, WLBGA, and WLCSP Signal Descriptions,” on page 117 by changing BT_VDDO to BT_VDDIO and adding a note to the GPIO pin description. • Table 31: “I/O States”. • Table 34: “ESD Specifications”. • Table 35: “Recommended Operating Conditions and DC Characteristics,” by changing CIN to COUT. • • • • • • • • • • Document Number: 002-14949 Rev. *H Table 36: “Bluetooth Receiver RF Specifications” by deleting what was footnote e, altering footnote b, and adding footnote b to one additional place. Table 37: “Bluetooth Transmitter RF Specifications” “Introduction”. RSSI accuracy in Table 42: “WLAN 2.4 GHz Receiver Performance Specifications” and Table 44: “WLAN 5 GHz Receiver Performance Specifications”. Table 43: “WLAN 2.4 GHz Transmitter Performance Specifications” and the note preceding it. Table 45: “WLAN 5 GHz Transmitter Performance Specifications” and the note preceding it. Section 18: “Internal Regulator Electrical Specifications” “WLAN Current Consumption” on page 175. Figure 65: “SDIO Bus Output Timing (SDR Modes up to 100 MHz)”. Figure 66: “SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)”. Page 110 of 112 PRELIMINARY CYW43353 Document Title: CYW43353 Single-Chip 5G MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and Industrial Applications Document Number: 002-14949 *B - 05/28/2014 43353-DS102-R Updated: • The Features listed in the front matter of the document. • By changing all instances of Bluetooth 4.0 to Bluetooth 4.1 throughout the document. • By removing the word draft after all instances of IEEE 802.11ac throughout the document. • Features. • External 32.768 kHz Low-Power Oscillator. • Advanced Bluetooth/WLAN Coexistence. • SDIO v3.0. • Table 20: “FCFBGA, WLBGA, and WLCSP Signal Descriptions,” on page 25 by fixing an incorrect WLBGA ball. The second instance of M12 was changed to M10. • Table 16. • Table 18. • Table 19. • Description of Control Signals. • Figure 44: “WLAN = ON, Bluetooth = OFF” . *C - 10/16/2014 43353-DS103-R Updated: • Cover page. *D - 11/17/2014 43353-DS104-R Updated: • The state of the data sheet from Advance Data Sheet to Data Sheet. • Table 47. *E 5449254 10/04/2016 Added Cypress Part Numbering Scheme and Mapping Table on Page 1. Updated to Cypress template. *F 5730057 05/10/2017 Updated Cypress Logo and Copyright. *G 6516509 04/13/2020 Updated Figure 46 (spec 002-13196 ** to *A) in Package Information. *H 7108629 03/24/2021 Removed Cypress Part Numbering Scheme. Updated Features and 10.2.IEEE 802.11ac PHY. Updated Table 32 and Table 34. Document Number: 002-14949 Rev. *H Page 111 of 112 PRELIMINARY CYW43353 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Code Examples | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless 112 © Cypress Semiconductor Corporation, 2013-2021. This document is the property of Cypress Semiconductor Corporation, and Infineon Technologies company, and its affiliates (“Cypress”). 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Cypress, the Cypress logo, and combinations thereof, WICED, ModusToolBox, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress or a subsidiary of Cypress in the United States or in other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-14949 Rev. *H Revised March 24, 2021 Page 112 of 112