Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
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Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CYW4339
PRELIMINARY
Single-Chip 5G WiFi IEEE 802.11ac MAC/
Baseband/Radio with Integrated Bluetooth 4.1
General Description
The Cypress® CYW4339 single-chip device provides the highest level of integration for Internet of Things and handheld wireless
system with integrated single-stream IEEE 802.11ac MAC/baseband/radio and Bluetooth 4.1. In IEEE 802.11ac mode, the WLAN
operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz channels for data rates up to 433.3 Mbps.
In addition, all the rates specified in IEEE 802.11a/b/g/n are supported. Included on-chip are 2.4 GHz and 5 GHz transmit amplifiers,
and receive low-noise amplifiers. Optional external PAs, LNAs, and antenna diversity are also supported.
For the WLAN section, several alternative host interface options are included: an SDIO v3.0 interface that can operate in 4b or 1b
and a PCIe Gen1 interface (3.0 compliant). For the Bluetooth section, host interface options of a high-speed 4-wire UART and USB
2.0 full-speed (12 Mbps) are provided.
Using advanced design techniques and process technology to reduce active and idle power, the CYW4339 is designed to address
the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which
simplifies the system power topology and allows for direct operation from a mobile platform battery while maximizing battery life.
The CYW4339 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which
ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. In addition, coexistence support for external
radios (such as LTE cellular, GPS, and WiMAX) is provided via an external interface. As a result, enhanced overall quality for
simultaneous voice, video, and data transmission is achieved.
Features
IEEE 802.11x Key Features
■
IEEE 802.11ac compliant.
■
Single-stream spatial multiplexing up to 433.3 Mbps
data rate.
■
Supports 20, 40, and 80 MHz channels with optional
SGI (256 QAM modulation).
■
Full IEEE 802.11a/b/g/n legacy compatibility with
enhanced performance.
■
Supports Rx space-time block coding (STBC)
■
Supports IEEE 802.11ac/n beamforming.
■
On-chip power amplifiers and low-noise amplifiers for
both bands.
■
Support for optional front-end modules (FEM) with
external PAs and LNAs
■
Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while
maintaining excellent sensitivity for both Bluetooth
and WLAN.
■
Internal fractional nPLL allows support for a wide
range of reference clock frequencies
■
Supports IEEE 802.15.2 external coexistence interface to optimize bandwidth utilization with other co-
Cypress Semiconductor Corporation
Document No. 002-14784 Rev. *I
•
located wireless technologies such as LTE, GPS, or
WiMAX
■
Supports standard SDIO v3.0 (including DDR50 mode
at 50 MHz and SDR104 mode at 208 MHz, 4-bit and
1-bit) host interfaces.
■
Backward compatible with SDIO v2.0 host interfaces.
■
PCIe mode (FCBGA package only) complies with PCI
Express base specification revision 3.0 compliant
Gen1 interface for ×1 lane and power management
base specification.
■
■
198 Champion Court
Integrated ARMCR4™ processor with tightly coupled
memory for complete WLAN subsystem functionality,
minimizing the need to wake up the applications processor for standard WLAN functions. This allows for
further minimization of power consumption, while
maintaining the ability to field upgrade with future features. On-chip memory includes 768 KB SRAM and
640 KB ROM.
OneDriver™ software architecture for easy migration
from existing embedded WLAN and Bluetooth
devices as well as future devices.
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 24, 2021
PRELIMINARY
Bluetooth Key Features
General Features
■
Complies with Bluetooth Core Specification Version
4.1 with provisions for supporting future specifications.
■
Bluetooth Class 1 or Class 2 transmitter operation.
■
Supports extended synchronous connections (eSCO),
for enhanced voice quality by allowing for retransmission of dropped packets.
■
Adaptive frequency hopping (AFH) for reducing radio
frequency interference.
■
■
Supports battery voltage range from 3.0V to 5.25V
supplies with internal switching regulator.
■
Programmable dynamic power management
■
OTP: 502 bytes of user-accessible memory
■
GPIOs: 12 on FCFBGA, nine on WLBGA, and 16 on
WLCSP
■
Package options:
❐
❐
Interface support, host controller interface (HCI) using
a USB or high-speed UART interface and PCM for
audio data.
❐
■
USB 2.0 full-speed (12 Mbps) supported (FCFBGA
and WLCSP packages).
■
Low power consumption improves battery life of handheld devices.
❐
■
Supports multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound.
❐
■
Automatic frequency detection for standard crystal
and TCXO values.
■
CYW4339
❐
❐
Supports serial flash interfaces.
■
160 ball FCFBGA (8 mm x 8 mm, 0.4 mm pitch)
145 ball WLBGA (4.87 mm × 5.413 mm, 0.4 mm
pitch)
286 bump WLCSP (4.87 mm × 5.413 mm, 0.2 mm
pitch)Security:
WPA™ and WPA2™ (Personal) support for powerful encryption and authentication
AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility
Reference WLAN subsystem provides Cisco®
Compatible Extensions (CCX, CCX 2.0, CCX 3.0,
CCX 4.0, CCX 5.0)
Reference WLAN subsystem provides
Wi-Fi Protected Setup (WPS)
Worldwide regulatory support: Global products
supported with worldwide homologated design.
Figure 1.Functional Block Diagram
VIO
VBAT
WL_REG_ON
WLAN
Host I/F
5 GHz WLAN TX
PCIe
5 GHz WLAN RX
SDIO*
External
Coexistence I/F
FEM or
T/R
Switch
COEX
2.4 GHz WLAN TX
2.4 GHz WLAN/BT RX
CYW4339
CLK_REQ
Bluetooth TX
FEM or
T/R
Switch
CBF
BT_REG_ON
UART
USB 2.0
Bluetooth Host I/F
I2S
PCM
BT_DEV_WAKE
BT_HOST_WAKE
Document No. 002-14784 Rev. *I
Page 2 of 132
PRELIMINARY
CYW4339
Contents
1. Overview ............................................................ 5
1.1
Overview ............................................................. 5
1.2
Features .............................................................. 6
1.3
Standards Compliance ........................................ 7
2. Power Supplies and Power Management ....... 8
5.8
Fast Connection (Interlaced Page and Inquiry
Scans) ................................................................25
6. Microprocessor and Memory Unit for
Bluetooth ......................................................... 26
6.1
RAM, ROM, and Patch Memory .........................26
6.2
Reset ..................................................................26
2.1
Power Supply Topology ...................................... 8
2.2
PMU Features ..................................................... 8
2.3
WLAN Power Management ............................... 10
7.1
SPI Interface ......................................................27
2.4
PMU Sequencing .............................................. 10
7.2
SPI/UART Transport Detection ..........................27
2.5
Power-Off Shutdown ......................................... 11
7.3
2.6
Power-Up/Power-Down/Reset Circuits ............. 11
PCM Interface ....................................................27
7.3.1 Slot Mapping ...........................................27
7.3.2 Frame Synchronization ...........................28
7.3.3 Data Formatting ......................................28
7.3.4 Wideband Speech Support .....................28
7.3.5 Burst PCM Mode ....................................28
7.3.6 PCM Interface Timing .............................29
7.4
USB Interface .....................................................35
7.4.1 Features .................................................35
7.4.2 Operation ................................................35
7.4.3 USB Hub and UHE Support ...................36
7.4.4 USB Full-Speed Timing ..........................36
7.5
UART Interface ..................................................37
7.6
I2S Interface .......................................................39
7.6.1 I2S Timing ...............................................39
7. Bluetooth Peripheral Transport Unit............. 27
3. Frequency References ................................... 12
3.1
Crystal Interface and Clock Generation ............ 12
3.2
External Frequency Reference ......................... 13
3.3
Frequency Selection ......................................... 14
3.4
External 32.768 kHz Low-Power Oscillator ....... 15
4. Bluetooth Subsystem Overview .................... 16
4.1
Features ............................................................ 16
4.2
Bluetooth Radio ................................................. 17
4.2.1 Transmit ................................................. 17
4.2.2 Digital Modulator .................................... 17
4.2.3 Digital Demodulator and Bit Synchronizer 17
4.2.4 Power Amplifier ..................................... 17
4.2.5 Receiver ................................................ 17
4.2.6 Digital Demodulator and Bit Synchronizer 17
4.2.7 Receiver Signal Strength Indicator ........ 17
4.2.8 Local Oscillator Generation ................... 18
4.2.9 Calibration ............................................. 18
5. Bluetooth Baseband Core.............................. 19
8. WLAN Global Functions................................. 41
8.1
WLAN CPU and Memory Subsystem ................41
8.2
One-Time Programmable Memory .....................41
8.3
GPIO Interface ...................................................41
8.4
External Coexistence Interface ..........................42
8.5
UART Interface ..................................................42
JTAG Interface ...................................................42
SPROM Interface (FCBGA Package only) .........42
5.1
Bluetooth 4.1 Features ...................................... 19
8.6
5.2
Bluetooth Low Energy ....................................... 19
8.7
5.3
Link Control Layer ............................................. 20
5.4
Test Mode Support ............................................ 20
5.5
Bluetooth Power Management Unit .................. 21
5.5.1 RF Power Management ......................... 21
5.5.2 Host Controller Power Management ..... 21
5.5.3 BBC Power Management ...................... 23
5.5.4 Wideband Speech ................................. 23
5.5.5 Packet Loss Concealment ..................... 23
5.5.6 Audio Rate-Matching Algorithms ........... 24
5.5.7 Codec Encoding .................................... 24
5.5.8 Multiple Simultaneous A2DP Audio
Streams ................................................. 24
5.5.9 Burst Buffer Operation ........................... 24
5.6
Adaptive Frequency Hopping ............................ 24
5.7
Advanced Bluetooth/WLAN Coexistence .......... 25
Document No. 002-14784 Rev. *I
9. WLAN Host Interfaces .................................... 43
9.1
SDIO v3.0 ...........................................................43
9.1.1 SDIO Pins ...............................................43
9.2
PCI Express Interface (FCBGA Package Only) .45
9.2.1 Transaction Layer Interface ....................45
9.2.2 Data Link Layer ......................................45
9.2.3 Physical Layer ........................................46
9.2.4 Logical Subblock ....................................46
9.2.5 Scrambler/Descrambler ..........................46
9.2.6 8B/10B Encoder/Decoder .......................46
9.2.7 Elastic FIFO ............................................46
9.2.8 Electrical Subblock .................................46
9.2.9 Configuration Space ...............................46
10. Wireless LAN MAC and PHY.......................... 47
10.1 IEEE 802.11ac MAC ..........................................47
Page 3 of 132
PRELIMINARY
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.1.7
PSM ....................................................... 48
WEP ...................................................... 48
TXE ........................................................ 48
RXE ....................................................... 48
IFS ......................................................... 49
TSF ........................................................ 49
NAV ....................................................... 49
10.2 IEEE 802.11ac PHY .......................................... 50
11. WLAN Radio Subsystem ............................... 52
11.1 Receiver Path .................................................... 52
11.2 Transmit Path .................................................... 52
11.3 Calibration ......................................................... 52
12. Pinout and Signal Descriptions..................... 54
12.1 Ball Maps .......................................................... 54
12.2 Pin Lists ............................................................. 57
12.3 Signal Descriptions ........................................... 65
12.4 WLAN GPIO Signals and Strapping Options .... 71
12.4.1 Multiplexed Bluetooth GPIO Signals ..... 73
12.5 GPIO/SDIO Alternative Signal Functions .......... 75
12.6 I/O States .......................................................... 76
13. DC Characteristics.......................................... 80
13.1 Absolute Maximum Ratings .............................. 80
13.2 Environmental Ratings ...................................... 80
CYW4339
Specifications .....................................................99
15.7 General Spurious Emissions Specifications .....100
16. Internal Regulator Electrical Specifications 100
16.1 Core Buck Switching Regulator .......................100
16.2 3.3V LDO (LDO3P3) ........................................101
16.3 2.5V LDO (BTLDO2P5) ....................................102
16.4 CLDO ...............................................................103
16.5 LNLDO .............................................................104
17. System Power Consumption ....................... 105
17.1 WLAN Current Consumption ............................105
17.2 Bluetooth Current Consumption .......................107
18. Interface Timing and AC Characteristics ... 108
18.1 SDIO Timing .....................................................108
18.1.1 SDIO Default Mode Timing ...................108
18.1.2 SDIO High-Speed Mode Timing ...........109
18.1.3 SDIO Bus Timing Specifications in SDR
Modes ...................................................109
18.1.4 SDIO Bus Timing Specifications in
DDR50 Mode ........................................114
18.2 PCI Express Interface Parameters ...................116
18.3 JTAG Timing ....................................................117
19. Power-Up Sequence and Timing ................. 118
13.4 Recommended Operating Conditions and DC
Characteristics .................................................. 81
19.1 Sequencing of Reset and Regulator Control
Signals .............................................................118
19.1.1 Description of Control Signals ..............118
19.1.2 Control Signal Timing Diagrams ...........118
14. Bluetooth RF Specifications .......................... 83
20. Package Information .................................... 121
15. WLAN RF Specifications ................................ 89
20.1 Package Thermal Characteristics ....................121
15.1 Introduction ....................................................... 89
20.2 Junction Temperature Estimation and PSIJT
Versus THETAJC ..............................................121
13.3 Electrostatic Discharge Specifications .............. 81
15.2 All WLAN specifications are specified at the RF port,
unless otherwise specified.2.4 GHz Band General RF
Specifications .................................................... 89
15.3 WLAN 2.4 GHz Receiver Performance
Specifications .................................................... 90
20.3 Environmental Characteristics .........................121
21. Mechanical Information................................ 122
22. Ordering Information.................................... 127
15.4 WLAN 2.4 GHz Transmitter Performance
Specifications .................................................... 94
23. IoT Resources ............................................... 128
15.5 WLAN 5 GHz Receiver Performance
Specifications .................................................... 95
Document History Page ............................................... 129
15.6 WLAN 5 GHz Transmitter Performance
Document No. 002-14784 Rev. *I
23.1 References .......................................................128
Sales, Solutions, and Legal Information .................... 132
Page 4 of 132
PRELIMINARY
CYW4339
1. Overview
1.1 Overview
The Cypress CYW4339 single-chip device provides the highest level of integration for IoT applications or handheld wireless system, with integrated IEEE 802.11 a/b/g/n/ac
MAC/baseband/radio, Bluetooth 4.1 + enhanced data rate (EDR).
It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and
function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption
and reliable operation.
The following figure shows the interconnect of all the major physical blocks in the CYW4339 and their associated external interfaces, which are described in greater detail in
the following sections.
Figure 1. CYW4339 Block Diagram
S E C I U A R T
a n d G C I‐ G P IO s
GCI
RAM
ROM
UART
Port Control
I2 S
PCM
ARM CM 3
JT A G
M a ste r
G P IO
T im e r s
W D
Pau se
W LAN
M a ste r
S la v e
W L A N
B T A c c e s s
LCU
APU
B lu e R F
A X I2 A H B
AHB2AXI
C h ip
Com m on
O TP
R X /T X
BLE
AHB2APB
VBAT
AHB Bus Matrix
DM A
PM U
ARM CR4
U SB
R e g is t e r s
W L_REG _O N
BT_REG _O N
TCM
RAM 768KB
RO M 640KB
W L A N R A M
S h a r in g
S D IO D
S D IO 3 .0
P C IE
P C IE 1 .1
NIC‐301 AXI Backplane
BT_H O ST_W AKE
BT_DEV_W AKE
UART
U S B 2 .0
PCM
I2S
O t h e r G P IO s
W L_H O ST_W A KE
W L_D EV_W AKE
JT A G
O t h e r G P IO s
A X I2 A P B
D O T 1 1 M A C ( D 1 1 )
G C I C o e x I/ F
S h a r e d L N A C o n t r o l
a n d O t h e r C o e x I/ F s
R F S w it c h C o n t r o ls
1 x 1 8 0 2 .1 1 a c P H Y
2 .4 G H z / 5 G H z 8 0 2 .1 1 a c
D u a l‐ B a n d R a d io
M odem
XTAL
B lu e t o o t h R F
3 2 k H z E x t e r n a l L P O
BT
PA
W LA N
B lu e t o o t h
CLB
F E M o r
SP3T
2 .4 G H z
F E M o r
SPD T
5 G H z
D ip le x e r
Document No. 002-14784 Rev. *I
Page 5 of 132
PRELIMINARY
CYW4339
1.2 Features
The CYW4339 supports the following features:
■
IEEE 802.11a/b/g/n/ac dual-band radio with virtual-simultaneous dual-band operation
■
Bluetooth v4.1 + EDR with integrated Class 1 PA
■
Concurrent Bluetooth, and WLAN operation
■
On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality
■
WLAN host interface options:
❐
■
SDIO v3.0 (1-bit/4-bit)—up to 208 MHz clock rate in SDR104 mode
BT host digital interface (which can be used concurrently with the above interfaces):
❐
UART (up to 4 Mbps)
■
BT supports full-speed USB version 1.1 for FCBGA package.
■
ECI—enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN receptions
■
I2S/PCM for BT audio
■
HCI high-speed UART (H4, H4+, H5) transport support
■
Wideband speech support (16 bits linear data, MSB first, left justified at 4K samples/s for transparent air coding, both through I2S
and PCM interface)
■
Bluetooth SmartAudio® technology improves voice and music quality to headsets
■
Bluetooth low-power inquiry and page scan
■
Bluetooth Low Energy (BLE) support
■
Bluetooth Packet Loss Concealment (PLC)
■
Bluetooth Wide Band Speech (WBS)
■
Audio rate-matching algorithms
■
Multiple simultaneous A2DP audio streams
Document No. 002-14784 Rev. *I
Page 6 of 132
PRELIMINARY
CYW4339
1.3 Standards Compliance
The CYW4339 supports the following standards:
■
Bluetooth 2.1 + EDR
■
Bluetooth 3.0
■
Bluetooth 4.1 (Bluetooth Low Energy)
■
IEEE802.11ac single-stream mandatory and optional requirements for 20 MHz, 40 MHz, and 80 MHz channels
■
IEEE 802.11n—Handheld Device Class (Section 11)
■
IEEE 802.11a
■
IEEE 802.11b
■
IEEE 802.11g
■
IEEE 802.11d
■
IEEE 802.11h
■
IEEE 802.11i
■
Security:
❐
WEP
❐
WPA™ Personal
❐
❐
❐
❐
❐
❐
❐
■
Proprietary Protocols:
❐
❐
❐
❐
■
WPA2™ Personal
WMM
WMM-PS (U-APSD)
WMM-SA
AES (Hardware Accelerator)
TKIP (HW Accelerator)
CKIP (SW Support)
CCXv2
CCXv3
CCXv4
CCXv5
IEEE 802.15.2 Coexistence Compliance—on silicon solution compliant with IEEE 3 wire requirements
The CYW4339 will support the following future drafts/standards:
■
IEEE 802.11r—Fast Roaming (between APs)
■
IEEE 802.11w—Secure Management Frames
■
IEEE 802.11 Extensions:
❐
❐
❐
❐
IEEE 802.11e QoS Enhancements (as per the WMM® specification is already supported)
IEEE 802.11h 5 GHz Extensions
IEEE 802.11i MAC Enhancements
IEEE 802.11k Radio Resource Measurement
Document No. 002-14784 Rev. *I
Page 7 of 132
PRELIMINARY
CYW4339
2. Power Supplies and Power Management
2.1 Power Supply Topology
One buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW4339. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs.
A single VBAT (3.0V to 5.25V DC maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided
by the regulators in the CYW4339.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective section out of
reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only
when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off and on based on the dynamic
demands of the digital baseband.
The CYW4339 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO
regulators. When in this state, LPLDO1 and LPLDO2 (which are low-power linear regulators that are supplied by the system VIO
supply) provide the CYW4339 with all the voltages it requires, further reducing leakage currents.
2.2 PMU Features
■
VBAT to 1.35V (275 mA nominal, 600 mA maximum) Core-Buck (CBUCK) switching regulator
■
VBAT to 3.3V (200 mA nominal, 450 mA maximum) LDO3P3
■
VBAT to 2.5V (15 mA nominal, 70 mA maximum) BTLDO2P5
■
1.35V to 1.2V (100 mA nominal, 150 mA maximum) LNLDO
■
1.35V to 1.2V (175 mA nominal, 300 mA maximum) CLDO with bypass mode for deep-sleep
■
Additional internal LDOs (not externally accessible)
The following figure shows the regulators and a typical power topology.
Document No. 002-14784 Rev. *I
Page 8 of 132
PRELIMINARY
CYW4339
Figure 2. Typical Power Topology for CYW4339
Shaded areas are internal to the CYW4339
Internal LNLDO
80 mA
Internal LNLDO
80 mA
Internal VCOLDO
80 mA
Internal LNLDO
80 mA
1.2V
XTAL LDO
30 mA
1.2V
WL RF – AFE
1.2V
WL RF – TX (2.4 GHz, 5 GHz)
1.2V
WL RF – LOGEN (2.4 GHz, 5 GHz)
1.2V
WL RF – RX/LNA (2.4 GHz, 5 GHz)
WL RF – XTAL
WL RF – RFPLL PFD/MMD
LNLDO
100 mA
1.2V
BT RF
HSIC/DFE/DFLL
WL_REG_ON
BT_REG_ON
VBAT
PCIE PLL/RXTX
Core Buck
Regulator
CBUCK
Peak 600 mA
Average 275 mA
WLAN BBPLL/DFLL
1.35V
WLAN/BT/CLB/Top, always on
WL OTP
VDDIO
LPLDO1
3 mA
1.1V
CLDO
Peak 300 mA
Average 175 mA
(Bypass in deep
sleep)
WL PHY
1.2V– 1.1V
WL DIGITAL
BT DIGITAL
WL/BT SRAMs
VDDIO
BTLDO2P5
Peak 70 mA
Average 15 mA
2.5V
MEMLPLDO
3 mA
0.9V
BT CLASS 1 PA
WL PA/PAD (2.4 GHz, 5 GHz)
VDDIO_RF
Internal LNLDO
25 mA
Internal LNLDO
8 mA
Document No. 002-14784 Rev. *I
2.5V
3.3V
2.5V
LDO3P3
Peak 800–450 mA
Average 200 mA
WL OTP 3.3V
WL RF – VCO
WL RF – CP
Page 9 of 132
PRELIMINARY
CYW4339
2.3 WLAN Power Management
The CYW4339 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip
design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and
supply voltages. Additionally, the CYW4339 integrated RAM is a high Vt memory with dynamic clock control. The dominant supply
current consumed by the RAM is leakage current only. Additionally, the CYW4339 includes an advanced WLAN power management
unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW4339 into various power
management states appropriate to the current environment and activities that are being performed. The power management unit
enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table
that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully
programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock frequency) in the PMU sequencer are used
to turn on and turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the
current mode. Slower clock speeds are used wherever possible.
The CYW4339 WLAN power states are described as follows:
■
Active mode— All WLAN blocks in the CYW4339 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock
speeds are dynamically adjusted by the PMU sequencer.
■
Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW4339 remains
powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are shut down to reduce active power consumption
to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU
sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.
■
Deep-sleep mode—Most of the chip, including both analog and digital domains, and most of the regulators are powered off. Logic
states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is powered off. Upon a wake-up event triggered by the PMU timers, an external interrupt, or a host resume through the SDIO bus, logic
states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization.
■
Power-down mode—The CYW4339 is effectively powered off by shutting down all internal regulators. The chip is brought out of
this mode by external logic reenabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system resources
based on a computation of the required resources and a table that describes the relationship between resources and the time needed
to enable and disable them.
Resource requests may come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of four states (enabled, disabled, transition_on, and transition_off) and has a timer that contains 0 when the
resource is enabled or disabled and a nonzero value in the transition states. The timer is loaded with the time_on or time_off value of
the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz
PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is
0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go
immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or
the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
■
Computes the required resource set based on requests and the resource dependency table.
■
Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the Resource Pending bit for the resource
and inverts the Resource State bit.
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■
Compares the request with the current resource status and determines which resources must be enabled or disabled.
■
Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents.
■
Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
2.5 Power-Off Shutdown
The CYW4339 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices
in the system, remain operational. When the CYW4339 is not needed in the system, VDDIO_RF and VDDC are shut down while
VDDIO remains powered. This allows the CYW4339 to be effectively off while keeping the I/O pins powered so that they do not draw
extra current from any other devices connected to the I/O.
During a low-power shut-down state, the provided VDDIO remains applied to the CYW4339, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW4339 to be fully integrated in an embedded device and
take full advantage of the lowest power-savings modes.
When the CYW4339 is powered on from this state, it is the same as a normal power-up, and the device does not retain any information
about its state from before it was powered down.
2.6 Power-Up/Power-Down/Reset Circuits
The CYW4339 has two signals (see Table 1) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks,
allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see
Power-Up Sequence and Timing on page 118.
Table 1. Power-Up/Power-Down/Reset Control Signals
Signal
Description
WL_REG_ON
This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also OR-gated with the BT_REG_ON
input to control the internal CYW4339 regulators. When this pin is high, the regulators are enabled and the WLAN section is
out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the regulators
are disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through
programming.
BT_REG_ON
This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal CYW4339 regulators.
If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 k pull-down resistor
that is enabled by default. It can be disabled through programming.
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3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency
reference may be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW4339 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator,
including all external components, is shown in Figure 3. Consult the reference schematics for the latest configuration and recommended components.
Figure 3. Recommended Oscillator Configuration
C *
WRF_XTAL_IN
37.4 MHz
C *
X ohms *
WRF_XTAL_OUT
* Values determined by crystal drive
level. See reference schematics for details.
A fractional-N synthesizer in the CYW4339 generates the radio frequencies, clocks, and data/packet timing, enabling the CYW4339
to operate using a wide selection of frequency references.
For SDIO applications, the recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal
interface are listed in Table 2.
Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Cypress for details.
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3.2 External Frequency Reference
As an alternative to a crystal, an external precision frequency reference can be used. The recommended default frequency is 37.4
MHz. This must meet the phase noise requirements listed in Table 2.
If used, the external clock should be connected to the WRF_XTAL_IN pin through an external 1000 pF coupling capacitor, as shown
in Figure 4. The internal clock buffer connected to this pin will be turned off when the CYW4339 goes into sleep mode. When the clock
buffer turns on and off, there will be a small impedance variation. Power must be supplied to the WRF_XTAL_BUCK_VDD1P5 pin.
Figure 4. Recommended Circuit to Use with an External Reference Clock
1000 pF
Reference
Clock
WRF_XTAL_IN
NC
WRF_XTAL_OUT
Table 2. Crystal Oscillator and External Clock—Requirements and Performance
Parameter
External Frequency
Reference2 3
Crystal1
Conditions/Notes
Min.
Typ.
Max.
Min.
Typ.
Max.
Frequency
2.4 GHz and 5 GHz bands,
IEEE 802.11ac operation
35
37.4
38.4
–
37.4
–
Frequency
5 GHz band, IEEE 802.11n operation only
19
37.4
38.4
35
37.4
38.4
Units
MHz
MHz
4
Frequency
2.4 GHz band IEEE 802.11n operation, and both
bands legacy 802.11a/b/g operation only
Frequency tolerance over
the lifetime of the
equipment, including
temperature5
Without trimming
–20
–
20
–20
–
20
ppm
Crystal load capacitance
–
–
12
–
–
–
–
pF
ESR
–
–
–
60
–
–
–
Ω
Drive level
External crystal must be able to tolerate this drive
level.
200
–
–
–
–
–
µW
Input impedance
(WRF_XTAL_IN)
Resistive
–
–
–
30k
100k
–
Ω
Capacitive
–
–
7.5
–
–
7.5
pF
WRF_XTAL_IN
input low level
DC-coupled digital signal
–
–
–
0
–
0.2
V
WRF_XTAL_IN
input high level
DC-coupled digital signal
–
–
–
1.0
–
1.26
V
WRF_XTAL_IN
input voltage
(see Figure 4)
AC-coupled analog signal
–
–
–
1000
–
1200
mVp-p
Duty cycle
37.4 MHz clock
–
–
–
40
50
60
%
Phase noise6
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–129
dBc/Hz
(IEEE 802.11b/g)
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–136
dBc/Hz
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–137
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–144
dBc/Hz
Phase
noise6
(IEEE 802.11a)
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Table 2. Crystal Oscillator and External Clock—Requirements and Performance (Cont.)
Parameter
External Frequency
Reference2 3
Crystal1
Conditions/Notes
Min.
Typ.
Min.
Typ.
Max.
Units
Phase noise6
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–134
dBc/Hz
(IEEE 802.11n, 2.4 GHz)
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–141
dBc/Hz
Phase noise
6
Max.
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–142
dBc/Hz
(IEEE 802.11n, 5 GHz)
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–149
dBc/Hz
Phase noise6
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–148
dBc/Hz
(IEEE 802.11ac, 5 GHz)
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–155
dBc/Hz
1. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT.
2. See External Frequency Reference for alternative connection methods.
3. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz.
4. The frequency step size is approximately 80 Hz.
5. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications.
6. Assumes that external clock has a flat phase-noise response above 100 kHz.
3.3 Frequency Selection
Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard
mobile platform reference frequencies of 19.2, 19.8, 24, 26, 33.6, 37.4, and 38.4 MHz, but also other frequencies in this range with
an approximate resolution of 80 Hz. The CYW4339 must have the reference frequency set correctly in order for any of the UART or
PCM interfaces to function correctly, since all bit timing is derived from the reference frequency.
Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default require
support to be added in the driver plus additional, extensive system testing. Contact Cypress for details.
The reference frequency for the CYW4339 may be set in the following ways:
■
Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency.
■
Autodetect any of the standard handset reference frequencies using an external LPO clock.
For applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard
frequencies commonly used, the CYW4339 automatically detects the reference frequency and programs itself to the correct reference
frequency. In order for automatic frequency detection to work correctly, the CYW4339 must have a valid and stable 32.768 kHz LPO
clock that meets the requirements listed in Table 3 and is present during power-on reset.
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3.4 External 32.768 kHz Low-Power Oscillator
The CYW4339 uses a secondary low-frequency clock for low-power-mode timing. Either the internal low-precision LPO or an external
32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage,
and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a small
current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in
Table 3.
Table 3. External 32.768 kHz Sleep Clock Specifications
Parameter
LPO Clock
Units
Nominal input frequency
32.768
kHz
Frequency accuracy
±200
ppm
Duty cycle
30–70
%
Input signal amplitude
200–1800
mV, p-p
Signal type
Square-wave or sine-wave
–
Input impedance1
>100k
0 .3 5 T
V H = 2 .0 V
SCK
V L = 0 .8 V
t h tr > 0
t o t r < 0 .8 T
S D a n d W S
T = C lo c k p e r io d
T t r = M in im u m a llo w e d c lo c k p e r io d fo r t r a n s m it t e r
T = T t r
* t R C is o n ly r e le v a n t fo r t r a n s m itt e r s in s la v e m o d e .
Figure 18. I2S Receiver Timing
T
t L C > 0 .3 5 T
t H C > 0 .3 5
V H = 2 .0 V
SCK
V L = 0 .8 V
t s r > 0 .2 T
thr > 0
S D a n d W S
T = C lo c k p e rio d
T r = M in im u m a llo w e d c lo c k p e rio d fo r tr a n s m itt e r
T > T r
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8. WLAN Global Functions
8.1 WLAN CPU and Memory Subsystem
The CYW4339 WLAN section includes an integrated ARM Cortex-R4™ 32-bit processor with internal RAM and ROM. The ARM
Cortex-R4 is a low-power processor that features low gate count, low interrupt latency, and low-cost debug capabilities. It is intended
for deeply embedded applications that require fast interrupt response features. Delivering more than 30% performance gain over
ARM7TDMI, the ARM Cortex-R4 implements the ARM v7-R architecture with support for the Thumb®-2 instruction set.
At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit
devices on MIPS/µW. It supports integrated sleep modes.
Using multiple technologies to reduce cost, the ARM Cortex-R4 offers improved memory utilization, reduced pin overhead, and
reduced silicon area. It supports independent buses for Code and Data access (ICode/DCode and System buses), and extensive
debug features including real time trace of program execution.
On-chip memory for the CPU includes 768 KB SRAM and 640 KB ROM.
8.2 One-Time Programmable Memory
Various hardware configuration parameters may be stored in an internal One-Time Programmable (OTP) memory, which is read by
the system software after device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC
address can be stored, depending on the specific board design. Customer accessible OTP memory is 502 bytes.
The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0.
The entire OTP array can be programmed in a single write cycle using a utility provided with the Cypress WLAN manufacturing test
tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state
can be altered during each programming cycle.
Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with
the reference board design package.
8.3 GPIO Interface
The following number of general-purpose I/O (GPIO) pins are available on the WLAN section of the CYW4339 that can be used to
connect to various external devices:
■
FCBGA package – 12 GPIOs
■
WLBGA package – 9 GPIOs
■
WLCSP package – 16 GPIOs
Upon power up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via
the GPIO control register. In addition, the GPIO pins can be assigned to various other functions (see Table 26, “CYW4339 GPIO/SDIO
Alternative Signal Functions,”).
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8.4 External Coexistence Interface
An external handshake interface is available to enable signaling between the device and an external co-located wireless device, such
as GPS, WiMAX, LTE, or UWB, to manage wireless medium sharing for optimum performance.
Figure 19 shows the LTE coexistence interface. See Table 26, “CYW4339 GPIO/SDIO Alternative Signal Functions,” for details on
multiplexed signals such as the GPIO pins.
See Table 13, “Example of Common Baud Rates,” for UART baud rates.
Figure 19. Broadcom GCI or BT-SIG Mode LTE Coexistence Interface for CYW4339
CYW4339
WLAN
GCI
SECI_OUT/BT_TXD
SECI_IN/BT_TXD
LTE\IC
UART_IN
UART_OUT
BT
NOTES:
SECI_OUT/BT_TXD and SECI_IN/BT_RXD, on the BCM4339, are multiplexed on the
GPIOs.
The 2-wire LTE coexistence interface is intended for future compatibility with the BT
SIG 2-wire interface that is being standardized for Core 4.1.
ORing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is
achieved by setting the GPIO mask registers appropriately.
8.5 UART Interface
One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins (see Table 26, “CYW4339 GPIO/SDIO
Alternative Signal Functions,”). Provided primarily for debugging during development, this UART enables the CYW4339 to operate
as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the
industry standard 16550 UART, and provides a FIFO size of 64 × 8 in each direction.
8.6 JTAG Interface
The CYW4339 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing
during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and characterization test tools during board bringup. Therefore, it is highly recommended to provide access to the JTAG pins by means of test points
or a header on all PCB designs.
See Table 26, “CYW4339 GPIO/SDIO Alternative Signal Functions,” for JTAG pin assignments.
8.7 SPROM Interface (FCBGA Package only)
For use only with the PCIe Interface in the FCBGA package, various hardware configuration parameters may be stored in an external
SPROM instead of the OTP. The SPROM is read by system software after device reset. In addition, depending on the board design,
customer-specific parameters may be stored in SPROM.
The four SPROM control signals —SPROM_CS, SPROM_CLK, SPROM_DIN, and SPROM_DOUT are multiplexed on the SDIO
interface (see Table 26, “CYW4339 GPIO/SDIO Alternative Signal Functions,” for additional details). By default, the SPROM interface
supports 2 kbit serial SPROMs, and it can also support 4 kbit and 16 kbit serial SPROMs by using the appropriate strapping option.
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9. WLAN Host Interfaces
9.1 SDIO v3.0
The CYW4339 WLAN section supports SDIO version 3.0, including the new UHS-I modes:
■
DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).
■
HS: High speed up to 50 MHz (3.3V signaling).
■
SDR12: SDR up to 25 MHz (1.8V signaling).
■
SDR25: SDR up to 50 MHz (1.8V signaling).
■
SDR50: SDR up to 100 MHz (1.8V signaling).
■
SDR104: SDR up to 208 MHz (1.8V signaling).
■
DDR50: DDR up to 50 MHz (1.8V signaling).
Note: The CYW4339 is backward compatible with SDIO v2.0 host interfaces.
The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an interrupt different
from the one provided by the SDIO interface. The ability to force control of the gated clocks from within the device is also provided.
SDIO mode is enabled by strapping options. Refer to Table 19 WLAN GPIO Functions and Strapping Options.
The following three functions are supported:
■
Function 0 Standard SDIO function (Max. BlockSize/ByteCount = 32B)
■
Function 1 Backplane Function to access the internal system-on-chip (SoC) address space
(Max. BlockSize/ByteCount = 64B)
■
Function 2 WLAN Function for efficient WLAN packet transfer through DMA
(Max. BlockSize/ByteCount = 512B)
9.1.1 SDIO Pins
Table 16. SDIO Pin Description
SD 4-Bit Mode
SD 1-Bit Mode
DATA0
Data line 0
DATA
Data line
DATA1
Data line 1 or Interrupt
IRQ
Interrupt
DATA2
Data line 2 or Read Wait
RW
Read Wait
DATA3
Data line 3
N/C
Not used
CLK
Clock
CLK
Clock
CMD
Command line
CMD
Command line
Figure 20. Signal Connections to SDIO Host (SD 4-Bit Mode)
CLK
SD Host
CMD
CYW4339
DAT[3:0]
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Figure 21. Signal Connections to SDIO Host (SD 1-Bit Mode)
CLK
CMD
SD Host
DATA
CYW4339
IRQ
RW
Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four DATA lines and the CMD
line. This requirement must be met during all operating states either through the use of external pull-up resistors or through proper
programming of the SDIO host’s internal pull-ups.
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9.2 PCI Express Interface (FCBGA Package Only)
The PCI Express (PCIe™) core on the CYW4339 is a high-performance serial I/O interconnect that is protocol compliant and electrically compatible with the PCI Express Base Specification (revision 3.0 compliant Gen1 interface). This core contains all the necessary
blocks, including logical and electrical functional subblocks to perform PCIe functionality and maintain high-speed links, using existing
PCI system configuration software implementations without modification.
Organization of the PCIe core is in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as shown in Figure 22. A
configuration or link management block is provided for enumerating the PCIe configuration space and supporting generation and
reception of System Management Messages by communicating with PCIe layers.
Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication between the host and
CYW4339 device. The transmit side processes outbound packets while the receive side processes inbound packets. Packets are
formed and generated in the Transaction and Data Link Layer for transmission onto the high-speed links and onto the receiving device.
A header is added at the beginning to indicate the packet type and any other optional fields.
Figure 22. PCI Express Layer Model
HW/SW Interface
HW/SW Interface
Transaction
Layer
Transaction
Layer
Data Link
Layer
Data Link
Layer
Physical Layer
Physical Layer
Logical Subblock
Logical Subblock
Electrical Subblock
Electrical Subblock
TX
RX
TX
RX
9.2.1 Transaction Layer Interface
The PCIe core employs a packet-based protocol to transfer data between the host and CYW4339 device, delivering new levels of
performance and features. The upper layer of the PCIe is the Transaction Layer. The Transaction layer is primarily responsible for
assembly and disassembly of Transaction Layer Packets (TLPs). TLP structure contains header, data payload, and End-to-End CRC
(ECRC) fields, which are used to communicate transactions, such as read and write requests and other events.
A pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication between devices with creditbased flow control of TLP, which eliminates wasted link bandwidth due to retries.
9.2.2 Data Link Layer
The data link layer serves as an intermediate stage between the transaction layer and the physical layer. Its primary responsibility is
to provide reliable, efficient mechanism for the exchange of TLPs between two directly connected components on the link. Services
provided by the data link layer include data exchange, initialization, error detection and correction, and retry services.
Data Link Layer Packets (DLLPs) are generated and consumed by the data link layer. DLLPs are the mechanism used to transfer link
management information between data link layers of the two directly connected components on the link, including TLP acknowledgement, power management, and flow control.
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9.2.3 Physical Layer
The physical layer of the PCIe provides a handshake mechanism between the data link layer and the high-speed signaling used for
Link data interchange. This layer is divided into the logical and electrical functional subblocks. Both subblocks have dedicated transmit
and receive units that allow for point-to-point communication between the host and CYW4339 device. The transmit section prepares
outgoing information passed from the data link layer for transmission, and the receiver section identifies and prepares received
information before passing it to the data link layer. This process involves link initialization, configuration, scrambler, and data
conversion into a specific format.
9.2.4 Logical Subblock
The logical sub block primary functions are to prepare outgoing data from the data link layer for transmission and identify received
data before passing it to the data link layer.
9.2.5 Scrambler/Descrambler
This PCIe PHY component generates pseudo-random sequence for scrambling of data bytes and the idle sequence. On the transmit
side, scrambling is applied to characters prior to the 8b/10b encoding. On the receive side, descrambling is applied to characters after
8b/10b decoding. Scrambling may be disabled in polling and recovery for testing and debugging purposes.
9.2.6 8B/10B Encoder/Decoder
The PCIe core on the CYW4339 uses an 8b/10b encoder/decoder scheme to provide DC balancing, synchronizing clock and data
recovery, and error detection. The transmission code is specified in the ANSI X3.230-1994, clause 11 and in IEEE 802.3z, 36.2.4.
Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a 6-bit code group,
respectively. The control bit in conjunction with the data character is used to identify when to encode one of the twelve Special Symbols
included in the 8b/10b transmission code. These code groups are concatenated to form a 10-bit symbol, which is then transmitted
serially. Special Symbols are used for link management, frame TLPs, and DLLPs, allowing these packets to be quickly identified and
easily distinguished.
9.2.7 Elastic FIFO
An elastic FIFO is implemented in the receiver side to compensate for the differences between the transmit clock domain and the
receive clock domain, with worse case clock frequency specified at 600 ppm tolerance. As a result, the transmit and receive clocks
can shift one clock every 1666 clocks. In addition, the FIFO adaptively adjusts the elastic level based on the relative frequency
difference of the write and read clock. This technique reduces the elastic FIFO size and the average receiver latency by half.
9.2.8 Electrical Subblock
The high-speed signals utilize the Common Mode Logic (CML) signaling interface with on-chip termination and de-emphasis for bestin-class signal integrity. A de-emphasis technique is employed to reduce the effects of Intersymbol Interference (ISI) due to the
interconnect by optimizing voltage and timing margins for worst case channel loss. This results in a maximally open “eye” at the
detection point, thereby allowing the receiver to receive data with acceptable Bit-Error Rate (BER).
To further minimize ISI, multiple bits of the same polarity that are output in succession are de-emphasized. Subsequent same bits are
reduced by a factor of 3.5 dB in power. This amount is specified by PCIe to allow for maximum interoperability while minimizing the
complexity of controlling the de-emphasis values. The high-speed interface requires AC coupling on the transmit side to eliminate the
DC common mode voltage from the receiver. The range of AC capacitance allowed is 75 nF to 200 nF.
9.2.9 Configuration Space
The PCIe function in the CYW4339 implements the configuration space as defined in the PCI Express Base Specification (revision
3.0 compliant Gen1 interface).
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10. Wireless LAN MAC and PHY
10.1 IEEE 802.11ac MAC
The CYW4339 WLAN MAC is designed to support high-throughput operation with low-power consumption. It does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power saving
modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing synchronization. The architecture diagram of the MAC is shown in Figure 23.
The following sections provide an overview of the important modules in the MAC.
Figure 23. WLAN MAC Architecture
E m b e d d e d C P U In t e r fa c e
H o s t R e g is te r s , D M A E n g in e s
T X ‐F IF O
3 2 K B
PM Q
R X ‐F IF O
1 0 K B
PSM
PSM
UCODE
M e m o ry
IF S
B a c k o ff , B T C X
W EP
T K IP , A E S , W A P I
TSF
SH M
BUS
IH R
NAV
E X T ‐ IH R
BUS
TXE
T X A ‐M P D U
RXE
R X A ‐ M P D U
S h a r e d M e m o r y
6 K B
M A C ‐P H Y In t e r fa c e
The CYW4339 WLAN media access controller (MAC) supports features specified in the IEEE 802.11 base standard, and amended
by IEEE 802.11n. The key MAC features include:
■
Enhanced MAC for supporting IEEE 802.11ac features
■
Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput (HT)
■
Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP) and multiphase PSMP
operation
■
Support for immediate ACK and Block-ACK policies
■
Interframe space timing support, including RIFS
■
Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges
■
Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification
■
Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time
(TBTT) generation in hardware
■
Hardware offload for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management
■
Support for coexistence with Bluetooth and other external radios
■
Programmable independent basic service set (IBSS) or infrastructure basic service set functionality
■
Statistics counters for MIB support
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PRELIMINARY
CYW4339
10.1.1 PSM
The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control to the hardware, to
implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow control operations, which are predominant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which
allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving
IEEE 802.11 specifications.
The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data
store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad
memory (similar to a register bank) to store frequently accessed and temporary variables.
The PSM exercises fine-grained control over the hardware engines, by programming internal hardware registers (IHR). These IHRs
are co-located with the hardware functions they control, and are accessed by the PSM via the IHR bus.
The PSM fetches instructions from the microcode memory using an address determined by the program counter, instruction literal,
or a program stack. For ALU operations the operands are obtained from shared memory, scratch-pad, IHRs, or instruction literals,
and the results are written into the shared memory, scratch-pad, or IHRs.
There are two basic branch instructions: conditional branches and ALU based branches. To better support the many decision points
in the IEEE 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch condition
signals are available to the PSM without polling the IHRs), or on the results of ALU operations.
10.1.2 WEP
The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, and
MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, WPA2 AESCCMP.
The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to be used. It supplies
the keys to the hardware engines from an on-chip key table. The WEP interfaces with the TXE to encrypt and compute the MIC on
transmit frames, and the RXE to decrypt and verify the MIC on receive frames.
10.1.3 TXE
The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames
in the TXFIFO. It interfaces with WEP module to encrypt frames, and transfers the frames across the MAC-PHY interface at the
appropriate time determined by the channel access mechanisms.
The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic
streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule
a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a
precise timing trigger received from the IFS module.
The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware
module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed.
10.1.4 RXE
The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames
from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The
decrypted data is stored in the RXFIFO.
The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria
such as receiver address, BSSID, and certain frame types.
The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate
them into component MPDUS.
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PRELIMINARY
CYW4339
10.1.5 IFS
The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple
backoff engines required to support prioritized access to the medium as specified by WMM.
The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers
provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform
transmit frame-bursting (RIFS or SIFS separated, as within a TXOP).
The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or
pause the backoff counters. When the backoff counters reach 0, the TXE gets notified, so that it may commence frame transmission.
In the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies
provided by the PSM.
The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power
save mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized by
the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer
expires the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration ensuring that the TSF
is synchronized to the network.
The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.
10.1.6 TSF
The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon
and probe response frames in order to maintain synchronization with the network.
The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink
transmission times used in PSMP.
10.1.7 NAV
The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration
field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard.
The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames.
This timing information is provided to the IFS module, which uses it as a virtual carrier-sense indication.
MAC-PHY Interface
The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is an
programming interface, which can be controlled either by the host or the PSM to configure and control the PHY.
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PRELIMINARY
CYW4339
10.2 IEEE 802.11ac PHY
The CYW4339 WLAN Digital PHY is designed to comply with IEEE 802.11ac and IEEE 802.11a/b/g/n single-stream specifications to
provide wireless LAN connectivity supporting data rates from 1 Mbps to 433.3 Mbps for low-power, high-performance handheld
applications.
The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. It incorporates
optimized implementations of the filters, FFT and Viterbi decoder algorithms. Efficient algorithms have been designed to achieve
maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking,
channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier sense has
been tuned to provide high throughput for IEEE 802.11g/11b hybrid networks with Bluetooth coexistence. It has also been designed
for shared single antenna systems between WL and BT to support simultaneous RX-RX.
The key PHY features include:
■
Programmable data rates from MCS0–9 in 20 MHz, 40 MHz, and 80 MHz channels, as specified in IEEE 802.11ac
■
Supports Optional Short GI mode in TX and RX
■
Supports optional space-time block code (STBC) receive of two space-time streams for improved throughput and range in fading
channel environments.
■
All scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse operations in the receive
direction.
■
Supports IEEE 802.11h/k for worldwide operation
■
Advanced algorithms for low power, enhanced sensitivity, range, and reliability
■
Algorithms to improve performance in presence of Bluetooth
■
Automatic gain control scheme for blocking and non blocking application scenario for cellular applications
■
Closed loop transmit power control
■
Digital RF chip calibration algorithms to handle CMOS RF chip non-idealities
■
On-the-fly channel frequency and transmit power selection
■
Supports per packet RX antenna diversity
■
Available per-packet channel quality and signal strength measurements
■
Designed to meet FCC and other worldwide regulatory requirements
Document No. 002-14784 Rev. *I
Page 50 of 132
PRELIMINARY
CYW4339
Figure 24. WLAN PHY Block Diagram
CCK/DSSS Demodulate
Filters and Radio
Comp
Frequency and
Timing Synch
OFDM Demodulate
Viterbi Decoder
Descramble and
Deframe
Carrier Sense, AGC, and
Rx FSM
Buffers
Radio Control Block
MAC
Interface
FFT/IFFT
AFE and
Radio
Tx FSM
Common Logic Block
Modulation and
Coding
Frame and
Scramble
Filters and Radio Comp
PA Comp
Modulate/Spread
COEX
Document No. 002-14784 Rev. *I
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PRELIMINARY
CYW4339
11. WLAN Radio Subsystem
The CYW4339 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz Wireless
LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the
globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. The transmit and receive sections include all on-chip filtering, mixing,
and gain control functions.
Ten RF control signals are available to drive external RF switches and support optional external power amplifiers and low-noise
amplifiers for each band. See the reference board schematics for further details.
A block diagram of the radio subsystem is shown in Figure 25. Note that integrated on-chip baluns (not shown) convert the fully
differential transmit and receive paths to single-ended signal pins.
11.1 Receiver Path
The CYW4339 has a wide dynamic range, direct conversion receiver that employs high order on-chip channel filtering to ensure
reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. An on-chip low-noise amplifier (LNA) in the 2.4 GHz
path is shared between the Bluetooth and WLAN receivers, while the 5 GHz receive path has a dedicated on-chip LNA. Control signals
are available that can support the use of optional LNAs for each band, which can increase the receive sensitivity by several dB.
11.2 Transmit Path
Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5-GHz U-NII bands, respectively. Linear on-chip power amplifiers
are included, which are capable of delivering high output powers while meeting IEEE 802.11ac and IEEE 802.11a/b/g/n specifications
without the need for external PAs. When using the internal PAs, closed-loop output power control is completely integrated. As an
option, external PAs can be used for even higher output power, in which case the closed-loop output power control is provided by
means of a-band and g-band TSSI inputs from external power detectors.
11.3 Calibration
The CYW4339 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variations
across components. These calibration routines are performed periodically in the course of normal radio operation. Examples of some
of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance, and LOFT
calibration for carrier leakage reduction. In addition, I/Q Calibration, R Calibration, and VCO Calibration are performed on-chip. No
per-board calibration is required in manufacturing test, which helps to minimize the test time and cost in large volume production.
Document No. 002-14784 Rev. *I
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PRELIMINARY
CYW4339
Figure 25. Radio Functional Block Diagram
WL DAC
WL PA
WL PAD
WL PGA
WL A‐PA
WL A‐PAD
WL A‐PGA
WL TXLPF
WL TX G‐Mixer
WL DAC
WL TXLPF
WL TX A‐Mixer
WL RX A‐Mixer
Voltage
Regulators
WLAN BB
WL ADC
WL A‐LNA11
WL A‐LNA12
WL RXLPF
MUX
WL ADC
SLNA
WL G‐LNA12
WL RXLPF
WL RX G‐Mixer
WL ATX
WL ARX
WL GTX
WL GRX
CLB
WL LOGEN
WL PLL
Gm
BT LNA GM
Shared XO
BT RX
BT TX
BT LOGEN
BT PLL
LPO/Ext LPO/RCAL
BT ADC
BT RXLPF
BT ADC
BT LNA Load
BT RX Mixer
BT RXLPF
BT BB
BT PA
BT
BT DAC
BT DAC
BT TX Mixer
Document No. 002-14784 Rev. *I
BT TXLPF
Page 53 of 132
PRELIMINARY
CYW4339
12. Pinout and Signal Descriptions
12.1 Ball Maps
Figure 26 shows the FCFBGA ball map. Figure 27 shows the WLBGA ball map. Figure 28 shows the WLCSP bump map.
Figure 26. 160-Ball FCFBGA (Top View)
1
A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SR_VLX
GPIO_13
GPIO_5
GPIO_3
VDDIO_SD
SDIO_DATA_1
B
SR_VDDBATP5V
SR_VLX
VDDIO
GPIO_4
GPIO_7
SDIO_DATA_3
SDIO_CLK
PAD_RDN0
C
SR_VDDBATP5V
SR_VDDBATP5V
SR_VDDBATA5V
BT_REG_ON
GPIO_2
SDIO_DATA_2 SDIO_DATA_0
SDIO_CMD
PAD_RDP0
GPIO_1
D
SR_PVSS
GPIO_14
GPIO_0
PCIE_VSS
PCIE_VSS
E
SR_PVSS
SR_PVSS
F
LDO_VDD1P5
LDO_VDD1P5
NO CONNECT
VOUT_CLDO
NO CONNECT
G
H
VOUT_3P3
JTAG_SEL
GPIO_6
WL_REG_ON GPIO_15
GPIO_8
VDDC
PMU_AVSS VSSC
VSSC
VSSC
VSSC
LPO_IN
VSSC
VSSC
K
VOUT_LNLDO
VDDC
VSSC
VSSC
BT_VDDIO
BT_VDDC
VSSC
BT_DEV_WAKE
BT_VDDC
VSSC
N
HUSB_DN
HUSB_DP
P
R
VSSC
VSSC
BT_VCOVSS
BT_PLLVSS
U
BT_I2S_WS
BT_I2S_DO
BT_I2S_DI
V
BT_UART_RTS_N
BT_HOST_WAKE
BT_VCOVDD
BT_PLLVDD
BT_PAVDD
WRF_GPIO_OUT
W
BT_UART_RXD
BT_UART_TXD
CLK_REQ
BT_LNAVDD
BT_IFVDD
BT_RF
WRF_RFIN_2G
BT_UART_CTS_N
3
PAD_PLL_AVDD1P2
BT_LNAVSS BT_IFVSS
BT_PAVSS
RF_SW_CTRL_8
RF_SW_CTRL_5 RF_SW_CTRL_6
VDDC
RF_SW_CTRL_9
RF_SW_CTRL_4
RF_SW_CTRL_7
RF_SW_CTRL_1 RF_SW_CTRL_2
VSSC
WRF_VCO_GND1P2
WRF_LOGENG_GND1P2
WRF_BUCK_GND1P5
BBPLLAVSS
5
Document No. 002-14784 Rev. *I
C
PAD_AVDD1P2
D
WRF_PA2G_VBAT_GND3P3 WRF_AFE_GND1P2
WRF_BUCK_VDD1P5
WRF_TX_GND1P2
WRF_MMD_GND1P2
WRF_PFD_GND1P2
WRF_PADRV_VBATGND3P3
WRF_LOGEN_GND1P2
WRF_LNA_2G_GND1P2
WRF_LNA_5G_GND1P2
6
7
8
9
10
WRF_TSSI_A
12
RF_SW_CTRL_0
14
15
J
K
OTP_VDD33
L
BBPLLAVDD
M
WRF_XTAL_VDD1P5
WRF_XTAL_GND1P2 WRF_XTAL_IN
WRF_XTAL_OUT
WRF_RX5G_GND1P2
WRF_PFD_VDD1P2
WRF_XTAL_VDD1P2
16
WRF_RFIN_5G
17
18
N
P
R
T
U
WRF_MMD_VDD1P2
WRF_RFOUT_5G
13
G
H
WRF_PA2G_VBAT_GND3P3 WRF_PA2G_VBAT_VDD3P3 WRF_PADRV_VBAT_VDD3P3 WRF_PA5G_VBAT_VDD3P3 WRF_PA5G_VBAT_GND3P3
WRF_RFOUT_2G
11
RF_SW_CTRL_3
WRF_XTAL_GND1P2
WRF_PA5G_VBAT_GND3P3
4
BT_GPIO_4
VDDIO_RF
WRF_RX2G_GND1P2
BT_I2S_CLK
2
B
WRF_CP_GND1P2
BT_SF_CLK
BT_SF_MISO
1
PCI_PME_L
VDDC
BT_SF_MOSI
BT_SF_CSN
T
A
PAD_REFCLKP
F
VOUT_3P3_SENSE
LDO_VDDBAT5V PMU_VDDIO
PERST_L
19
PCIE_CLKREQ_L
E
VOUT_BTLDO2P5
L
PAD_TDN0
18
PAD_REFCLKN
VDDC
J
M
PAD_TDP0
17
WRF_SYNTH_VBAT_VDD3P3
V
NO CONNECT
W
19
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PRELIMINARY
CYW4339
Figure 27. 145-Ball WLBGA (Top View)
1
A
2
3
4
NO CONNECT
NO CONNECT
NO CONNECT
WL_REG_ON
LPO_IN
5
6
7
NO CONNECT
NO CONNECT
GPIO_3
GPIO_0
HSIC_DATA
8
9
10
11
12
A
NO CONNECT
NO CONNECT
NO CONNECT
HSIC_STROBE
RREFHSIC
SDIO_DATA_0
SDIO_CLK
SDIO_CMD
B
B
SR_PVSS
SR_VLX
C
SR_VDDBATP5V
SR_VDDBATA5V PMU_AVSS
GPIO_6
GPIO_4
GPIO_1
WL_VDDC
HSIC_AVDD12PLL
HSIC_DVDD12
SDIO_DATA_1
SDIO_DATA_3
WL_VDDC
C
D
LDO_VDD1P5
VOUT_CLDO
BT_REG_ON
GPIO_7
GPIO_5
GPIO_2
VSSC
HSIC_AGNDPLL
VDDIO_SD
SDIO_DATA_2
VSSC
RF_SW_CTRL_4
D
E
VOUT_3P3
VOUT_LNLDO
VSSC
JTAG_SEL
BT_UART_CTS VDDIO_RF
RF_SW_CTRL_8
RF_SW_CTRL_3
RF_SW_CTRL_2
E
F
VOUT_BTLDO2P5
LDO_VDDBAT5V VDDIO
RF_SW_CTRL_1
RF_SW_CTRL_0
F
G
BT_PCM_IN
BT_PCM_CLK
H
GPIO_8
BT_PCM_SYNC
J
FM_AUDIOVDD1P2
K
VSSC
RF_SW_CTRL_9 BT_UART_RTS BT_UART_TXD
RF_SW_CTRL_5
WL_VDDC
WL_VDDC
BT_UART_RXD RF_SW_CTRL_7
WL_VDDC
BBPLL_AVS
WRF_XTAL_GND1P2
BBPLL_AVDD1P2
G
BT_VDDIO
BT_VDDC
BT_I2S_WS
WRF_GPIO_OUT
WRF_WL_LNLDOIN_VDD1P5 RF_SW_CTRL_6
WRF_VCO_GND
WRF_XTAL_VDD1P5
WRF_XTAL_IN
H
BT_HOST_WAKE BT_PCM_OUT
BT_VDDC
VSSC
BT_I2S_CLK
WRF_TSSI_A
WRF_BUCK_GND1P5
WRF_MMD_GND1P2
WRF_PFD_GND1P2
WRF_CP_GND
WRF_XTAL_OUT
J
FM_AOUT1
FM_AUDIOVSS
VSSC
BT_I2S_DI
BT_I2S_DO
WRF_AFE_GND1P2
WRF_LO_GND1P2_2
WRF_SYNTH_VBAT_VDD3P3 WRF_MMD_VDD1P2
WRF_PFD_VDD1P2
WRF_XTAL_VDD1P2
K
L
FM_AOUT2
FM_PLLVDD1P2 FM_PLLVSS
BT_IFVDD1P2
BT_PLLVSS
BT_IFVSS
WRF_RX2G_GND1P2
WRF_TX_GND1P2
WRF_PADRV_VBAT_VDD3P3 WRF_PADRV_VBAT_GND3P3 WRF_LO_GND1P2_2
WRF_RX5G_GND1P2
L
M
FM_VCOVSS
FM_LNAVSS
BT_PLLVDD1P2 BT_PAVSS
BT_AGPIO
WRF_LNA_2G_GND1P2 WRF_PA_VBAT_GND3P3_4 WRF_PA_VBAT_GND3P3_3
N
FM_LNAVCOVDD1P2 FM_RFIN
1
2
CLK_REQ
BT_DEV_WAKE
BT_VCOVSS
BT_VCOVDD1P2 BT_LNAVDD1P2 BT_RF
3
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4
BT_PAVDD2P5 WRF_RFIN_2G
5
6
7
WRF_RFOUT_2G
8
WRF_PA2G_VBAT_VDD3P3
9
WRF_PA_VBAT_GND3P3_2
WRF_PA_VBAT_GND3P3_1 WRF_LNA_5G_GND1P2
M
WRF_PA5G_VBAT_VDD3P3
WRF_RFOUT_5G
N
10
11
WRF_RFIN_5G
12
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PRELIMINARY
CYW4339
Figure 28. 286-Bump WLCSP (Bottom View)
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PRELIMINARY
CYW4339
12.2 Pin Lists
Table 17 contains the 286-bump WLCSP coordinates.
Table 17. 286-Bump WLCSP Coordinates
Bump#
Signal Name
Package Bump Side View
(0,0 center of die)
X
Y
Package Top Side View
(0,0 center of die)
X
Y
1
SR_PVSS
2275.005
2003.355
–2275.005
2003.355
2
SR_PVSS
1992.162
2003.355
–1992.162
2003.355
3
WL_REG_ON
1709.319
2003.355
–1709.319
2003.355
4
SR_PVSS
2133.584
1861.934
–2133.584
1861.934
5
SR_PVSS
1850.741
1861.934
–1850.741
1861.934
6
SR_VLX
1567.898
1861.934
–1567.898
1861.934
7
SR_VLX
1992.162
1720.512
–1992.162
1720.512
8
SR_VLX
1709.319
1720.512
–1709.319
1720.512
9
SR_VLX
1850.741
1579.091
–1850.741
1579.091
10
SR_VLX
1567.898
1579.091
–1567.898
1579.091
11
SR_VDDBATP5V
2275.005
1437.669
–2275.005
1437.669
12
SR_VDDBATP5V
1992.162
1437.669
–1992.162
1437.669
13
SR_VLX
1709.319
1437.669
–1709.319
1437.669
14
SR_VDDBATP5V
2133.584
1296.248
–2133.584
1296.248
15
SR_VDDBATA5V
1850.741
1296.248
–1850.741
1296.248
16
LDO_VDD1P5
2275.005
1154.826
–2275.005
1154.826
17
VOUT_CLDO
1992.162
1154.826
–1992.162
1154.826
18
VOUT_CLDO
1709.319
1154.826
–1709.319
1154.826
19
LDO_VDD1P5
2133.584
1013.405
–2133.584
1013.405
20
VOUT_CLDO
1850.741
1013.405
–1850.741
1013.405
21
PMU_AVSS
1567.898
1013.405
–1567.898
1013.405
22
VOUT_3P3
2275.005
871.983
–2275.005
871.983
23
LDO_VDD1P5
1992.162
871.983
–1992.162
871.983
24
VOUT_LNLDO
1709.319
871.983
–1709.319
871.983
25
VOUT_3P3
2133.584
730.562
–2133.584
730.562
26
LDO_VDD1P5
1850.741
730.562
–1850.741
730.562
27
LDO_VDDBAT5V
2275.005
589.140
–2275.005
589.140
28
VOUT_3P3
1992.162
589.140
–1992.162
589.140
29
VOUT_3P3_SENSE
1709.319
589.140
–1709.319
589.140
30
LDO_VDDBAT5V
2133.584
447.719
–2133.584
447.719
31
VSSC
1850.741
447.719
–1850.741
447.719
32
BT_REG_ON
1567.898
447.719
–1567.898
447.719
33
VOUT_BTLDO2P5
2275.005
306.297
–2275.005
306.297
34
LDO_VDDBAT5V
1992.162
306.297
–1992.162
306.297
35
VSSC
1709.319
306.297
–1709.319
306.297
Document No. 002-14784 Rev. *I
Page 57 of 132
PRELIMINARY
CYW4339
Table 17. 286-Bump WLCSP Coordinates (Cont.)
Bump#
Signal Name
Package Bump Side View
(0,0 center of die)
X
Y
Package Top Side View
(0,0 center of die)
X
Y
36
LDO_VDDBAT5V
2133.584
164.876
–2133.584
164.876
37
PMU_VDDIO
1850.741
164.876
–1850.741
164.876
38
PMU_VDDIO
1567.898
164.876
–1567.898
164.876
39
LPO_IN
2000.397
–45.054
–2000.397
–45.054
40
HUSB_DN
2252.010
–55.251
–2252.010
–55.251
41
HUSB_DP
2264.169
–255.429
–2264.169
–255.429
42
BT_I2S_DO
1548.201
–773.253
–1548.201
–773.253
43
BT_I2S_DI
1931.412
–980.847
–1931.412
–980.847
44
BT_I2S_CLK
1659.396
–597.546
–1659.396
–597.546
45
BT_I2S_WS
1944.471
–623.367
–1944.471
–623.367
46
BT_PCM_CLK
2063.397
–268.848
–2063.397
–268.848
47
BT_PCM_SYNC
1800.498
–434.448
–1800.498
–434.448
48
BT_PCM_IN
1794.801
–223.146
–1794.801
–223.146
49
BT_PCM_OUT
1784.397
–839.853
–1784.397
–839.853
50
BT_UART_CTS_N
2136.414
–959.733
–2136.414
–959.733
51
BT_UART_RTS_N
1653.744
–991.854
–1653.744
–991.854
52
BT_UART_RXD
1583.904
–1213.488
–1583.904
–1213.488
53
BT_UART_TXD
1393.104
–1114.101
–1393.104
–1114.101
54
BT_TM1
632.001
–1226.646
–632.001
–1226.646
55
BT_VDDC_ISO_1
859.998
–1166.652
–859.998
–1166.652
56
CLK_REQ
2156.196
–1334.853
–2156.196
–1334.853
57
BT_DEV_WAKE
1652.097
–1650.546
–1652.097
–1650.546
58
BT_HOST_WAKE
1925.202
–1363.752
–1925.202
–1363.752
59
BT_GPIO_2
859.998
–966.654
–859.998
–966.654
60
BT_GPIO_3
1688.097
–1449.099
–1688.097
–1449.099
61
BT_GPIO_4
470.001
–1031.652
–470.001
–1031.652
62
BT_GPIO_5
1139.997
–1226.646
–1139.997
–1226.646
63
BT_VDDIO
1358.481
–704.151
–1358.481
–704.151
64
BT_VDDIO
1489.998
–211.653
–1489.998
–211.653
65
BT_VDDIO
1475.499
–464.652
–1475.499
–464.652
66
BT_VDDC_ISO_2
1265.574
–519.930
–1265.574
–519.930
67
BT_VDDC
933.699
–1354.050
–933.699
–1354.050
68
BT_VDDC
1482.501
–1453.950
–1482.501
–1453.950
69
BT_VDDC
294.996
–1131.651
–294.996
–1131.651
70
BT_VDDC
294.996
–1331.649
–294.996
–1331.649
71
BT_VDDC
294.996
–931.653
–294.996
–931.653
72
BT_VDDC
864.903
–482.949
–864.903
–482.949
73
BT_VDDC
1067.997
–482.949
–1067.997
–482.949
Document No. 002-14784 Rev. *I
Page 58 of 132
PRELIMINARY
CYW4339
Table 17. 286-Bump WLCSP Coordinates (Cont.)
Bump#
Signal Name
Package Bump Side View
(0,0 center of die)
X
Y
Package Top Side View
(0,0 center of die)
X
Y
74
BT_VDDC
1139.997
–1026.648
–1139.997
–1026.648
75
FM_RFAUX
1479.864
–2546.550
–1479.864
–2546.550
76
FM_IFVSS
1569.797
–1888.101
–1569.797
–1888.101
77
FM_LNAVSS
1597.593
–2333.169
–1597.593
–2333.169
78
FM_RFIN
1756.686
–2533.167
–1756.686
–2533.167
79
FM_IFVDD
1769.795
–1888.101
–1769.795
–1888.101
80
FM_LNAVDD
1797.591
–2333.169
–1797.591
–2333.169
81
FM_DAC_VSS
2045.451
–1548.549
–2045.451
–1548.549
82
FM_DAC_AVDD
2045.451
–1760.319
–2045.451
–1760.319
83
FM_VCOVSS
2080.781
–2546.550
–2080.781
–2546.550
84
FM_PLLVDD
2118.860
–1960.317
–2118.860
–1960.317
85
FM_DAC_VOUT2
2245.449
–1760.319
–2245.449
–1760.319
86
FM_DAC_VOUT1
2245.449
–1548.549
–2245.449
–1548.549
87
FM_VCOVDD
2261.469
–2444.675
–2261.469
–2444.675
88
FM_PLLVSS
2274.852
–2086.889
–2274.852
–2086.889
89
BT_IFVSS
99.975
–1842.066
–99.975
–1842.066
90
BT_IFVDD
99.975
–2042.064
–99.975
–2042.064
91
BT_AGPIO
99.975
–2291.099
–99.975
–2291.099
92
BT_PAVDD
281.860
–2422.625
–281.860
–2422.625
93
BT_RF
461.505
–2525.544
–461.505
–2525.544
94
BT_PAVSS
661.503
–2491.097
–661.503
–2491.097
95
BT_LNAVSS
873.183
–2116.746
–873.183
–2116.746
96
BT_LNAVDD
1005.281
–2501.330
–1005.281
–2501.330
97
BT_PLLVSS
1174.454
–1842.066
–1174.454
–1842.066
98
BT_PLLVDD
1174.454
–2042.064
–1174.454
–2042.064
99
BT_VCOVDD
1208.352
–2500.155
–1208.352
–2500.155
100
BT_VCOVSS
1352.595
–2240.766
–1352.595
–2240.766
101
WRF_LNA_5G_GND1P2
–2275.490
–2150.537
2275.490
–2150.537
102
WRF_RFIN_5G
–2251.986
–2411.789
2251.986
–2411.789
103
WRF_RX5G_GND1P2
–2119.686
–1753.146
2119.686
–1753.146
104
WRF_LOGEN_GND1P2
–1902.494
–1572.417
1902.494
–1572.417
105
WRF_PA5G_VBAT_GND3P3
–1800.006
–2098.656
1800.006
–2098.656
106
WRF_RFOUT_5G
–1800.006
–2561.652
1800.006
–2561.652
107
WRF_PA5G_VBAT_VDD3P3
–1600.008
–2570.652
1600.008
–2570.652
108
WRF_PADRV_VBAT_GND3P3
–1400.010
–1671.660
1400.010
–1671.660
109
WRF_PA5G_VBAT_GND3P3
–1400.010
–2098.656
1400.010
–2098.656
110
WRF_PA5G_VBAT_VDD3P3
–1400.010
–2552.652
1400.010
–2552.652
111
WRF_PA2G_VBAT_GND3P3
–1125.249
–1987.776
1125.249
–1987.776
Document No. 002-14784 Rev. *I
Page 59 of 132
PRELIMINARY
CYW4339
Table 17. 286-Bump WLCSP Coordinates (Cont.)
Bump#
Signal Name
Package Bump Side View
(0,0 center of die)
X
Y
Package Top Side View
(0,0 center of die)
X
Y
112
WRF_PADRV_VBAT_VDD3P3
–1089.249
–1666.260
1089.249
–1666.260
113
WRF_PA2G_VBAT_VDD3P3
–1000.014
–2552.652
1000.014
–2552.652
114
WRF_PA2G_VBAT_VDD3P3
–800.016
–2570.652
800.016
–2570.652
115
WRF_RFOUT_2G
–600.018
–2552.652
600.018
–2552.652
116
WRF_PA2G_VBAT_GND3P3
–542.224
–2017.656
542.224
–2017.656
117
WRF_RX2G_GND1P2
–302.509
–1761.939
302.509
–1761.939
118
WRF_RFIN_2G
–200.022
–2471.652
200.022
–2471.652
119
WRF_LNA_2G_GND1P2
–200.022
–2071.656
200.022
–2071.656
120
WRF_RX2G_GND1P2
–165.822
–1590.174
165.822
–1590.174
121
WRF_TSSI_A
–200.022
–943.668
200.022
–943.668
122
WRF_GPIO_OUT
–279.173
–759.168
279.173
–759.168
123
WRF_LOGENG_GND1P2
–338.919
–1125.594
338.919
–1125.594
124
WRF_AFE_GND1P2
–661.308
–1125.594
661.308
–1125.594
125
WRF_TX_GND1P2
–856.014
–1271.664
856.014
–1271.664
126
WRF_VCO_GND1P2
–1032.414
–471.672
1032.414
–471.672
127
WRF_BUCK_VDD1P5
–1066.853
–1047.744
1066.853
–1047.744
128
WRF_BUCK_VDD1P5
–1066.853
–847.746
1066.853
–847.746
129
WRF_BUCK_GND1P5
–1166.852
–647.748
1166.852
–647.748
130
WRF_BUCK_VDD1P5
–1266.851
–1047.744
1266.851
–1047.744
131
WRF_BUCK_VDD1P5
–1266.851
–847.746
1266.851
–847.746
132
WRF_SYNTH_VBAT_VDD3P3
–1503.344
–1089.662
1503.344
–1089.662
133
WRF_MMD_GND1P2
–1627.031
–889.668
1627.031
–889.668
134
WRF_MMD_VDD1P2
–1854.006
–1271.664
1854.006
–1271.664
135
WRF_CP_GND1P2
–1922.892
–980.154
1922.892
–980.154
136
WRF_XTAL_VDD1P5
–1950.522
–353.066
1950.522
–353.066
137
WRF_XTAL_GND1P2
–2000.004
–554.598
2000.004
–554.598
138
WRF_XTAL_IN
–2199.998
–353.066
2199.998
–353.066
139
WRF_PFD_VDD1P2
–2200.002
–1185.062
2200.002
–1185.062
140
WRF_PFD_GND1P2
–2200.002
–985.064
2200.002
–985.064
141
WRF_XTAL_VDD1P2
–2200.002
–753.062
2200.002
–753.062
142
WRF_XTAL_OUT
–2200.002
–553.063
2200.002
–553.063
143
BBPLLAVDD1P2
–2205.429
–52.326
2205.429
–52.326
144
BBPLLAVSS
–2005.431
–57.348
2005.431
–57.348
145
RF_SW_CTRL_0
–1831.200
318.141
1831.200
318.141
146
RF_SW_CTRL_1
–2072.022
449.946
2072.022
449.946
147
RF_SW_CTRL_2
–1691.052
517.221
1691.052
517.221
148
RF_SW_CTRL_3
–1895.118
544.410
1895.118
544.410
149
RF_SW_CTRL_4
–1809.960
772.110
1809.960
772.110
Document No. 002-14784 Rev. *I
Page 60 of 132
PRELIMINARY
CYW4339
Table 17. 286-Bump WLCSP Coordinates (Cont.)
Bump#
Signal Name
Package Bump Side View
(0,0 center of die)
X
Y
Package Top Side View
(0,0 center of die)
X
Y
150
RF_SW_CTRL_5
–1617.639
713.790
1617.639
713.790
151
RF_SW_CTRL_6
–2129.154
817.452
2129.154
817.452
152
RF_SW_CTRL_7
–1573.278
922.392
1573.278
922.392
153
RF_SW_CTRL_8
–1749.264
1019.259
1749.264
1019.259
154
RF_SW_CTRL_9
–1944.888
972.936
1944.888
972.936
155
OTP_VDD33
–1400.001
808.353
1400.001
808.353
156
VDDIO_RF
–1399.398
343.350
1399.398
343.350
157
VDDIO_RF
–1400.001
543.348
1400.001
543.348
158
NC
–2055.795
2207.556
2055.795
2207.556
159
PAD_PLL_AVDD1P2
–1943.295
2041.056
1943.295
2041.056
160
NC
–1689.455
2041.056
1689.455
2041.056
161
PAD_PLL_AVSS
–2280.795
2207.556
2280.795
2207.556
162
NC
–2168.295
2041.056
2168.295
2041.056
163
PAD_PLL_AVSS
–1830.795
2207.556
1830.795
2207.556
164
NC
–1576.959
2207.556
1576.959
2207.556
165
NC
–2168.295
2374.758
2168.295
2374.758
166
NC
–1943.295
2374.758
1943.295
2374.758
167
PAD_RXTX_AVDD1P2
–1689.455
2374.758
1689.455
2374.758
168
PAD_RXTX_AVSS
–2280.795
2541.258
2280.795
2541.258
169
NC
–1830.795
2541.258
1830.795
2541.258
170
NC
–2055.795
2541.258
2055.795
2541.258
171
SDIO_CLK
–1269.996
1963.350
1269.996
1963.350
172
SDIO_CMD
–1269.996
2168.352
1269.996
2168.352
173
SDIO_DATA_0
–1040.001
1963.350
1040.001
1963.350
174
SDIO_DATA_1
–1040.001
2168.352
1040.001
2168.352
175
SDIO_DATA_2
–830.004
1963.350
830.004
1963.350
176
SDIO_DATA_3
–735.000
2168.352
735.000
2168.352
177
VDDIO_SD
–1040.001
1763.352
1040.001
1763.352
178
VDDIO_SD
–830.004
1763.352
830.004
1763.352
179
STROBE
–545.001
1963.350
545.001
1963.350
180
DATA
–240.000
1963.350
240.000
1963.350
181
RREFHSIC
–805.002
1568.349
805.002
1568.349
182
AGND12PLL
–605.004
1553.346
605.004
1553.346
183
DVDD12HSIC2
–394.998
1763.352
394.998
1763.352
184
AVDD12PLL
–605.004
1763.352
605.004
1763.352
185
DVDD12HSIC
–394.998
1553.346
394.998
1553.346
186
NC
–15.000
2168.352
15.000
2168.352
187
NC
4.998
1768.347
–4.998
1768.347
Document No. 002-14784 Rev. *I
Page 61 of 132
PRELIMINARY
CYW4339
Table 17. 286-Bump WLCSP Coordinates (Cont.)
Bump#
Signal Name
Package Bump Side View
(0,0 center of die)
X
Package Top Side View
(0,0 center of die)
Y
X
Y
188
NC
–5.001
1968.354
5.001
1968.354
189
GPIO_0
239.997
1968.354
–239.997
1968.354
190
GPIO_1
239.997
1768.347
–239.997
1768.347
191
GPIO_2
290.001
2168.352
–290.001
2168.352
192
GPIO_3
284.997
1568.349
–284.997
1568.349
193
GPIO_4
675.003
1908.351
–675.003
1908.351
194
GPIO_5
485.004
1568.349
–485.004
1568.349
195
GPIO_6
675.003
1708.353
–675.003
1708.353
196
GPIO_7
689.997
1508.346
–689.997
1508.346
197
GPIO_8
920.001
1568.349
–920.001
1568.349
198
GPIO_9
820.002
1348.353
–820.002
1348.353
199
GPIO_10
820.002
1073.349
–820.002
1073.349
200
GPIO_11
1119.999
1073.349
–1119.999
1073.349
201
GPIO_12
1119.999
1338.354
–1119.999
1338.354
202
GPIO_14
1180.002
1738.350
–1180.002
1738.350
203
GPIO_13
1180.002
1538.352
–1180.002
1538.352
204
GPIO_15
1180.002
1973.349
–1180.002
1973.349
205
JTAG_SEL
1119.999
2168.352
–1119.999
2168.352
206
VSSC
699.996
668.349
–699.996
668.349
207
VSSC
699.996
468.351
–699.996
468.351
208
VSSC
900.003
468.351
–900.003
468.351
209
VSSC
900.003
668.349
–900.003
668.349
210
VDDIO
605.001
1148.346
–605.001
1148.346
211
VDDIO
384.996
1368.351
–384.996
1368.351
212
VDDIO
605.001
948.348
–605.001
948.348
213
VDDC_PHY
–2120.001
1213.353
2120.001
1213.353
214
VDDC_PHY
–1920.003
1213.353
1920.003
1213.353
215
VDDC
–1689.999
–71.649
1689.999
–71.649
216
VDDC
–1490.001
–71.649
1490.001
–71.649
217
VDDC_PHY
–1490.001
128.349
1490.001
128.349
218
VDDC_PHY
–1249.998
128.349
1249.998
128.349
219
VDDC_PHY
–840.003
578.349
840.003
578.349
220
VDDC_PHY
–639.996
578.349
639.996
578.349
221
VDDC_PHY
–269.997
628.353
269.997
628.353
222
VDDC_PHY
–269.997
828.351
269.997
828.351
223
VDDC
–195.000
1568.349
195.000
1568.349
224
VDDC
–195.000
1768.347
195.000
1768.347
225
VDDC_PHY
–195.000
1268.352
195.000
1268.352
Document No. 002-14784 Rev. *I
Page 62 of 132
PRELIMINARY
CYW4339
Table 17. 286-Bump WLCSP Coordinates (Cont.)
Bump#
Signal Name
Package Bump Side View
(0,0 center of die)
X
Y
Package Top Side View
(0,0 center of die)
X
Y
226
VDDC
4.998
–6.651
–4.998
–6.651
227
VDDC_SUBCORE
4.998
193.347
–4.998
193.347
228
VDDC_SUBCORE
4.998
393.354
–4.998
393.354
229
VDDC
4.998
628.353
–4.998
628.353
230
VDDC
4.998
828.351
–4.998
828.351
231
VDDC_SUBCORE
4.998
1028.349
–4.998
1028.349
232
VDDC_SUBCORE
4.998
1568.349
–4.998
1568.349
233
VDDC_SUBCORE
4.998
1268.352
–4.998
1268.352
234
VDDC
120.000
–216.648
–120.000
–216.648
235
VDDC
319.998
–216.648
–319.998
–216.648
236
VDDC
405.003
1148.346
–405.003
1148.346
237
VDDC_SUBCORE
405.003
948.348
–405.003
948.348
238
VDDC
689.997
–211.653
–689.997
–211.653
239
VDDC
890.004
–211.653
–890.004
–211.653
240
VDDC_SUBCORE
1090.002
–11.646
–1090.002
–11.646
241
VDDC_SUBCORE
1396.119
–24.588
–1396.119
–24.588
242
VSSC
–1374.999
1263.348
1374.999
1263.348
243
VSSC
–1269.996
1563.354
1269.996
1563.354
244
VSSC
–1175.001
1263.348
1175.001
1263.348
245
VSSC
–1269.996
1763.352
1269.996
1763.352
246
VSSC
–1249.998
–71.649
1249.998
–71.649
247
VSSC
–975.003
1263.348
975.003
1263.348
248
VSSC
–1050.000
–71.649
1050.000
–71.649
249
VSSC
–1040.001
1563.354
1040.001
1563.354
250
VSSC
–840.003
–71.649
840.003
–71.649
251
VSSC
–840.003
128.349
840.003
128.349
252
VSSC
–840.003
328.347
840.003
328.347
253
VSSC
–840.003
828.351
840.003
828.351
254
VSSC
–840.003
1028.349
840.003
1028.349
255
VSSC
–805.002
1368.351
805.002
1368.351
256
VSSC
–639.996
828.351
639.996
828.351
257
VSSC
–639.996
1028.349
639.996
1028.349
258
VSSC
–439.998
128.349
439.998
128.349
259
VSSC
–439.998
328.734
439.998
328.734
260
VSSC
–439.998
–71.649
439.998
–71.649
261
VSSC
94.998
–606.654
–94.998
–606.654
262
VSSC
94.998
–806.652
–94.998
–806.652
263
VSSC
204.996
193.347
–204.996
193.347
Document No. 002-14784 Rev. *I
Page 63 of 132
PRELIMINARY
CYW4339
Table 17. 286-Bump WLCSP Coordinates (Cont.)
Bump#
Signal Name
Package Bump Side View
(0,0 center of die)
X
Y
Package Top Side View
(0,0 center of die)
X
Y
264
VSSC
204.996
1028.349
–204.996
1028.349
265
VSSC
204.996
628.353
–204.996
628.353
266
VSSC
204.996
828.351
–204.996
828.351
267
VSSC
133.104
–1457.550
–133.104
–1457.550
268
VSSC
305.004
–446.652
–305.004
–446.652
269
VSSC
204.996
393.354
–204.996
393.354
270
VSSC
499.998
193.347
–499.998
193.347
271
VSSC
457.401
–1457.550
–457.401
–1457.550
272
VSSC
499.998
–806.652
–499.998
–806.652
273
VSSC
505.002
–446.652
–505.002
–446.652
274
VSSC
499.998
468.351
–499.998
468.351
275
VSSC
499.998
668.349
–499.998
668.349
276
VSSC
499.998
–6.651
–499.998
–6.651
277
VSSC
699.996
–806.652
–699.996
–806.652
278
VSSC
699.996
–606.654
–699.996
–606.654
279
VSSC
699.996
–6.651
–699.996
–6.651
280
VSSC
660.603
–1457.550
–660.603
–1457.550
281
VSSC
900.003
68.346
–900.003
68.346
282
VSSC
1090.002
–211.653
–1090.002
–211.653
283
VSSC
1100.001
668.349
–1100.001
668.349
284
VSSC
1229.997
508.347
–1229.997
508.347
285
VSSC
1229.997
308.349
–1229.997
308.349
286
VSSC
1290.000
–211.653
–1290.000
–211.653
Document No. 002-14784 Rev. *I
Page 64 of 132
PRELIMINARY
CYW4339
12.3 Signal Descriptions
The signal name, type, and description of each pin in the CYW4339 is listed in Table 18. The symbols shown under Type indicate pin
directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up
resistor and PD = weak internal pull-down resistor), if any.
Table 18. FCFBGA, WLBGA, and WLCSP Signal Descriptions
WLBGA
Ball#
FCFBGA
Ball#
WLCSP
Bump#
Signal Name
Type
Description
WLAN and Bluetooth RF Signal Interface
N7
W10
118
WRF_RFIN_2G
I
2.4 GHz Bluetooth and WLAN receiver shared
input.
N5
W8
93
BT_RF_TX
O
Bluetooth PA output.
N12
W18
102
WRF_RFIN_5G
I
5 GHz WLAN receiver input.
2.4 GHz WLAN PA output.
N8
W12
115
WRF_RFOUT_2G
O
N11
W16
106
WRF_RFOUT_5G
O
5 GHz WLAN PA output.
J7
V11
121
WRF_TSSI_A
I
5 GHz TSSI input from an optional external
power amplifier/power detector.
H7
V10
122
WRF_RES_EXT/WRF_GPIO_OUT/WRF_TSSI_G
I/O
GPIO or 2.4 GHz TSSI input from an optional
external power amplifier/power detector.
Programmable RF switch control lines. The
control lines are programmable via the driver
and NVRAM file.
RF Switch Control Lines
F12
J19
145
RF_SW_CTRL_0
O
F11
J17
146
RF_SW_CTRL_1
O
E12
J18
147
RF_SW_CTRL_2
O
E11
G19
148
RF_SW_CTRL_3
O
D12
H17
149
RF_SW_CTRL_4
O
F8
G17
150
RF_SW_CTRL_5
O
H9
G18
151
RF_SW_CTRL_6
O
G7
J16
152
RF_SW_CTRL_7
O
E10
G16
153
RF_SW_CTRL_8
O
F5
H16
154
RF_SW_CTRL_9
O
WLAN PCI Express Interface
OD
PCIe clock request signal which indicates
when the REFCLK to the PCIe interface can be
gated.
1 = the clock can be gated
0 = the clock is required
I (PU)
PCIe System Reset. This input is the PCIe
reset as defined in the PCIe base specification
version 1.1.
–
A19
–
PCIE_CLKREQ_L
–
B16
–
PERST_L
–
B13
–
PAD_RDN0
I
–
C13
–
PAD_RDP0
I
–
A18
–
PAD_REFCLKN
I
–
B18
–
PAD_REFCLKP
I
–
B15
–
PAD_TDN0
O
–
B14
–
PAD_TDP0
O
Document No. 002-14784 Rev. *I
Receiver differential pair (x1 lane).
PCIE Differential Clock inputs (negative and
positive). 100 MHz differential.
Transmitter differential pair (x1 lane).
Page 65 of 132
PRELIMINARY
CYW4339
Table 18. FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)
WLBGA
Ball#
FCFBGA
Ball#
WLCSP
Bump#
Signal Name
Description
Type
–
B19
–
PCI_PME_L
OD
PCI power management event output. Used to
request a change in the device or system
power state. The assertion and deassertion of
this signal is asynchronous to the PCIe
reference clock. This signal has an open-drain
output structure, as per the PCI Bus Local Bus
Specification, revision 2.3.
–
–
–
PAD_TESTP
–
PCIe test pin.
–
–
–
PAD_TESTN
–
WLAN SDIO Bus Interface
Note: These signals can also have alternate functionality depending on package and host interface mode. Refer to Table 26, “CYW4339 GPIO/
SDIO Alternative Signal Functions,” for additional details.
B11
B11
171
SDIO_CLK
I
B12
C11
172
SDIO_CMD
I/O
SDIO command line.
B10
C10
173
SDIO_DATA_0
I/O
SDIO data line 0.
SDIO data line 1.
SDIO clock input.
C10
A11
174
SDIO_DATA_1
I/O
D10
C9
175
SDIO_DATA_2
I/O
SDIO data line 2.
C11
B9
176
SDIO_DATA_3
I/O
SDIO data line 3.
WLAN GPIO Interface
Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to behave as various specific functions. See Table 26, “CYW4339
GPIO/SDIO Alternative Signal Functions,” for additional details.
B6
D9
189
GPIO_0
I/O
C6
C16
190
GPIO_1
I/O
D6
C8
191
GPIO_2
I/O
B5
A7
192
GPIO_3
I/O
C5
B5
193
GPIO_4
I/O
D5
A5
194
GPIO_5
I/O
C4
C7
195
GPIO_6
I/O
D4
B7
196
GPIO_7
I/O
H1
E8
197
GPIO_8
I/O
–
–
198
GPIO_9
I/O
–
–
199
GPIO_10
I/O
–
–
200
GPIO_11
I/O
–
–
201
GPIO_12
I/O
–
A3
202
GPIO_14
I/O
–
D8
203
GPIO_13
I/O
–
D6
204
GPIO_15
I/O
E5
C6
205
JTAG_SEL
Programmable GPIO pins.
Note: These GPIO signals can be configured by
software: as either inputs or outputs, to have
internal pull-ups or pull-downs enabled or
disabled, and to use either a high or low polarity
upon assertion.
JTAG Interface
I/O
JTAG select. Pull high to select the JTAG
interface. If the JTAG interface is not used, this
pin may be left floating or connected to ground.
Note: See Table 26, “CYW4339 GPIO/SDIO
Alternative Signal Functions,” for the JTAG
signal pins.
Document No. 002-14784 Rev. *I
Page 66 of 132
PRELIMINARY
CYW4339
Table 18. FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)
WLBGA
Ball#
FCFBGA
Ball#
WLCSP
Bump#
Signal Name
Description
Type
Clocks
H12
P19
138
WRF_XTAL_IN
I
XTAL oscillator input.
J12
R19
142
WRF_XTAL_OUT
O
XTAL oscillator output.
B4
J7
39
LPO_IN
I
External sleep clock input (32.768 kHz).
O
Reference clock request (shared by BT and
WLAN).
H3
W3
56
CLK_REQ
–
N3
49
BT_SF_MOSI
I/O
SFLASH_SI
–
P3
46
BT_SF_CLK
I/O
SFLASH_CLK
–
R1
47
BT_SF_CSN
I/O
SFLASH_CSN
I/O
SFLASH_SO
SFLASH
–
R2
48
BT_SF_MISO
N2
–
78
FM_RFIN
I
FM Radio antenna port.
–
–
75
FM_RFAUX
I
FM radio auxiliary antenna port.
K1
–
86
FM_DAC_VOUT1/FM_AOUT1
O
FM DAC output 1.
O
FM DAC output 2.
I/O
PCM clock; can be master (output) or slave
(input).
L1
–
85
FM_DAC_VOUT2/FM_AOUT2
G2
–
46
BT_PCM_CLK/BT_PCMCLK
G1
–
48
BT_PCM_IN
I
PCM data input.
J3
–
49
BT_PCM_OUT
O
PCM data output.
H2
–
47
BT_PCM_SYNC
I/O
PCM sync; can be master (output) or slave
(input).
–
N1
40
HUSB_DN
I/O
USB (Host) data negative. Negative terminal of
the USB transceiver.
–
N2
41
HUSB_DP
I/O
USB (Host) data positive. Positive terminal of
the USB transceiver.
Bluetooth PCM
Bluetooth USB Interface
Bluetooth UART
E6
T3
50
BT_UART_CTS_N/
BT_UART_CTS
I
UART clear-to-send. Active-low clear-to-send
signal for the HCI UART interface.
F6
V1
51
BT_UART_RTS_N/
BT_UART_RTS/BT_LED
O
UART request-to-send. Active-low request-tosend signal for the HCI UART interface. BT
LED control pin.
G6
W1
52
BT_UART_RXD/ BT_RFDISABLE2
I
UART serial input. Serial data input for the HCI
UART interface. BT RF disable pin 2.
F7
W2
53
BT_UART_TXD
O
UART serial output. Serial data output for the
HCI UART interface.
Bluetooth/I2S
J6
R3
44
BT_I2S_CLK
I/O
I2S clock, can be master (output) or slave
(input).
K6
U2
42
BT_I2S_DO
I/O
I2S data output.
K5
U3
43
BT_I2S_DI
I/O
I2S data input.
Document No. 002-14784 Rev. *I
Page 67 of 132
PRELIMINARY
CYW4339
Table 18. FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)
WLBGA
Ball#
FCFBGA
Ball#
WLCSP
Bump#
Signal Name
Description
Type
I/O
I2S WS; can be master (output) or slave (input).
I/O
ARM JTAG mode.
BT_GPIO_2
I/O
Bluetooth general-purpose I/O.
60
BT_GPIO_3
I/O
Bluetooth general-purpose I/O.
61
BT_GPIO_4
I/O
Bluetooth general-purpose I/O.
Bluetooth general-purpose I/O.
BT analog GPIO pin.
H6
U1
45
BT_I2S_WS
–
U1
55
BT_TM1
–
–
59
–
–
–
C19
Bluetooth Test Mode
Bluetooth GPIO
–
–
62
BT_GPIO_5
I/O
M6
–
91
BT_AGPIO
I/O
Miscellaneous
B3
D5
3
WL_REG_ON
I
Used by PMU to power up or power down the
internal CYW4339 regulators used by the
WLAN section. Also, when deasserted, this pin
holds the WLAN section in reset. This pin has
an internal 200 kΩ pull-down resistor that is
enabled by default. It can be disabled through
programming.
D3
C5
32
BT_REG_ON
I
Used by PMU to power up or power down the
internal CYW4339 regulators used by the
Bluetooth section. Also, when deasserted, this
pin holds the Bluetooth section in reset. This
pin has an internal 200 kΩ pull-down resistor
that is enabled by default. It can be disabled
through programming.
K3
M3
57
BT_DEV_WAKE
I/O
Bluetooth DEV_WAKE.
J2
V3
58
BT_HOST_WAKE
I/O
Bluetooth HOST_WAKE.
Unsupported. This pin can be connected to
ground or left unconnected (no-connect).
Unsupported. This pin can be connected to
ground or left unconnected (no-connect).
B8
–
179
HSIC_STROBE/STROBE
I/O
B7
–
180
HSIC_DATA/DATA
I/O
B9
–
181
RREFHSIC
C2
C3
15
SR_VDDBATA5V
C1
B1, B2, C1
11, 12, 14
I
Unsupported. Leave this pin unconnected (noconnect).
I
Quiet VBAT.
SR_VDDBATP5V
I
Power VBAT.
Cbuck switching regulator output. Refer to
Table 42 for details of the inductor and
capacitor required on this output.
LNLDO input.
Integrated Voltage Regulators
B2
A2, B2
6–10, 13
SR_VLX
O
D1
F1, F2
16, 19, 23, 26
LDO_VDD1P5
I
LDO VBAT.
F2
L1
27, 30, 34, 36
LDO_VDDBAT5V
I
H11
N19
136
WRF_XTAL_VDD1P5/WRF_XTAL_BUCK_VDD1P5
I
XTAL LDO input (1.35V).
K12
T19
141
WRF_XTAL_VDD1P2/WRF_XTAL_OUT_VDD1P2
O
XTAL LDO output (1.2V).
E2
K2
24
VOUT_LNLDO
O
Output of LNLDO.
D2
G2
17, 18, 20
VOUT_CLDO
O
Output of core LDO.
F1
J2
33
VOUT_BTLDO2P5
O
Output of BT LDO.
Document No. 002-14784 Rev. *I
Page 68 of 132
PRELIMINARY
CYW4339
Table 18. FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)
WLBGA
Ball#
E1
FCFBGA
Ball#
H1
WLCSP
Bump#
22, 25, 28
Signal Name
Description
Type
VOUT_3P3
O
LDO 3.3V output.
O
Voltage sense pin for LDO 3.3V output.
–
H2
29
VOUT_3P3_SENSE
N6
V8
92
BT_PAVDD/BT_PAVDD2P5
N4
W5
96
Bluetooth Supplies
PWR
Bluetooth PA power supply.
BT_LNAVDD/BT_LNAVDD1P2
PWR
Bluetooth LNA power supply.
Bluetooth IF block power supply.
L4
W6
90
BT_IFVDD/BT_IFVDD1P2
PWR
M4
V6
98
BT_PLLVDD/BT_PLLVDD1P2
PWR
Bluetooth RF PLL power supply.
N3
V5
99
BT_VCOVDD/BT_VCOVDD1P2
PWR
Bluetooth RF power supply.
–
–
55
BT_VDDC_ISO_1
PWR
Core supply for power-on/off island VDDC_G.
BT_VDDC_ISO_2
PWR
Core supply for power-on/off island VDDB.
FM_VCOVDD
PWR
FM VCO supply.
FM LNA power supply.
–
–
66
FM Transceiver Supplies
–
–
87
–
–
80
FM_LNAVDD
PWR
N1
–
–
FM_LNAVCOVDD1P2
PWR
FM LNA VCO power supply.
L2
–
84
FM_PLLVDD/FM_PLLVDD1P2
PWR
FM PLL power supply.
–
–
79
FM_IFVDD
PWR
FM IF power supply.
FM DAC power supply.
–
–
82
FM_DAC_AVDD
PWR
J1
–
–
FM_AUDIOVDD1P2
PWR
FM Audio power supply.
Internal capacitor-less LDO supply.
WLAN Supplies
–
L15
127, 128, 130,
131
WRF_BUCK_VDD1P5
PWR
H8
–
–
WRF_WL_LNLDOIN_VDD1P5
PWR
LNLDO 1.35V supply.
K9
V19
132
WRF_SYNTH_VBAT_VDD3P3
PWR
Synth VDD 3.3V supply.
L9
V14
112
WRF_PADRV_VBAT_VDD3P3
PWR
PA Driver VBAT supply.
N10
V15
107, 110
WRF_PA5G_VBAT_VDD3P3
PWR
5 GHz PA 3.3V VBAT supply.
2 GHz PA 3.3V VBAT supply.
N9
V13
113, 114
WRF_PA2G_VBAT_VDD3P3
PWR
K10
U18
134
WRF_MMD_VDD1P2
PWR
1.2V supply.
K11
T18
139
WRF_PFD_VDD1P2
PWR
1.2V supply.
–
L18
155
OTP_VDD33
PWR
OTP 3.3V supply.
C7, C12, G4,
G5, G8
E10, E11,
G14, H14, K7
213–241
VDDC/WL_VDDC
PWR
1.2V core supply for WLAN.
F3
B3
210–212
VDDIO /VDDIO2
PWR
1.8V–3.3V supply for WLAN. Must be directly
connected to PMU_VDDIO and BT_VDDIO on
the PCB.
H5, J4
L7, M7
67–74
BT_VDDC
PWR
1.2V core supply for BT.
–
L2
37, 38
PMU_VDDIO
PWR
1.8V–3.3V supply for PMU controls. Must be
directly connected to VDDIO and BT_VDDIO
on the PCB.
H4
L3
63–65
BT_VDDIO
PWR
1.8V–3.3V supply for BT. Must be directly
connected to PMU_VDDIO and VDDIO on the
PCB.
Miscellaneous Supplies
Document No. 002-14784 Rev. *I
Page 69 of 132
PRELIMINARY
CYW4339
Table 18. FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)
WLBGA
Ball#
D9
FCFBGA
Ball#
A9
WLCSP
Bump#
177, 178
Signal Name
Description
Type
VDDIO_SD
PWR
IO supply for RF switch control pads (3.3V).
1.8V–3.3V supply for SDIO pads.
E7
K17
156, 157
VDDIO_RF
PWR
C8
–
184
AVDD12PLL/HSIC_AVDD12PLL
PWR
HSIC is not supported. Connect this pin to
ground to minimize leakage.
C9
–
185
DVDD12HSIC/HSIC_DVDD12
PWR
HSIC is not supported. Connect this pin to
ground to minimize leakage.
G12
L19
143
BBPLL_AVDD1P2
PWR
1.2V supply for baseband PLL.
–
D18
159
PLL_AVDD1P2
PWR
1.2V supply for PCIe PLL.
–
D19
167
AVDD1P2
PWR
1.2V supply for PCIe.
H10
L12
126
WRF_VCO_GND1P2/
WRF_VCO_GND
GND
VCO/LOGEN ground.
–
–
183
DVDD12HSIC2
GND
Supply for DVDD12HSIC2.
K7
R12
124
WRF_AFE_GND1P2
GND
AFE ground.
Internal capacitor-less LDO ground.
Ground
J8
M12
129
WRF_BUCK_GND1P5
GND
M7
T10
119
WRF_LNA_2G_GND1P2
GND
2 GHz internal LNA ground.
M12
T15
101
WRF_LNA_5G_GND1P2
GND
5 GHz internal LNA ground.
L8
R13
125
WRF_TX_GND1P2
GND
TX ground.
PAD ground.
L10
R14
108
WRF_PADRV_VBAT_GND3P3
GND
G11
M15, P18
137
WRF_XTAL_GND1P2
GND
XTAL ground.
L7
P11
117, 120
WRF_RX2G_GND1P2
GND
RX 2GHz ground.
L12
T16
103
WRF_RX5G_GND1P2
GND
RX 5GHz ground.
LOGEN ground.
–
R15
104
WRF_LOGEN_GND1P2
GND
–
M11
123
WRF_LOGENG_GND1P2
GND
LOGEN ground.
L11
–
–
WRF_LO_GND1P2_1
GND
LO ground.
K8
–
–
WRF_LO_GND1P2_2
GND
LO ground.
5 GHz PA ground.
–
U15, V16
105, 109
WRF_PA5G_VBAT_GND3P3
GND
–
R11, V12
111, 116
WRF_PA2G_VBAT_GND3P3
GND
2 GHz PA ground.
M11
–
–
WRF_PA_VBAT_GND3P3_1
GND
PA ground.
M10
–
–
WRF_PA_VBAT_GND3P3_2
GND
PA ground.
PA ground.
M9
–
–
WRF_PA_VBAT_GND3P3_3
GND
M8
–
–
WRF_PA_VBAT_GND3P3_4
GND
PA ground.
J9
P14
133
WRF_MMD_GND1P2
GND
Ground.
J11
N15
135
WRF_CP_GND1P2/
WRF_CP_GND
GND
Ground.
J10
P15
140
WRF_PFD_GND1P2
GND
Ground.
Core ground for WLAN and BT.
D7, D11, E3,
E8, J5, K4
H9–H12,
J8, J12, K8,
K12, L8, L11,
M8–M10
31, 35, 161,
163, 168,
242–286
VSSC
GND
B1
D1, E1, E2
1, 2, 4, 5
SR_PVSS
GND
Power ground.
C3
H8
21
PMU_AVSS
GND
Quiet ground.
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CYW4339
Table 18. FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)
WLBGA
Ball#
D8
FCFBGA
Ball#
–
WLCSP
Bump#
182
Signal Name
Description
Type
AGND12PLL/HSIC_AGNDPLL
GND
Bluetooth PA ground.
PLL ground.
M5
T8
94
BT_PAVSS
GND
–
R8
95
BT_LNAVSS
GND
Bluetooth LNA ground.
L6
R9
89
BT_IFVSS
GND
Bluetooth IF block ground.
L5
R7
97
BT_PLLVSS
GND
Bluetooth PLL ground.
Bluetooth VCO ground.
M3
P8
100
BT_VCOVSS
GND
M1
–
83
FM_VCOVSS
GND
FM VCO Ground.
M2
–
77
FM_LNAVSS
GND
FM LNA Ground.
L3
–
88
FM_PLLVSS
GND
FM PLL Ground.
FM IF ground.
–
–
76
FM_IFVSS
GND
–
–
81
FM_DAC_VSS
GND
FM DAC ground.
K2
–
–
FM_AUDIOVSS
GND
FM Audio Ground.
G10
L13
144
AVSS_BBPLL/BBPLLAVSS
GND
Baseband PLL ground.
PCIe ground.
–
D13, D16
–
PCIE_VSS
GND
–
–
209
VSSC
GND
Ground.
–
–
208
VSSC
GND
Ground.
–
–
207
VSSC
GND
Ground.
VSSC
GND
Ground.
–
–
206
No Connect
A2, A3, A4,
A6, A7, A9,
A10, A11
F5, G5, W19
158, 160, 162,
164, 165, 166,
169, 170, 186,
187, 188
–
NC
No connect
12.4 WLAN GPIO Signals and Strapping Options
The pins listed in Table 19 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few
milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative
function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor
that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a
10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 19. WLAN GPIO Functions and Strapping Options
Pin Name
FCBGA
Pin #
WLBGA
Pin #
WLCSP
Pin #
Default Function
Description
GPIO_7
B7
D4
196
1
SDIO_SEL1
GPIO_8
E8
H1
197
0
SDIO_PADVDDIO
GPIO_14
A3
–
202
0
PCIE_DISABLE
SDIO_CLK
B11
B11
171
1
CPU-LESS/SPROM_DISABLE1
SDIO_DATA_2
C9
D10
175
1
SPI_SEL1
1. See Table 20, Table 21, and Table 22.
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CYW4339
Table 20. SDIO/ I/O Voltage Selection (All Packages)
SDIO_SEL
SPI_SEL
SDIO_PADVDDIO
Mode
1
X
0
1.8V I/O
1
X
1
3.3V I/O
0
1
0
1.8V I/O
0
1
1
3.3V I/O
0
0
X
3.3V I/O
Table 21. Host Interface Selection (FCBGA Package only)
SDIO_SEL
SPI_SEL
PCIE_DISABLE
SPROM_DISABLE1
0
X
Mode
1
X
SDIO and PCIe mode
1
X
1
X
SDIO mode
0
1
0
X
PCIe mode
0
1
1
X
reserved
0
0
0
0
PCIe mode with SPROM on the SDIO pins2
0
0
0
1
PCIe mode (no SPROM)
1. SPROM_DISABLE strapping is valid only in the FCBGA package and only used if SDIO is disabled.
2. SPROM is only available for PCIe mode.
Table 22. Host Interface Selection (WLBGA and WLCSP Packages1)
SDIO_SEL
SPI_SEL
CPULESS
Mode
1
X
X
SDIO Mode (3.3V or 1.8V I/O)
0
1
X
reserved
0
0
0
Unsupported
0
0
1
Unsupported
1. PCIe and SPROM modes are not available in the WLBGA and WLCSP packages.
Table 23. OTP/SPROM Select
Mode
SDIO CIS
PCIe Disabled
From OTP if OTP is programmed;
PCIe Enabled
Default CIS
PCIE Configuration
–
ELSE default CIS.
From SPROM if SPROM is present;
ELSE from OTP (if programmed);
ELSE default configuration.
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CYW4339
12.4.1 Multiplexed Bluetooth GPIO Signals
The Bluetooth GPIO pins (BT_GPIO_0 to BT_GPIO_7) are multiplexed pins and can be programmed to be used as GPIOs or for
other Bluetooth interface signals such as I2S. The specific function for a given BT_GPIO_X pin is chosen by programming the Pad
Function Control register for that specific pin. Table 24 shows the possible options for each BT_GPIO_X pin. Note that each
BT_GPIO_X pin's Pad Function Control register setting is independent (BT_GPIO_1 can be set to pad function 7 at the same time
that BT_GPIO_3 is set to pad function 0). When the Pad Function Control register is set to 0, the BT_GPIOs do not have specific
functions assigned to them and behave as generic GPIOs. The A_GPIO_X pins described below are multiplexed behind the
CYW4339's PCM and I2S interface pins.
Table 24. GPIO Multiplexing Matrix
Pin Name
Pad Function Control Register Setting
0
1
2
3
4
5
6
7
15
BT_UART_CTS_
N
UART_CTS
_N
–
–
–
–
–
–
A_GPIO[1]
–
BT_UART_RTS_
N
UART_RTS_
N
–
–
–
–
–
–
A_GPIO[0]
–
BT_UART_RXD
UART_RXD
–
–
–
–
–
–
GPIO[5]
–
BT_UART_TXD
UART_TXD
–
–
–
–
–
–
GPIO[4]
–
BT_PCM_IN
A_GPIO[3]
PCM_IN
PCM_IN
HCLK
–
–
–
I2S_SSDI/
MSDI
SF_MISO
BT_PCM_OUT
A_GPIO[2]
PCM_OUT
PCM_OUT
LINK_IND
–
I2S_MSD
O
–
I2S_SSDO
SF_MOSI
BT_PCM_SYNC
A_GPIO[1]
PCM_SYN
C
PCM_SYN
C
HCLK
INT_LPO
I2S_MW
S
–
I2S_SWS
SF_SPI_CS
N
BT_PCM_CLK
A_GPIO[0]
PCM_CLK
PCM_CLK
–
–
I2S_MSC
K
–
I2S_SSCK
SF_SPI_CL
K
BT_I2S_DO
A_GPIO[5]
PCM_OUT
–
–
I2S_SSDO
I2S_MSD
O
–
STATUS
–
BT_I2S_DI
A_GPIO[6]
PCM_IN
–
HCLK
I2S_SSDI/
MSDI
–
–
TX_CON_FX
–
BT_I2S_WS
GPIO[7]
PCM_SYN
C
–
LINK_IND
–
I2S_MW
S
–
I2S_SWS
–
BT_I2S_CLK
GPIO[6]
PCM_CLK
–
–
INT_LPO
I2S_MSC
K
–
I2S_SSCK
–
BT_GPIO_51
GPIO[5]
HCLK
–
I2S_MSC
K
I2S_SSCK
–
–
CLK_REQ
–
BT_GPIO_41
GPIO[4]
LINK_IND
–
I2S_MSD
O
I2S_SSDO
–
–
–
–
BT_GPIO_31
GPIO[3]
–
–
I2S_MWS
I2S_SWS
–
–
–
–
1
GPIO[2]
–
–
–
I2S_SSDI/
MSDI
–
–
–
–
BT_GPIO_1
GPIO[1]
–
–
–
–
–
–
CLASS1[2]
–
BT_GPIO_0
GPIO[0]
–
–
–
clk_12p288
–
–
–
–
CLK_REQ
WL/
BT_CLK_RE
Q
–
–
–
–
–
–
A_GPIO[7]
–
BT_GPIO_2
1. Available only in the WLCSP package.
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CYW4339
The multiplexed GPIO signals are described in Table 25.
Table 25. Multiplexed GPIO Signals
Pin Name
Type
Description
UART_CTS_N
I
Host UART clear to send.
UART_RTS_N
O
Device UART request to send.
UART_RXD
I
Device UART receive data.
UART_TXD
O
Host UART transmit data.
PCM_IN
I
PCM data input.
PCM_OUT
O
PCM data output.
PCM_SYNC
I/O
PCM sync signal, can be master (output) or slave (input).
PCM_CLK
I/O
PCM clock, can be master (output) or slave (input).
GPIO[7:0]
I/O
General-purpose I/O.
A_GPIO[7:0]
I/O
A group general-purpose I/O.
I2S_MSDO
O
I2S master data output.
I2S_MWS
O
I2S master word select.
I2S_MSCK
O
I2S master clock.
I2S_SSCK
I
I2S slave clock.
I2S_SSDO
O
I2S slave data output.
I2S_SWS
I
I2S slave word select.
I2S_SSDI/MSDI
I
I2S slave/master data input.
STATUS
O
Signals Bluetooth priority status.
TX_CON_FX
I
WLAN-BT coexist. Transmission confirmation; permission for BT to transmit.
RF_ACTIVE
O
WLAN-BT coexist. Asserted (logic high) during local BT RX and TX slots.
LINK_IND
O
BT receiver/transmitter link indicator.
CLK_REQ
O
WLAN/BT clock request output.
SF_SPI_CLK
O
SFlash SCLK: serial clock (output from master).
SF_MISO
I
SFlash MISO; SOMI: master input, slave output (output from slave).
SF_MOSI
O
SFlash MOSI; SIMO: master output, slave input (output from master).
SF_SPI_CSN
O
SFlash SS: slave select (active low, output from master).
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CYW4339
12.5 GPIO/SDIO Alternative Signal Functions
Table 26. CYW4339 GPIO/SDIO Alternative Signal Functions 1 2
Pins
WLBGA SDIO
WLCSP SDIO
FCBGA PCIE
FCBGA SDIO
GPIO_0
WL_HOST_WAKE
WL_HOST_WAKE
WL_HOST_WAKE
GPIO_1
WL_DEV_WAKE
WL_DEV_WAKE
WL_RF_DISABLE_L
WL_HOST_WAKE
WL_RF_DISABLE_L
GPIO_2
TCK, GCI_GPIO_1, or
UART RX
TCK or GCI_GPIO_1
TCK, GCI_GPIO_1, or UART RX
TCK, GCI_GPIO_1, or UART RX
GPIO_3
TMS or GCI_GPIO_0
TMS or GCI_GPIO_0
TMS or GCI_GPIO_0
TMS or GCI_GPIO_0
GPIO_4
TDI or SECI_IN
TDI
TDI or SECI_IN
TDI or SECI_IN
GPIO_5
TDO or SECI_OUT
TDO
TDO or SECI_OUT
TDO or SECI_OUT
GPIO_6
TRST_L or UART TX
TRST_L
TRST_L or UART TX
TRST_L or UART TX
GPIO_7
[Strap, tied High]
[Strap, tied High]
[Strap, tied Low]
[Strap, tied High]
GPIO_8
[Strap, tied High or Low]
[Strap, tied High or Low]
–
[Strap, tied High or Low]
GPIO_9
N/A
–
N/A
N/A
GPIO_10
N/A
SECI_IN
N/A
N/A
GPIO_11
N/A
SECI_OUT
N/A
N/A
GPIO_12
N/A
UART_TX
N/A
N/A
GPIO_13
N/A
UART_RX
WL_LED
WL_LED
GPIO_14
N/A
–
–
–
GPIO_15
N/A
–
–
–
SDIO_CLK
SDIO_CLK
SDIO_CLK
[Strap, tied High]
SDIO_CLK
SDIO_CMD
SDIO_CMD
SDIO_CMD
SPROM_CS
SDIO_CMD
SDIO_DATA_0
SDIO_DATA_0
SDIO_DATA_0
SPROM_CLK
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_1
SDIO_DATA_1
SPROM_MISO
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_2
SDIO_DATA_2
[Strap, tied Low]
SDIO_DATA_2
SDIO_DATA_3
SDIO_DATA_3
SDIO_DATA_3
SPROM_MOSI
SDIO_DATA_3
1. N/A = Pin not available in this package.
2. JTAG signals (TCK, TDI, TDO, TMS, and TRST_L) are selected when JTAG_SEL pin is high.
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CYW4339
12.6 I/O States
The following notations are used in Table 27:
■
I: Input signal
■
O: Output signal
■
I/O: Input/Output signal
■
PU = Pulled up
■
PD = Pulled down
■
NoPull = Neither pulled up nor pulled down
Table 27. I/O States
Name
I/O
Keeper1
Active Mode
Low Power State/
Sleep (All Power
Present)
Power-down2
(BT_REG_ON and
WL_REG_ON Held
Low)
Out-of-Reset;
(WL_REG_ON High
Before SW Download and BT_REG_ON = 0)
(BT_REG_ON High;
and VDDIOs Are
WL_REG_ON High)
Present
Power Rail
WL_REG_ON
I
N
Input; PD (pull-down
can be disabled)
Input; PD (pull-down
can be disabled)
Input; PD (of 200K)
Input; PD (of 200K)
Input; PD (of 200K)
–
BT_REG_ON
I
N
Input; PD (pull down
can be disabled)
Input; PD (pull down
can be disabled)
Input; PD (of 200K)
Input; PD (of 200K)
Input; PD (of 200K)
–
CLK_REQ
I/O
Y
Open drain or pushpull (programmable).
Active high.
Open drain or pushpull (programmable).
Active high
PD
Open drain. Active high
Open drain. Active high.
BT_VDDIO
BT_HOST_WAK
E
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable)
Input/Output; PU, PD,
NoPull
(programmable)
High-Z, NoPull
Input, PU
Input, PD
BT_VDDIO
BT_DEV_WAKE
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable)
Input; PU, PD, NoPull
(programmable)
High-Z, NoPull
Input, PD
Input, PD
BT_VDDIO
BT_GPIO 2, 3, 4,
5
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable)
Input/Output; PU, PD,
NoPull
(programmable)
High-Z, NoPull
Input, PD
Input, PD
BT_VDDIO
BT_UART_CTS
I
Y
Input; NoPull
Input; NoPull
High-Z, NoPull
Input; PU
Input; PU
BT_VDDIO
BT_UART_RTS
O
Y
Output; NoPull
Output; NoPull
High-Z, NoPull
Input; PU
Input; PU
BT_VDDIO
BT_UART_RXD
I
Y
Input; PU
Input; NoPull
High-Z, NoPull
Input; PU
Input; PU
BT_VDDIO
BT_UART_TXD
O
Y
Output; NoPull
Output; NoPull
High-Z, NoPull
Input; PU
Input; PU
BT_VDDIO
SDIO Data
I/O
N
Input/Output;
PU (SDIO Mode)
Input; PU (SDIO
Mode)
High-Z, NoPull
Input; PU (SDIO Mode)
Input; PU (SDIO Mode)
VDDIO_SD
SDIO CMD
I/O
N
Input/Output;
PU (SDIO Mode)
Input; PU (SDIO
Mode)
High-Z, NoPull
Input; PU (SDIO Mode)
Input; PU (SDIO Mode)
VDDIO_SD
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CYW4339
Table 27. I/O States (Cont.)
Name
I/O
Keeper1
Active Mode
Low Power State/
Sleep (All Power
Present)
Power-down2
(BT_REG_ON and
WL_REG_ON Held
Low)
Out-of-Reset;
(WL_REG_ON High
Before SW Download and BT_REG_ON = 0)
(BT_REG_ON High;
and VDDIOs Are
WL_REG_ON High)
Present
Power Rail
SDIO_CLK
I
N
Input; NoPull
Input; noPull
High-Z, NoPull
Input; noPull
Input; noPull
VDDIO_SD
BT_PCM_CLK
I/O
Y
Input; NoPull3
Input; NoPull3
High-Z, NoPull
Output
Input, PD
BT_VDDIO
BT_PCM_IN
I/O
Y
Input; NoPull3
Input; NoPull3
High-Z, NoPull
Input; NoPull, Hi-Z
Input, PD
BT_VDDIO
BT_PCM_OUT
I/O
Y
3
Input; NoPull
3
Input; NoPull
High-Z, NoPull
Output
Input, PD
BT_VDDIO
BT_PCM_SYNC
I/O
Y
Input; NoPull 3
Input; NoPull3
High-Z, NoPull
Output
Input, PD
BT_VDDIO
BT_I2S_WS
I/O
Y
PD4
PD4
High-Z, NoPull
Input, PD
Input, PD
BT_VDDIO
BT_I2S_CLK
I/O
Y
4
4
High-Z, NoPull
Input, PD
Input, PD
BT_VDDIO
BT_I2S_DI
I/O
Y
PD
Input; PD
High-Z, NoPull
Input, PD
Input, PD
BT_VDDIO
BT_I2S_DO
I/O
Y
Output4
Output4
High-Z, NoPull
Input, PD
Input, PD
BT_VDDIO
WL GPIO_0
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])
High-Z, NoPull
Input; PD
Input; PD
VDDIO
WL GPIO_1
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
High-Z, NoPull
Input; NoPull
Input; NoPull
VDDIO
WL GPIO_2
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
High-Z, NoPull
Input; NoPull
Input; NoPull
VDDIO
WL GPIO_3
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])
High-Z, NoPull
Input; PD
Input; PD
VDDIO
WL GPIO_4
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
High-Z, NoPull
Input; NoPull
Input; NoPull
VDDIO
WL GPIO_5
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])
High-Z, NoPull
Input; PD
Input; PD
VDDIO
Document No. 002-14784 Rev. *I
PD
4
PD
4
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Table 27. I/O States (Cont.)
Name
I/O
Keeper1
Active Mode
Low Power State/
Sleep (All Power
Present)
Power-down2
(BT_REG_ON and
WL_REG_ON Held
Low)
Out-of-Reset;
(WL_REG_ON High
Before SW Download and BT_REG_ON = 0)
(BT_REG_ON High;
and VDDIOs Are
WL_REG_ON High)
Present
Power Rail
WL GPIO_6
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
High-Z, NoPull
Input; NoPull
Input; NoPull
VDDIO
WL GPIO_7
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
High-Z, NoPull
Input; NoPull
Input; NoPull
VDDIO
WL GPIO_8
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])5
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])5
High-Z, NoPull
Input; PD5
Input; PD5
VDDIO
WL GPIO_96
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])
High-Z, NoPull
Input; PD
Input; PD
VDDIO
WL GPIO_106
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
High-Z, NoPull
Input; NoPull
Input; NoPull
VDDIO
WL GPIO_116
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])
Input/Output; PU, PD,
NoPull
(programmable
[Default: PD])
High-Z, NoPull
Input; PD
Input; PD
VDDIO
WL GPIO_126
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
High-Z, NoPull
Input; NoPull
Input; NoPull
VDDIO
WL GPIO_137
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
High-Z, NoPull
Input; NoPull
Input; NoPull
VDDIO
WL GPIO_147
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
High-Z, NoPull
Input; NoPull
Input; NoPull
VDDIO
WL GPIO_157
I/O
Y
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
Input/Output; PU, PD,
NoPull
(programmable
[Default: NoPull])
High-Z, NoPull
Input; NoPull
Input; NoPull
VDDIO
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CYW4339
Table 27. I/O States (Cont.)
Name
RF_SW_CTRL_
X
I/O
O
Keeper1
N
Active Mode
Output, NoPull
Low Power State/
Sleep (All Power
Present)
Power-down2
(BT_REG_ON and
WL_REG_ON Held
Low)
Output, NoPull
High-Z, NoPull
Out-of-Reset;
(WL_REG_ON High
Before SW Download and BT_REG_ON = 0)
(BT_REG_ON High;
and VDDIOs Are
WL_REG_ON High)
Present
Output, NoPull
Output, NoPull
Power Rail
VDDIO_RF
1. Keeper column: N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in Power-down state. If there is no keeper, and it is an input and there is Nopull, then the
pad should be driven to prevent leakage due to floating pad (SDIO_CLK, for example).
2. In the Power-down state (xx_REG_ON=0): High-Z; NoPull => the pad is disabled because power is not supplied.
3. Depending on whether the PCM interface is enabled and the configuration of PCM is in master or slave mode, it can be either output or input.
4. Depending on whether the I2S interface is enabled and the configuration of I2S is in master or slave mode, it can be either output or input
5. NoPull when in SDIO mode.
6. Only available in WLCSP package.
7. Only available in WLCSP and FCBGA packages.
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13. DC Characteristics
13.1 Absolute Maximum Ratings
Caution! The absolute maximum ratings in Table 28 indicate levels where permanent damage to the device can occur, even if these
limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute
maximum conditions for extended periods can adversely affect long-term reliability of the device.
Table 28. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
DC supply for VBAT and PA driver supply1
VBAT
–0.5 to +6.0
V
DC supply voltage for digital I/O
VDDIO
–0.5 to 3.9
V
DC supply voltage for RF switch I/Os
VDDIO_RF
–0.5 to 3.9
V
DC input supply voltage for CLDO and LNLDO
–
–0.5 to 1.575
V
DC supply voltage for RF analog
VDD1P2
–0.5 to 1.32
V
DC supply voltage for core
VDDC
–0.5 to 1.32
V
–
–0.5 to 3.63
V
Maximum undershoot voltage for I/O
Vundershoot
–0.5
V
Maximum overshoot voltage for I/Ob
Vovershoot
VDDIO + 0.5
V
Maximum junction temperature
Tj
125
°C
WRF_TCXO_VDD
2
1. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V (for up to 10 seconds), cumulative duration over the lifetime of the
device, are allowed. Voltage transients as high as 5.5V (for up to 250 seconds), cumulative duration over the lifetime of the device, are allowed.
2. Duration not to exceed 25% of the duty cycle.
13.2 Environmental Ratings
The environmental ratings are shown in Table 29.
Table 29. Environmental Ratings
Characteristic
Value
Units
Conditions/Comments
Ambient Temperature (TA)
–30 to +85
°C
Functional operation1
Storage Temperature
–40 to +125
°C
–
Relative Humidity
Less than 60
%
Storage
Less than 85
%
Operation
1. Functionality is guaranteed but specifications require derating at extreme temperatures; see the specification tables for details.
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13.3 Electrostatic Discharge Specifications
Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps
to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.
Table 30. ESD Specifications
Symbol
Condition
ESD, Handling Reference:
NQY00083, Section 3.4,
Group D9, Table B
Pin Type
ESD_HAND_HBM
Human body model contact discharge per JEDEC
EID/JESD22-A114
±1000
ESD Rating
V
Unit
CDM
ESD_HAND_CDM
Charged device model contact discharge per
JEDEC EIA/JESD22-C101
±300
V
13.4 Recommended Operating Conditions and DC Characteristics
Caution! Functional operation is not guaranteed outside of the limits shown in Table 31 and operation outside these limits for
extended periods can adversely affect long-term reliability of the device.
Table 31. Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Value
Minimum
Typical
Maximum
Unit
DC supply voltage for VBAT
VBAT
3.01
–
5.252
V
DC supply voltage for core
VDD
1.14
1.2
1.26
V
DC supply voltage for RF blocks in chip
VDD1P2
1.14
1.2
1.26
V
DC supply voltage for TCXO input buffer
WRF_TCXO_VDD
1.62
1.8
1.98
V
DC supply voltage for digital I/O
VDDIO, VDDIO_SD
1.71
–
3.63
V
DC supply voltage for RF switch I/Os
VDDIO_RF
3.13
3.3
3.46
V
External TSSI input
WRF_TSSI_A,
WRF_TSSI_G
0.15
–
0.95
V
Internal POR threshold
Vth_POR
0.4
–
0.7
V
SDIO Interface I/O Pins
For VDDIO_SD = 1.8V:
Input high voltage
VIH
1.27
–
–
V
Input low voltage
VIL
–
–
0.58
V
Output high voltage @ 2 mA
VOH
1.40
–
–
V
Output low voltage @ 2 mA
VOL
–
–
0.45
V
Input high voltage
VIH
0.625 × VDDIO
–
–
V
Input low voltage
VIL
–
–
0.25 × VDDIO
V
Output high voltage @ 2 mA
VOH
0.75 × VDDIO
–
–
V
Output low voltage @ 2 mA
VOL
–
–
0.125 ×
VDDIO
V
For VDDIO_SD = 3.3V:
Other Digital I/O Pins
For VDDIO = 1.8V:
Input high voltage
VIH
0.65 × VDDIO
–
–
V
Input low voltage
VIL
–
–
0.35 × VDDIO
V
Output high voltage @ 2 mA
VOH
VDDIO – 0.45
–
–
V
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Table 31. Recommended Operating Conditions and DC Characteristics (Cont.)
Parameter
Output low voltage @ 2 mA
Symbol
Value
Minimum
Typical
Maximum
Unit
VOL
–
–
0.45
V
Input high voltage
VIH
2.00
–
–
V
Input low voltage
VIL
–
–
0.80
V
Output high voltage @ 2 mA
VOH
VDDIO – 0.4
–
–
V
Output low Voltage @ 2 mA
VOL
–
–
0.40
V
For VDDIO = 3.3V:
3
RF Switch Control Output Pins
For VDDIO_RF = 3.3V:
Output high voltage @ 2 mA
VOH
VDDIO – 0.4
–
–
V
Output low voltage @ 2 mA
VOL
–
–
0.40
V
Output capacitance
COUT
–
–
5
pF
1. The CYW4339 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only
for 3.13V < VBAT < 4.8V.
2. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V (for up to 10 seconds), cumulative duration over the lifetime of the
device are allowed. Voltage transients as high as 5.5V (for up to 250 seconds), cumulative duration over the lifetime of the device are allowed.
3. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.
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14. Bluetooth RF Specifications
Unless otherwise stated, limit values apply for the conditions specified in Table 29, “Environmental Ratings,” and Table 31, “Recommended Operating Conditions and DC Characteristics,”. Typical values apply for the following conditions:
■
VBAT = 3.6V
■
Ambient temperature +25°C
Figure 29. Port Locations for Bluetooth Testing
CYW4339
RF Switch
(0.5 dB typical insertion loss)
WLAN Tx
Filter
BT Tx
WLAN/BT Rx
Antenna
Port
RF Port
Chip
Port
Note: All Bluetooth specifications are measured at the chip port unless otherwise specified.
Table 32. Bluetooth Receiver RF Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Unit
Note: The specifications in this table are measured at the chip port output unless otherwise specified.
General
Frequency range
–
2402
–
2480
MHz
RX sensitivity
GFSK, 0.1% BER, 1 Mbps
–
–93.5
–
dBm
/4–DQPSK, 0.01% BER,
–
–95.5
–
dBm
2 Mbps
8–DPSK, 0.01% BER, 3 Mbps
–
–89.5
–
dBm
Input IP3
–
–16
–
–
dBm
Maximum input at antenna
–
–
–
–20
dBm
2.4 GHz band
–
–
–90.0
–80.0
dBm
RX LO Leakage
Interference
Performance1
C/I co-channel
GFSK, 0.1% BER
–
8
–
dB
C/I 1-MHz adjacent channel
GFSK, 0.1% BER
–
–7
–
dB
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Table 32. Bluetooth Receiver RF Specifications (Cont.)
Parameter
Conditions
Minimum
Typical
Maximum
Unit
C/I 2-MHz adjacent channel
GFSK, 0.1% BER
–
–38
–
dB
C/I 3-MHz adjacent channel
GFSK, 0.1% BER
–
–56
–
dB
C/I image channel
GFSK, 0.1% BER
–
–31
–
dB
C/I 1-MHz adjacent to image channel
GFSK, 0.1% BER
–
–46
–
dB
C/I co-channel
/4–DQPSK, 0.1% BER
–
9
–
dB
C/I 1-MHz adjacent channel
/4–DQPSK, 0.1% BER
–
–11
–
dB
–
–39
–
dB
–
–55
–
dB
–
–23
–
dB
–
–43
–
dB
C/I 1-MHz adjacent to image channel
/4–DQPSK, 0.1% BER
/4–DQPSK, 0.1% BER
/4–DQPSK, 0.1% BER
/4–DQPSK, 0.1% BER
C/I co-channel
8–DPSK, 0.1% BER
–
17
–
dB
C/I 1 MHz adjacent channel
8–DPSK, 0.1% BER
–
–4
–
dB
C/I 2-MHz adjacent channel
C/I 3-MHz adjacent channel
C/I image channel
C/I 2 MHz adjacent channel
8–DPSK, 0.1% BER
–
–37
–
dB
C/I 3-MHz adjacent channel
8–DPSK, 0.1% BER
–
–53
–
dB
C/I Image channel
8–DPSK, 0.1% BER
–
–16
–
dB
C/I 1-MHz adjacent to image channel
8–DPSK, 0.1% BER
–
–37
–
dB
30–2000 MHz
0.1% BER
–
–10.0
–
dBm
2000–2399 MHz
0.1% BER
–
–27
–
dBm
2498–3000 MHz
0.1% BER
–
–27
–
dBm
3000 MHz–12.75 GHz
0.1% BER
–
–10.0
–
dBm
Out-of-Band Blocking Performance (CW)
Out-of-Band Blocking Performance, Modulated Interferer
GFSK (1 Mbps)2
698–716 MHz
WCDMA
–
–13.5
–
dBm
776–849 MHz
WCDMA
–
–13.8
–
dBm
824–849 MHz
GSM850
–
–13.5
–
dBm
824–849 MHz
WCDMA
–
–14.3
–
dBm
880–915 MHz
E-GSM
–
–13.1
–
dBm
880–915 MHz
WCDMA
–
–13.1
–
dBm
1710–1785 MHz
GSM1800
–
–18.1
–
dBm
1710–1785 MHz
WCDMA
–
–17.4
–
dBm
1850–1910 MHz
GSM1900
–
–19.4
–
dBm
1850–1910 MHz
WCDMA
–
–18.8
–
dBm
1880–1920 MHz
TD-SCDMA
–
–19.7
–
dBm
1920–1980 MHz
WCDMA
–
–19.6
–
dBm
2010–2025 MHz
TD–SCDMA
–
–20.4
–
dBm
WCDMA
–
–20.4
–
dBm
2500–2570 MHz
5
Band 7
–
–30.5
–
dBm
2300-2400 MHz 6
Band 40
–
–34.0
–
dBm
3
Band 38
–
–30.8
–
dBm
2500–2570 MHz
2570–2620 MHz
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Table 32. Bluetooth Receiver RF Specifications (Cont.)
Parameter
2545–2575 MHz
4
Conditions
Minimum
XGP Band
–
π/4 DPSK (2 Mbps)
698–716 MHz
WCDMA
Typical
Maximum
Unit
–29.5
–
dBm
–9.8
–
dBm
2
–
776–794 MHz
WCDMA
–
–9.7
–
dBm
824–849 MHz
GSM850
–
–10.7
–
dBm
824–849 MHz
WCDMA
–
–11.4
–
dBm
880–915 MHz
E-GSM
–
–10.4
–
dBm
880–915 MHz
WCDMA
–
–10.2
–
dBm
1710–1785 MHz
GSM1800
–
–15.8
–
dBm
1710–1785 MHz
WCDMA
–
–15.4
–
dBm
1850–1910 MHz
GSM1900
–
–16.6
–
dBm
1850–1910 MHz
WCDMA
–
–16.4
–
dBm
1880–1920 MHz
TD-SCDMA
–
–17.9
–
dBm
1920–1980 MHz
WCDMA
–
–16.8
–
dBm
2010–2025 MHz
TD-SCDMA
–
–18.6
–
dBm
2500–2570 MHz
WCDMA
–
–20.4
–
dBm
2500–2570 MHz 5
Band 7
–
–31.9
–
dBm
2300–2400 MHz 6
Band 40
–
–35.3
–
dBm
2570-2620 MHz
3
Band 38
–
–31.8
–
dBm
2545-2575 MHz
4
XGP Band
–
–31.1
–
dBm
–
–12.6
–
dBm
8DPSK (3
Mbps)2
698–716 MHz
WCDMA
776–794 MHz
WCDMA
–
–12.6
–
dBm
824–849 MHz
GSM850
–
–12.7
–
dBm
824–849 MHz
WCDMA
–
–13.7
–
dBm
880–915 MHz
E-GSM
–
–12.8
–
dBm
880–915 MHz
WCDMA
–
–12.6
–
dBm
1710–1785 MHz
GSM1800
–
–18.1
–
dBm
1710–1785 MHz
WCDMA
–
–17.4
–
dBm
1850–1910 MHz
GSM1900
–
–19.1
–
dBm
1850–1910 MHz
WCDMA
–
–18.6
–
dBm
1880–1920 MHz
TD-SCDMA
–
–19.3
–
dBm
1920–1980 MHz
WCDMA
–
–18.9
–
dBm
2010–2025 MHz
TD-SCDMA
–
–20.4
–
dBm
2500–2570 MHz
WCDMA
–
–21.4
–
dBm
2500–2570 MHz 5
Band 7
–
–31.0
–
dBm
2300–2400 MHz 6
Band 40
–
–34.5
–
dBm
2570–2620 MHz
3
Band 38
–
–31.2
–
dBm
2545–2575 MHz
4
XGP Band
–
–30.0
–
dBm
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Table 32. Bluetooth Receiver RF Specifications (Cont.)
Parameter
Conditions
Minimum
Typical
Maximum
Unit
Spurious Emissions
30 MHz–1 GHz
–
–95
–62
dBm
1–12.75 GHz
–
–70
–47
dBm
851–894 MHz
–
–147
–
dBm/Hz
925–960 MHz
–
–147
–
dBm/Hz
1805–1880 MHz
–
–147
–
dBm/Hz
1930–1990 MHz
–
–147
–
dBm/Hz
2110–2170 MHz
–
–147
–
dBm/Hz
1. The maximum value represents the actual Bluetooth specification required for Bluetooth qualification as defined in the version 4.1
specification.
2. Bluetooth reference level is taken at the 3 dB RX desense on each of the modulation schemes.
3. Interferer: 2380 MHz, BW=10 MHz; measured at 2480 MHz.
4. Interferer: 2355 MHz, BW=10 MHz; measured at 2480 MHz.
5. Interferer: 2560 MHz, BW=10 MHz; measured at 2480 MHz.
6. Interferer: 2360 MHz, BW=10 MHz; measured at 2402 MHz.
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Table 33. Bluetooth Transmitter RF Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Unit
Note: The specifications in this table are measured at the chip port output unless otherwise specified.
General
Frequency range
2402
–
2480
MHz
Basic rate (GFSK) TX power at Bluetooth
11.0
13.0
–
dBm
QPSK TX Power at Bluetooth
8.0
10.0
–
dBm
8PSK TX Power at Bluetooth
8.0
10.0
–
dBm
Power control step
2
4
8
dB
0.93
1
MHz
Note: Output power is with TCA and TSSI enabled.
GFSK In-Band Spurious Emissions
–20 dBc BW
–
–
EDR In-Band Spurious Emissions
1.0 MHz < |M – N| < 1.5 MHz
|M – N| 2.5 MHz1
M – N = the frequency range for which
the spurious emission is measured
relative to the transmit center
frequency.
30 MHz to 1 GHz
–
1.5 MHz < |M – N| < 2.5 MHz
–
–38
–26.0
dBc
–
–31
–20.0
dBm
–
–43
–40.0
dBm
–
–36.0 2, 3
Out-of-Band Spurious Emissions
–
b, 4, 5
dBm
dBm
1 GHz to 12.75 GHz
–
–
–
–30.0
1.8 GHz to 1.9 GHz
–
–
–
–47.0
dBm
5.15 GHz to 5.3 GHz
–
–
–
–47.0
dBm
–
–103
–
dBm
GPS Band Spurious Emissions
Spurious emissions
–
Out-of-Band Noise
Floor6
65–108 MHz
FM RX
–
–147
–
dBm/Hz
776–794 MHz
CDMA2000
–
–147
–
dBm/Hz
869–960 MHz
cdmaOne, GSM850
–
–147
–
dBm/Hz
925–960 MHz
E-GSM
–
–147
–
dBm/Hz
1570–1580 MHz
GPS
–
–146
–
dBm/Hz
1805–1880 MHz
GSM1800
–
–145
–
dBm/Hz
1930–1990 MHz
GSM1900, cdmaOne, WCDMA
–
–144
–
dBm/Hz
2110–2170 MHz
WCDMA
–
–141
–
dBm/Hz
2500–2570 MHz
Band 7
–
–140
–
dBm/Hz
2300–2400 MHz
Band 40
–
–140
–
dBm/Hz
2570–2620 MHz
Band 38
–
–140
–
dBm/Hz
2545–2575 MHz
XGP Band
–
–140
–
dBm/Hz
1. The typical number is measured at ±3 MHz offset.
2. The maximum value represents the value required for Bluetooth qualification as defined in the v4.1 specification.
3. The spurious emissions during Idle mode are the same as specified in Table 33.
4. Specified at the Bluetooth Antenna port.
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5. Meets this specification using a front-end band-pass filter.
6. Transmitted power in cellular and FM bands at the Bluetooth Antenna port. See Figure 29 for location of the port.
Table 34. Local Oscillator Performance
Parameter
Minimum
Typical
Maximum
Unit
LO Performance
Lock time
Initial carrier frequency tolerance
–
72
–
s
–
±25
±75
kHz
Frequency Drift
DH1 packet
–
±8
±25
kHz
DH3 packet
–
±8
±40
kHz
DH5 packet
–
±8
±40
kHz
Drift rate
–
5
20
kHz/50 μs
Frequency Deviation
00001111 sequence in payload1
140
155
175
kHz
2
115
140
–
kHz
–
1
–
MHz
10101010 sequence in payload
Channel spacing
1. This pattern represents an average deviation in payload.
2. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations.
Table 35. BLE RF Specifications
Parameter
Frequency range
RX sense
1
TX power2
Mod Char: delta F1 average
Mod Char: delta F2
max3
Mod Char: ratio
Conditions
Minimum
–
2402
GFSK, 0.1% BER, 1 Mbps
–
–
–
–
Typical
Maximum
Unit
2480
MHz
–95.5
–
dBm
8.5
–
dBm
225
255
275
kHz
–
99.9
–
–
%
–
0.8
0.95
–
%
1. Dirty TX is On.
2. BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc.). The output is capped at 12 dBm out.
The BLE TX power at the antenna port cannot exceed the 10 dBm specification limit.
3. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz
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15. WLAN RF Specifications
15.1 Introduction
The CYW4339 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the 5 GHz bands. This section
describes the RF characteristics of the 2.4 GHz and 5 GHz radio.
Unless otherwise stated, limit values apply for the conditions specified inTable 29, “Environmental Ratings,” and Table 31, “Recommended Operating Conditions and DC Characteristics,”. Typical values apply for the following conditions:
■
VBAT = 3.6V
■
Ambient temperature +25°C
Figure 30. Port Locations Showing Optional ePA and eLNA (Applies to 2.4 GHz and 5 GHz)
CYW4339
RF Switch
(0.5 dB typical insertion loss)
WLAN Tx
Filter
BT Tx
WLAN/BT Rx
Antenna
Port
RF Port
Chip
Port
15.2 All WLAN specifications are specified at the RF port, unless otherwise specified.2.4 GHz Band General RF Specifications
Table 36. 2.4 GHz Band General RF Specifications
Item
Condition
Minimum
Typical
Maximum
Unit
TX/RX switch time
Including TX ramp down
–
–
5
μs
RX/TX switch time
Including TX ramp up
–
–
2
μs
Power-up and power-down ramp time
DSSS/CCK modulations
–
–
100 mA VBAT = 3.6V
2.8
4
5.2
MHz
PWM output current
–
–
–
600
mA
Output current limit
–
–
1400
Output voltage range
Programmable, 30 mV steps Default = 1.35V
1.2
1.35
1.5
V
PWM output voltage
DC accuracy
Includes load and line regulation.
–4
–
4
%
PWM ripple voltage, static
Measure with 20 MHz bandwidth limit.
–
7
20
mVp
p
mA
Forced PWM mode
Static Load. Max. Ripple based on VBAT = 3.6V,
Vout = 1.35V, Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH,
Cap + Board total-ESR < 20 mΩ, Cout > 1.9 μF, ESL 1.35V, Co= 2.2 µF, Vo = 1.2V
20
–
–
dB
LDO turn-on time
LDO turn-on time when rest of chip is up
–
140
180
µs
External output capacitor, Co
Total ESR (trace/capacitor): 5 mΩ–240 mΩ
0.51
2.2
4.7
µF
External input capacitor
Only use an external input capacitor at the VDD_LDO pin if it is
not supplied from CBUCK output.
Total ESR (trace/capacitor): 30 mΩ–200 mΩ
–
1
2.2
µF
1. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
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CYW4339
17. System Power Consumption
Note: Unless otherwise stated, these values apply for the conditions specified in Table 31, “Recommended Operating Conditions and
DC Characteristics,”.
17.1 WLAN Current Consumption
Table 47 shows the typical, total current consumed by the CYW4339. To calculate total-solution current consumption for designs using
external PAs, LNAs, and/or FEMs, add the current consumption of the external devices to the numbers in Table 47.
All values in Table 47 are with the Bluetooth core in reset (that is, with Bluetooth off).
Table 47. Typical WLAN Current Consumption (CYW4339 Current Only)
Mode
VBAT = 3.6V, VDDIO = 1.8V, TA 25°C
Band
(GHz)
Bandwidth (MHz)
Vio1, μA
Vbat, mA
Sleep Modes
OFF2
–
–
0.005
5
SLEEP3
–
–
0.005
150
IEEE Power Save, DTIM 1
4
–
2.4
0.850
150
IEEE Power Save, DTIM 3
4
–
2.4
0.350
150
IEEE Power Save, DTIM 1
4
–
5
0.550
150
IEEE Power Save, DTIM 34
–
5
0.300
150
Active Modes
Receive5,6
20
2.4
50
5
CRS7
20
2.4
46
5
Receive5,6 MCS7 (SGI)
20
5
66
5
20
5
56
5
CRS
MCS8 (SGI)
7
5,6
40
5
79.5
5
CRS7
40
5
67
5
Receive5,6 MCS9 (SGI)
80
5
110
5
80
5
103
5
Receive
CRS
MCS7 (SGI)
7
Active Modes with Internal PAs (TX Output Power Measured at the Chip Port)
TX CCK 11 Mbps at 21.7 dBm
20
2.4
325
5
TX OFDM MCS8 (SGI) at 17.2 dBm
20
2.4
240
5
TX OFDM MCS7 (SGI) at 18.5 dBm
20
5
280
5
TX OFDM MCS7 at 18.7 dBm
40
5
340
5
TX OFDM MCS9 (SGI) at 16.2 dBm
40
5
270
5
TX OFDM MCS9 (SGI) at 15.7 dBm
80
5
270
5
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Table 47. Typical WLAN Current Consumption (CYW4339 Current Only) (Cont.)
Mode
VBAT = 3.6V, VDDIO = 1.8V, TA 25°C
Band
(GHz)
Bandwidth (MHz)
Vio1, μA
Vbat, mA
Active Modes with External PAs (TX Output Power is –5 dBm at the Chip Port)
Transmit, CCK
20
2.4
88
5
Transmit, MCS8, HT20, SGI5, 8
20
2.4
76
5
20
5
111
5
Transmit, MCS7, SGI
5, 8
5, 8
40
5
125
5
5, 8
40
5
125
5
Transmit, MCS9, SGI5, 8
80
5
147
5
Transmit, MCS7
Transmit, MCS9, SGI
1. VIO is specified with all pins idle (not switching) and not driving any loads.
2. WL_REG_ON, BT_REG_ON low.
3. Idle, not associated, or inter-beacon.
4. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @1 Mbps. Average current over the specified DTIM intervals.
5. Measured using packet engine test mode.
6. Duty cycle is 100%. Carrier sense (CS) detect/packet receive.
7. Carrier sense (CCA) when no carrier present.
8. Duty cycle is 100%. Excludes external PA contribution.
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CYW4339
17.2 Bluetooth Current Consumption
The Bluetooth, and Bluetooth BLE current consumption measurements are shown in Table 48.
Note:
■
The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 48.
■
The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.
Table 48. Bluetooth BLE Current Consumption
Operating Mode
VBAT (VBAT = 3.6V) Typical
VDDIO (VDDIO = 1.8V) Typical
Units
Sleep
10
225
μA
Standard 1.28s Inquiry Scan
180
235
μA
P and I Scan2
320
235
μA
500 ms Sniff Master
170
250
μA
500 ms Sniff Slave
120
250
μA
DM1/DH1 Master
22.81
0.034
mA
DM3/DH3 Master
28.06
0.044
mA
DM5/DH5 Master
29.01
0.047
mA
3DH5 Master
27.09
0.100
mA
SCO HV3 Master
7.9
0.123
mA
HV3 + Sniff + Scan1
11.38
0.180
mA
175
235
μA
BLE Scan 10 ms
14.09
0.022
mA
BLE Adv – Unconnectable 1.00 sec
69
245
μA
BLE Adv – Unconnectable 1.28 sec
67
235
μA
BLE Adv – Unconnectable 2.00 sec
42
240
μA
BLE Connected 7.5 ms
4.30
0.020
mA
BLE Connected 1 sec
53
240
μA
BLE Connected 1.28 sec
48
240
μA
BLE Scan
2
1. At maximum class 1 TX power, 500 ms sniff, four attempts (slave), P = 1.28s, and I = 2.56s.
2. No devices present. A 1.28 second interval with a scan window of 11.25 ms.
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CYW4339
18. Interface Timing and AC Characteristics
18.1 SDIO Timing
18.1.1 SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 31 and Table 49.
Figure 31. SDIO Bus Timing (Default Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tISU
tIH
Input
Output
tODLY
tODLY
(max)
(min)
Table 49. SDIO Bus Timing1 Parameters (Default Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
2
SDIO CLK (All values are referred to minimum VIH and maximum VIL )
Frequency – Data Transfer mode
fPP
0
–
25
MHz
Frequency – Identification mode
fOD
0
–
400
kHz
Clock low time
tWL
10
–
–
ns
Clock high time
tWH
10
–
–
ns
Clock rise time
tTLH
–
–
10
ns
Clock fall time
tTHL
–
–
10
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
tISU
5
–
–
ns
Input hold time
tIH
5
–
–
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
tODLY
0
–
14
ns
Output delay time – Identification mode
tODLY
0
–
50
ns
1. Timing is based on CL 40pF load on CMD and Data.
2. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.
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CYW4339
18.1.2 SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 32 and Table 50.
Figure 32. SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Table 50. SDIO Bus Timing1 Parameters (High-Speed Mode)
Parameter
Symbol
Minimum
Typical
SDIO CLK (all values are referred to minimum VIH and maximum
Maximum
Unit
VIL2)
Frequency – Data Transfer Mode
fPP
0
–
50
MHz
Frequency – Identification Mode
fOD
0
–
400
kHz
Clock low time
tWL
7
–
–
ns
Clock high time
tWH
7
–
–
ns
Clock rise time
tTLH
–
–
3
ns
Clock fall time
tTHL
–
–
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
tISU
6
–
–
ns
Input hold time
tIH
2
–
–
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
tODLY
–
–
14
ns
Output hold time
tOH
2.5
–
–
ns
Total system capacitance (each line)
CL
–
–
40
pF
1. Timing is based on CL 40pF load on CMD and Data.
2. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.
18.1.3 SDIO Bus Timing Specifications in SDR Modes
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CYW4339
Clock Timing
Figure 33. SDIO Clock Timing (SDR Modes)
tCLK
SDIO_CLK
tCR
tCF
tCR
Table 51. SDIO Bus Clock Timing Parameters (SDR Modes)
Parameter
–
Symbol
tCLK
Minimum
Maximum
Unit
Comments
40
–
ns
SDR12 mode
20
–
ns
SDR25 mode
10
–
ns
SDR50 mode
4.8
–
ns
SDR104 mode
–
tCR, tCF
–
0.2 × tCLK
ns
tCR, tCF < 2.00 ns (max.) @100 MHz, CCARD = 10 pF
Clock duty cycle
–
30
70
%
–
tCR, tCF < 0.96 ns (max.) @208 MHz, CCARD = 10 pF
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CYW4339
Device Input Timing
Figure 34. SDIO Bus Input Timing (SDR Modes)
SDIO_CLK
tIS
tIH
CMD input
DAT[3:0] input
Table 52. SDIO Bus Input Timing Parameters (SDR Modes)
Symbol
Minimum
Maximum
Unit
Comments
SDR104 Mode
tIS
1.4
–
ns
tIH
0.8
–
ns
CCARD = 10 pF, VCT = 0.975V
CCARD = 5 pF, VCT = 0.975V
SDR50 Mode
tIS
3.0
–
ns
tIH
0.8
–
ns
CCARD = 10 pF, VCT = 0.975V
CCARD = 5 pF, VCT = 0.975V
SDR25 Mode
tIS
3.0
–
ns
tIH
0.8
–
ns
CCARD = 10 pF, VCT = 0.975V
CCARD = 5 pF, VCT = 0.975V
SDR12 Mode
tIS
3.0
–
ns
CCARD = 10 pF, VCT = 0.975V
tIH
0.8
–
ns
CCARD = 5 pF, VCT = 0.975V
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CYW4339
Device Output Timing
Figure 35. SDIO Bus Output Timing (SDR Modes up to 100 MHz)
tCLK
SDIO_CLK
tODLY
tOH
CMD output
DAT[3:0] output
Table 53. SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz)
Symbol
Minimum
Maximum
Unit
Comments
tODLY
–
7.5
ns
tCLK ≥ 10 ns CL= 30 pF using driver type B for SDR50
tODLY
–
14.0
ns
tCLK ≥ 20 ns CL= 40 pF using for SDR12, SDR25
tOH
1.5
–
ns
Hold time at the tODLY (min) CL= 15 pF
Figure 36. SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)
tCLK
SDIO_CLK
tOP
tODW
CMD output
DAT[3:0] output
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CYW4339
Table 54. SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz)
Symbol
Minimum
Maximum
Unit
Comments
tOP
0
2
UI
Card output phase
ΔtOP
–350
+1550
ps
Delay variation due to temp change after tuning
tODW
0.60
–
UI
tODW=2.88 ns @208 MHz
■
ΔtOP = +1550 ps for junction temperature of ΔtOP = 90 degrees during operation
■
ΔtOP = –350 ps for junction temperature of ΔtOP = –20 degrees during operation
■
ΔtOP = +2600 ps for junction temperature of ΔtOP = –20 to +125 degrees during operation
Figure 37. ΔtOP Consideration for Variable Data Window (SDR 104 Mode)
Data valid window
Sampling point after tuning
ȴtOP =
1550 ps
ȴtOP =
–350 ps
Data valid window
Sampling point after card junction heating
by +90°C from tuning temperature
Data valid window
Sampling point after card junction cooling
by –20°C from tuning temperature
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CYW4339
18.1.4 SDIO Bus Timing Specifications in DDR50 Mode
Figure 38. SDIO Clock Timing (DDR50 Mode)
tCLK
SDIO_CLK
tCR
tCF
tCR
Table 55. SDIO Bus Clock Timing Parameters (DDR50 Mode)
Parameter
Symbol
Minimum
Maximum
Unit
Comments
–
tCLK
20
–
ns
DDR50 mode
–
tCR,tCF
–
0.2 × tCLK
ns
tCR, tCF < 4.00 ns (max) @50 MHz, CCARD = 10 pF
Clock duty cycle
–
45
55
%
–
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CYW4339
Data Timing, DDR50 Mode
Figure 39. SDIO Data Timing (DDR50 Mode)
FPP
SDIO_CLK
tISU2x
DAT[3:0]
input
Invalid
tIH2x
tISU2x
Data
Invalid
tIH2x
Data
Invalid
tODLY2x (max)
DAT[3:0]
output
Data
Invalid
tODLY2x (max)
tODLY2x
tODLY2x
(min)
(min)
Data
Available timing
window for card
output transition
Data
In DDR50 mode, DAT[3:0] lines are sampled on both edges of
the clock (not applicable for CMD line)
Data
Available timing
window for host to
sample data from card
Table 56. SDIO Bus Timing Parameters (DDR50 Mode)
Parameter
Symbol
Minimum
Maximum
Unit
Comments
Input CMD
Input setup time
tISU
6
–
ns
CCARD < 10pF (1 Card)
Input hold time
tIH
0.8
–
ns
CCARD < 10pF (1 Card)
Output delay time
tODLY
–
13.7
ns
CCARD < 30pF (1 Card)
Output hold time
tOH
1.5
–
ns
CCARD < 15pF (1 Card)
Input setup time
tISU2x
3
–
ns
CCARD < 10pF (1 Card)
Input hold time
tIH2x
0.8
–
ns
CCARD < 10pF (1 Card)
Output delay time
tODLY2x
–
7.0
ns
CCARD < 25pF (1 Card)
Output hold time
tODLY2x
1.5
–
ns
CCARD < 15pF (1 Card)
Output CMD
Input DAT
Output DAT
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CYW4339
18.2 PCI Express Interface Parameters
Table 57. PCI Express Interface Parameters
Parameter
Symbol
Comments
Minimum
Typical
Maximum
Unit
General
Baud rate
BPS
–
–
5
–
Gbaud
Reference clock amplitude
Vref
LVPECL, AC coupled
1
–
–
V
Receiver
Differential termination
ZRX-DIFF-DC
Differential termination
80
100
120
Ω
DC impedance
ZRX-DC
DC common-mode
impedance
40
50
60
Ω
Powered down termination
(POS)
ZRX-HIGH-IMP-DCPOS
Power-down or RESET high
impedance
100k
–
–
Ω
Powered down termination
(NEG)
ZRX-HIGH-IMP-DCNEG
Power-down or RESET high
impedance
1k
–
–
Ω
Input voltage
VRX-DIFFp-p
AC coupled, differential
p-p
175
–
–
mV
Jitter tolerance
TRX-EYE
Minimum receiver eye width
0.4
–
–
UI
Differential return loss
RLRX-DIFF
Differential return loss
10
–
–
dB
Common-mode return loss
RLRX-CM
Common-mode return loss
6
–
–
dB
Unexpected electrical idle
enter detect threshold
integration time
TRX-IDEL-DET-DIFFENTERTIME
An unexpected electrical
idle must be recognized no
longer than this time to
signal an unexpected idle
condition.
–
–
10
ms
Signal detect threshold
VRX-IDLE-DET-DIFFpp
Electrical idle detect
threshold
65
–
175
mV
Transmitter
Output voltage
VTX-DIFFp-p
Differential p-p, programmable in 16 steps
0.8
–
1200
mV
Output voltage rise time
VTX-RISE
20% to 80%
0.125
(2.5 GT/s)
–
–
UI
–
–
UI
0.15
(5 GT/s)
Output voltage fall time
VTX-FALL
80% to 20%
0.125
(2.5 GT/s)
0.15
(5 GT/s)
RX detection voltage swing
VTX-RCV-DETECT
The amount of voltage
change allowed during
receiver detection.
–
–
600
mV
TX AC peak common-mode
voltage
(5 GT/s)
VTX-CM-AC-PP
TX AC common mode
voltage (5 GT/s)
–
–
100
mV
TX AC peak common-mode
voltage
(2.5 GT/s)
VTX-CM-AC-P
TX AC common mode
voltage (2.5 GT/s)
–
–
20
mV
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CYW4339
Table 57. PCI Express Interface Parameters (Cont.)
Parameter
Symbol
Comments
Minimum
Typical
Maximum
Unit
Absolute delta of DC
common-model voltage
during L0 and electrical idle
VTX-CM-DC-ACTIVEIDLE-DELTA
Absolute delta of DC
common-model voltage
during L0 and electrical idle.
0
–
100
mV
Absolute delta of DC
common-model voltage
between D+ and D–
VTX-CM-DC-LINEDELTA
DC offset between D+ and
D–
0
–
25
mV
Electrical idle differential
peak output voltage
VTX-IDLE-DIFF-AC-p
Peak-to-peak voltage
0
–
20
mV
TX short circuit
current
ITX-SHORT
Current limit when TX output
is shorted to ground.
–
–
90
mA
DC differential TX termination
ZTX-DIFF-DC
Low impedance defined
during signaling (parameter
is captured for 5.0 GHz by
RLTX-DIFF)
80
–
120
Ω
Differential
return loss
RLTX-DIFF
Differential
return loss
10 (min) for
0.05:
1.25 GHz
–
–
dB
8 (min) for
1.25:
2.5 GHz
Common-mode
return loss
RLTX-CM
Common-mode return loss
6
–
–
dB
TX eye width
TTX-EYE
Minimum TX
eye width
0.75
–
–
UI
18.3 JTAG Timing
Table 58. JTAG Timing Characteristics
Signal Name
TCK
Output
Maximum
Period
125 ns
–
Output
Minimum
–
Setup
Hold
–
–
TDI
–
–
–
20 ns
0 ns
TMS
–
–
–
20 ns
0 ns
TDO
–
100 ns
0 ns
–
–
JTAG_TRST
250 ns
–
–
–
–
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CYW4339
19. Power-Up Sequence and Timing
19.1 Sequencing of Reset and Regulator Control Signals
The CYW4339 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and
internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the
signals for various operational states (see Figure 40, Figure 41, and Figure 42 and Figure 43). The timing values indicated are
minimum required values; longer delays are also acceptable.
19.1.1 Description of Control Signals
■
WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the
internal CYW4339 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this
pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled.
■
BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal CYW4339 regulators. If both the
BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT
section is in reset.
Note:
■
2w2For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles
(where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed,
then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start.
■
The CYW4339 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC
and VDDIO have both passed the POR threshold. Wait at least 150 ms after VDDC and VDDIO are available before initiating
SDIO accesses.
VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the same time as VDDIO. VDDIO
should NOT be present first or be held high before VBAT is high.
19.1.2 Control Signal Timing Diagrams
Figure 40. WLAN = ON, Bluetooth = ON
32.678 kHz
Sleep Clock
VBAT*
90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high
before VBAT is high.
Figure 41. WLAN = OFF, Bluetooth = OFF
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CYW4339
32.678 kHz
Sleep Clock
VBAT*
VDDIO
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
Figure 42. WLAN = ON, Bluetooth = OFF
32.678 kHz
Sleep Clock
VBAT*
90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
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CYW4339
Figure 43. WLAN = OFF, Bluetooth = ON
32.678 kHz
Sleep Clock
VBAT*
90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first or be held high before VBAT is high .
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CYW4339
20. Package Information
20.1 Package Thermal Characteristics
Table 59. Package Thermal Characteristics1
Characteristic
JA (°C/W) (value in still air)
JB (°C/W)
JC (°C/W)
FCFBGA
WLBGA
WLCSP
48.03
32.9
33.45
17.01
2.56
3.45
24.52
0.98
1.00
JT (°C/W)
10.78
3.30
3.45
JB (°C/W)
18.02
9.85
10.64
Maximum Junction Temperature Tj (°C)
125
125
125
Maximum Power Dissipation (W)
1.41
1.119
1.119
1. No heat sink, TA = 70°C. This is an estimate, based on a 4-layer PCB that conforms to EIA/JESD51–7 (101.6 mm × 101.6 mm × 1.6 mm) and
P = specified power maximum continuous power dissipation.
20.2 Junction Temperature Estimation and PSIJT Versus THETAJC
Package thermal characterization parameter PSI–JT (JT) yields a better estimation of actual junction temperature (TJ) versus using
the junction-to-case thermal resistance parameter Theta–JC (JC). The reason for this is that JC assumes that all the power is
dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom
and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation
for calculating the device junction temperature is:
TJ = TT + P x JT
Where:
■
TJ = Junction temperature at steady-state condition (°C)
■
TT = Package case top center temperature at steady-state condition (°C)
■
P = Device power dissipation (Watts)
■
JT = Package thermal characteristics; no airflow (°C/W)
20.3 Environmental Characteristics
For environmental characteristics data, see Table 29, “Environmental Ratings,”.
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21. Mechanical Information
Figure 44. 160-Ball FCFBGA Package Mechanical Information
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Figure 45. 145-Ball WLBGA Package Mechanical Information
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Figure 46. WLBGA Keep-out Areas for PCB Layout—Bottom View with Balls Facing Up
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Figure 47. 286-Bump WLCSP Package Mechanical Information
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Figure 48. WLCSP Keep-out Areas for PCB Layout—Bottom View with Bumps Facing Up
Note: No top-layer metal is allowed in keep-out areas.
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22. Ordering Information
Part Number
Package
Description
Operating Ambient
Temperature
CYW4339NKFFBG
160-ball FCFBGA (8 mm × 8 mm,
0.4 mm pitch)
Dual-band 2.4 GHz and 5 GHz WLAN + BT 4.1
–30°C to +85°C
CYW4339XKWBG
286-bump WLCSP (4.87 mm × 5.413
mm, 0.2 mm pitch)
Dual-band 2.4 GHz and 5 GHz WLAN + BT 4.1
–30°C to +85°C
CYW4339XKUBG
145-ball WLBGA
(4.87 mm × 5.413 mm, 0.4 mm pitch)
Dual-band 2.4 GHz and 5 GHz WLAN + BT 4.1
–30°C to +85°C
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23. IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iottto help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website (https://
community.cypress.com/)
23.1 References
The references in this section may be used in conjunction with this document.
Note: Cypress provides customer access to technical documentation and software through its
https://community.cypress.com and Downloads & Support site (see IoT Resources).
Document (or Item) Name
[1]
Bluetooth MWS Coexistence 2-wire Transport Interface Specification
Document No. 002-14784 Rev. *I
Number
–
Source
wiced-smart
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Document History Page
Document Title: CYW4339 Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1
Document Number: 002-14784
Revision
ECN
Submission Date
Description of Change
**
-
02/15/2013
4339-DS100-R
Initial release.
*A
-
03/12/2013
4339-DS101-R
Updated:
• Package option dimensions.
• Table 19: “286-Bump WLCSP Coordinates,” on page 109 by replacing the
PACKAGEOPTION_0 through PACKAGEOPTION_3 signal names with VSSC.
• The Power Rail column in Table 31: “I/O States”
• Table 32: “Absolute Maximum Ratings”.
• Table 35: “Recommended Operating Conditions and DC Characteristics”
• Table 43: “WLAN 2.4 GHz Transmitter Performance Specifications”
• Table 45: “WLAN 5 GHz Transmitter Performance Specifications”.
• “WLAN Current Consumption”
• Table 53: “Bluetooth BLE and FM Current Consumption” Figure 77: “145-Ball
WLBGA Package Mechanical Information”
• Section 24: “Ordering Information”
*B
-
07/02/2013
4339-DS102-R
Updated:
• Figure 1: “Functional Block Diagram”
• Figure 2: “BCM4339 Block Diagram”
• Figure 5: “Typical Power Topology for BCM4339”
• Table 20: “FCFBGA, WLBGA, and WLCSP Signal Descriptions”
• Table 35: “Recommended Operating Conditions and DC Characteristics,” by
changing DC supply voltage for VBAT from 4.8V to 5.25V.
• Table 47: “Core Buck Switching Regulator (CBUCK) Specifications,” by changing
input supply voltage (DC) Max from 4.8V to 5.25V.
• Table 48: “LDO3P3 Specifications,” by changing input supply voltage, VIN Max
from 4.8V to 5.25V.
• Table 49: “BTLDO2P5 Specifications,” by changing input supply voltage Max from
4.8V to 5.25V.
• Table 52: “Typical WLAN Power Consumption (External PA configuration)”
• Table 53: “Bluetooth BLE and FM Current Consumption” Section 24: “Ordering
Information”
*C
-
11/08/2013
4339-DS103-R
Updated:
• BT_VDDO to BT_VDDIO throughout the document.
• Table 34: “ESD Specifications”.
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Document Title: CYW4339 Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1
Document Number: 002-14784
Revision
*D
ECN
-
Submission Date
04/02/2014
Description of Change
4339-DS104-R
Updated:
• The cover page and the general features .
• By deleting the HSIC interface throughout, leaving pin and signal names
unchanged.
• By changing to PCI Express Base Specification (revision 3.0 compliant Gen1
interface) throughout.
• “External Frequency Reference” .
• Table 2: “Crystal Oscillator and External Clock — Requirements and Performance”
• “Frequency Selection”
• Figure 10: “Startup Signaling Sequence”
• Figure 22: “UART Timing”
• “One-Time Programmable Memory”.
• Figure 50: “160-Ball FCFBGA (Top View),” by changing BT_VDDO to BT_VDDIO.
• Figure 54: “286-Bump WLCSP (Bottom View)”.
• Table 19: “286-Bump WLCSP Coordinates” by changing BT_VDDO to BT_VDDIO.
• Table 20: “FCFBGA, WLBGA, and WLCSP Signal Descriptions” by changing
BT_VDDO to BT_VDDIO and adding a note to the GPIO pin description.
• Table 31: “I/O States”
• Table 34: “ESD Specifications”
• Table 35: “Recommended Operating Conditions and DC Characteristics,” by
changing CIN to COUT.
• Table 36: “Bluetooth Receiver RF Specifications,” by deleting what was footnote e,
altering footnote b, and adding footnote b to one additional place.
• “Introduction”.
• RSSI accuracy in Table 42: “WLAN 2.4 GHz Receiver Performance Specifications”
and Table 44: “WLAN 5 GHz Receiver Performance Specifications”
• Table 43: “WLAN 2.4 GHz Transmitter Performance Specifications,” and the note
preceding it.
• Table 45: “WLAN 5 GHz Transmitter Performance Specifications” and the note
preceding it.
• Section 18: “Internal Regulator Electrical Specifications” “WLAN Current
Consumption”.
• Figure 65: “SDIO Bus Output Timing (SDR Modes up to 100 MHz)”.
• Figure 66: “SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)”.
*E
-
05/28/2014
4339-DS105-R
Updated:
• The Features listed in the front matter of the document.
• By changing all instances of Bluetooth 4.0 to Bluetooth 4.1 throughout the
document.
• By removing the word draft after all instances of IEEE 802.11ac throughout the
document.
• “Features”.
• “External 32.768 kHz Low-Power Oscillator”.
• “Advanced Bluetooth/WLAN Coexistence”.
• “SDIO v3.0”.
• Table 20: “FCFBGA, WLBGA, and WLCSP Signal Descriptions” by fixing an
incorrect WLBGA ball. The second instance of M12 was changed to M10.
• Table 21: “WLAN GPIO Functions and Strapping Options” .
• Table 24: “Host Interface Selection (WLBGA and WLCSP Packages)”
*F
-
11/17/2014
4339-DS106-R
Updated:
• Table 55: “SDIO Bus Input Timing Parameters (SDR Modes)” .
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Document Title: CYW4339 Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1
Document Number: 002-14784
Revision
ECN
Submission Date
*G
5450674
10/04/2016
*H
5674872
03/29/2017
*I
7109428
03/24/2021
Description of Change
Added Cypress Part Numbering Scheme and Mapping Table on Page 1.
Updated to Cypress template.
Removed Sections belong to FM and gSPI throughout the document.
Removed Cypress Part Numbering Scheme.
Updated .Features and 10.2.IEEE 802.11ac PHY.
Updated Table 37 and Table 39.
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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cypress.com/iot
cypress.com/memory
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cypress.com/mcu
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cypress.com/psoc
Power Management ICs
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
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Community | Code Examples | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
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cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2013-2021. This document is the property of Cypress Semiconductor Corporation, and Infineon Technologies company, and its affiliates (“Cypress”). This
document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and
other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the
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externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction,
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively,
“Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security
Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the
extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of
any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes.
It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk
Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and
other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the HighRisk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any
use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, including its affiliates, and its directors, officers, employees, agents, distributors, and
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Cypress, the Cypress logo, and combinations thereof, WICED, ModusToolBox, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress or a subsidiary
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Document No. 002-14784 Rev. *I
Revised March 24, 2021
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