BCM43438KUBGT

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CYW43438 PRELIMINARY Single-Chip IEEE 802.11 b/g/n MAC/Baseband/ Radio with Integrated Bluetooth 5.1 Compliance The Cypress CYW43438 is a highly integrated single-chip solution and offers the lowest RBOM in the industry for smartphones, tablets, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio, and Bluetooth 5.1 compliance. In addition, it integrates a power amplifier (PA) that meets the output power requirements of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal transmit/receive (iTR) RF switch, further reducing the overall solution cost and printed circuit board area. The WLAN host interface supports gSPI and SDIO v2.0 modes, providing a raw data transfer rate up to 200 Mbps when operating in 4-bit mode at a 50 MHz bus frequency. An independent, high-speed UART is provided for the Bluetooth host interface. Using advanced design techniques and process technology to reduce active and idle power, the CYW43438 is designed to address the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit that simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery while maximizing battery life. The CYW43438 implements the world’s most advanced Enhanced Collaborative Coexistence algorithms and hardware mechanisms, allowing for an extremely collaborative WLAN and Bluetooth coexistence. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table 1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number BCM43438 CYW43438 BCM43438KUBG CYW43438KUBG Features IEEE 802.11x Key Features ■ Bluetooth Key Features Single-band 2.4 GHz IEEE 802.11b/g/n. ■ Qualified for Bluetooth Core Specification 5.1 compliance ■ Support for 2.4 GHz Broadcom QAM) and 20 MHz channel bandwidth. ■ Integrated iTR switch supports a single 2.4 GHz antenna shared between WLAN and Bluetooth. ■ QDID: 100820 Declaration ID: D035240. Supports Bluetooth 5.0's LE Secure Connections ■ Bluetooth Class 1 or Class 2 transmitter operation. ■ Supports explicit IEEE 802.11n transmit beamforming. ■ ■ Tx and Rx Low-density Parity Check (LDPC) support for improved range and power efficiency. Supports extended Synchronous Connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets. ■ Supports standard SDIO v2.0 and gSPI host interfaces. ■ ■ Supports Space-Time Block Coding (STBC) in the receiver. Adaptive Frequency Hopping (AFH) for reducing radio frequency interference. ■ Integrated ARM Cortex-M3 processor and on-chip memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to fieldupgrade with future features. On-chip memory includes 512 KB SRAM and 640 KB ROM. ■ Interface support — Host Controller Interface (HCI) using a high-speed UART interface and PCM for audio data. ■ Low-power consumption improves battery life of handheld devices. ■ Supports multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound. ■ Automatic frequency detection for standard crystal and TCXO values. ■ TurboQAM® ❐ data rates (256- ❐ OneDriver™ software architecture for easy migration from existing embedded WLAN and Bluetooth devices as well as to future devices. Cypress Semiconductor Corporation Document Number: 002-14796 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 16, PRELIMINARY General Features ■ ■ Supports a battery voltage range from 3.0V to 4.8V with an internal switching regulator. ■ Programmable dynamic power management. ■ 4 Kbit One-Time Programmable (OTP) memory for storing board parameters. ■ Can be routed on low-cost 1 x 1 PCB stack-ups. ■ 63-ball WLBGA package (4.87 mm × 2.87 mm, 0.4 mm pitch). CYW43438 Security: WPA and WPA2 (Personal) support for powerful encryption and authentication. ❐ AES in WLAN hardware for faster data encryption and IEEE 802.11i compatibility. ❐ Reference WLAN subsystem provides Wi–Fi Protected Setup (WPS). ■ Worldwide regulatory support: Global products supported with worldwide homologated design. ❐ Figure 1. CYW43438 System Block Diagram VDDIO VBAT WL_REG_ON WLAN Host I/F WL_IRQ SDIO*/SPI 2.4 GHz WLAN + Bluetooth TX/RX CLK_REQ BT_REG_ON PCM Bluetooth Host I/F BPF CYW43438 BT_DEV_WAKE BT_HOST_WAKE UART Document Number: 002-14796 Rev. *M Page 2 of 91 PRELIMINARY CYW43438 Contents 1. Overview ............................................................ 5 8. Bluetooth Baseband Core.............................. 33 1.1 Overview ............................................................. 5 8.1 Bluetooth Standard Features .............................33 1.2 Features .............................................................. 6 8.2 Bluetooth 5.0 Features .......................................33 1.3 Standards Compliance ........................................ 6 8.3 Link Control Layer ..............................................33 2. Power Supplies and Power Management ....... 8 8.4 Test Mode Support .............................................34 8.5 Bluetooth Power Management Unit ...................34 8.5.1 RF Power Management ..........................34 8.5.2 Host Controller Power Management ......34 8.5.3 BBC Power Management .......................36 8.5.4 FM Power Management .........................36 8.5.5 Wideband Speech ..................................36 8.5.6 Packet Loss Concealment ......................36 8.5.7 Codec Encoding .....................................37 8.5.8 Multiple Simultaneous A2DP Audio Streams ..................................................37 8.6 Adaptive Frequency Hopping .............................37 8.7 Advanced Bluetooth/WLAN Coexistence ...........37 8.8 Fast Connection (Interlaced Page and Inquiry Scans) ................................................................37 2.1 Power Supply Topology ...................................... 8 2.2 CYW43438 PMU Features .................................. 8 2.3 WLAN Power Management ............................... 11 2.4 PMU Sequencing .............................................. 11 2.5 Power-Off Shutdown ......................................... 12 2.6 Power-Up/Power-Down/Reset Circuits ............. 12 3. Frequency References ................................... 13 3.1 Crystal Interface and Clock Generation ............ 13 3.2 TCXO ................................................................ 13 3.3 External 32.768 kHz Low-Power Oscillator ....... 15 4. WLAN System Interfaces ............................... 16 4.1 SDIO v2.0 .......................................................... 16 4.1.1 SDIO Pin Descriptions ........................... 16 4.2 Generic SPI Mode ............................................. 17 4.2.1 SPI Protocol ........................................... 18 4.2.2 gSPI Host-Device Handshake ............... 21 4.2.3 Boot-Up Sequence ................................ 22 5. Wireless LAN MAC and PHY.......................... 25 5.1 MAC Features ................................................... 25 5.1.1 MAC Description .................................... 25 5.2 PHY Description ................................................ 27 5.2.1 PHY Features ........................................ 28 6. WLAN Radio Subsystem ................................ 29 6.1 Receive Path ..................................................... 30 6.2 Transmit Path .................................................... 30 6.3 Calibration ......................................................... 30 7. Bluetooth Overview ........................................ 31 9. Microprocessor and Memory Unit for Bluetooth ......................................................... 38 9.1 RAM, ROM, and Patch Memory .........................38 9.2 Reset ..................................................................38 10. Bluetooth Peripheral Transport Unit............. 39 10.1 PCM Interface ....................................................39 10.1.1 Slot Mapping ...........................................39 10.1.2 Frame Synchronization ...........................39 10.1.3 Data Formatting ......................................39 10.1.4 Wideband Speech Support .....................39 10.1.5 PCM Interface Timing .............................40 10.2 UART Interface ..................................................44 11. CPU and Global Functions ............................ 46 11.1 WLAN CPU and Memory Subsystem ................46 11.2 One-Time Programmable Memory .....................46 11.3 GPIO Interface ...................................................46 7.1 Features ............................................................ 31 11.4 External Coexistence Interface ..........................47 7.2 Bluetooth Radio ................................................. 32 7.2.1 Transmit ................................................. 32 7.2.2 Digital Modulator .................................... 32 7.2.3 Digital Demodulator and Bit Synchronizer 32 7.2.4 Power Amplifier ..................................... 32 7.2.5 Receiver ................................................ 32 7.2.6 Digital Demodulator and Bit Synchronizer 32 7.2.7 Receiver Signal Strength Indicator ........ 32 7.2.8 Local Oscillator Generation ................... 32 7.2.9 Calibration ............................................. 32 11.5 JTAG Interface ...................................................47 11.6 UART Interface ..................................................47 12. WLAN Software Architecture......................... 48 12.1 Host Software Architecture ................................48 12.2 Device Software Architecture .............................48 12.2.1 Remote Downloader ...............................48 12.3 Wireless Configuration Utility .............................48 13. Pinout and Signal Descriptions..................... 49 13.1 Ball Map .............................................................49 Document Number: 002-14796 Rev. *M Page 3 of 91 PRELIMINARY 13.2 WLBGA Ball List in Ball Number Order with X-Y Coordinates ...................................................... 50 13.3 WLBGA Ball List Ordered By Ball Name ........... 52 13.4 Signal Descriptions ........................................... 53 13.5 WLAN GPIO Signals and Strapping Options .... 56 13.6 Chip Debug Options .......................................... 56 13.7 I/O States .......................................................... 57 14. DC Characteristics.......................................... 59 14.1 Absolute Maximum Ratings .............................. 59 14.2 Environmental Ratings ...................................... 59 14.3 Electrostatic Discharge Specifications .............. 59 14.4 Recommended Operating Conditions and DC Characteristics 60 15. WLAN RF Specifications ................................ 62 15.1 2.4 GHz Band General RF Specifications ......... 62 15.2 WLAN 2.4 GHz Receiver Performance Specifications .................................................... 63 CYW43438 18.1.1 2.4 GHz Mode ........................................78 18.2 Bluetooth Consumption ......................................79 19. Interface Timing and AC Characteristics ..... 80 19.1 SDIO Default Mode Timing ................................80 19.2 SDIO High-Speed Mode Timing .........................81 19.3 gSPI Signal Timing .............................................82 19.4 JTAG Timing ......................................................82 20. Power-Up Sequence and Timing................... 83 20.1 Sequencing of Reset and Regulator Control Signals ...............................................................83 20.1.1 Description of Control Signals ................83 20.1.2 Control Signal Timing Diagrams .............84 21. Package Information ...................................... 86 21.1 Package Thermal Characteristics ......................86 21.1.1 Junction Temperature Estimation and PSI Versus Thetajc ........................................86 22. Mechanical Information.................................. 87 15.3 WLAN 2.4 GHz Transmitter Performance Specifications .................................................... 66 23. Ordering Information...................................... 89 15.4 General Spurious Emissions Specifications ...... 67 26. Additional Information ................................... 89 16. Bluetooth RF Specifications .......................... 68 26.1 Acronyms and Abbreviations .............................89 17. Internal Regulator Electrical Specifications.................................................. 74 Document History........................................................... 90 17.1 Core Buck Switching Regulator ........................ 74 17.2 3.3V LDO (LDO3P3) ......................................... 75 17.3 CLDO ................................................................ 76 17.4 LNLDO .............................................................. 77 26.2 IoT Resources ....................................................89 Sales, Solutions, and Legal Information ...................... 91 Worldwide Sales and Design Support ..............................91 Products ...........................................................................91 PSoC® Solutions ..............................................................91 Cypress Developer Community ........................................91 Technical Support .............................................................91 18. System Power Consumption ......................... 78 18.1 WLAN Current Consumption ............................. 78 Document Number: 002-14796 Rev. *M Page 4 of 91 PRELIMINARY CYW43438 1. Overview 1.1 Overview The Cypress CYW43438 provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The CYW43438 is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 shows the interconnection of all the major physical blocks in the CYW43438 and their associated external interfaces, which are described in greater detail in subsequent sections. Cortex M3 ETM JTAG* SDP Figure 2. CYW43438 Block Diagram Debug AHB AHB Bus Matrix AHB to APB  Bridge RAM ROM APB Patch WD Timer InterCtrl SW Timer DMA Bus Arb  ARM IP GPIO Ctrl JTAG supported over SDIO or BT PCM SDIO or gSPI gSPI ARM CM3 RAM RX/TX GPIO ROM Buffer IF PLL BT PHY Wake/ WiMax Coex Sleep Ctrl WiMax  Coex. BT‐WLAN ECI BT Clock Control Sleep‐ time  Keeping LPO Clock  Management PMU XO  Buffer PMU  Ctrl JTAG* 2.4 GHz PA Shared LNA BPF POR WLAN BT_REG_ON VREGs VBAT PTU XTAL GPIO UART Supported over SDIO or BT PCM UART Radio LCU OTP GPIO 2.4 GHz Digital Mod. Power Supply Sleep CLK XTAL WL_REG_ON WDT MAC PA LNPPHY PCM BlueRF  Interface SDIO IEEE 802.11a/b/g/n I/O Port Control Digital I/O BT Clock/  Hopper RF SWREG LDOx2 LPO XTAL OSC. POR PMU Control Backplane Debug  UART Modem Digital  Demod.  & Bit  Sync APU JTAG* Buffer Common and  Radio Digital BPL UART * Via GPIO configuration, JTAG is supported over SDIO or BT PCM Document Number: 002-14796 Rev. *M Page 5 of 91 PRELIMINARY CYW43438 1.2 Features The CYW43438 supports the following WLAN and Bluetooth features: ■ IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch ■ Bluetooth 5.1 with integrated Class 1 PA ■ Concurrent Bluetooth, and WLAN operation ■ On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality ■ Simultaneous BT/WLAN reception with a single antenna ■ WLAN host interface options: ❐ SDIO v2.0, including default and high-speed timing. ❐ gSPI—up to a 50 MHz clock rate ■ BT UART (up to 4 Mbps) host digital interface that can be used concurrently with the above WLAN host interfaces. ■ ECI—enhanced coexistence support, which coordinates BT SCO transmissions around WLAN receptions. ■ PCM for BT audio ■ HCI high-speed UART (H4 and H5) transport support ■ Wideband speech support (16 bits, 16 kHz sampling PCM, through PCM interfaces) ■ Bluetooth SmartAudio® technology improves voice and music quality to headsets. ■ Bluetooth low power inquiry and page scan ■ Bluetooth Low Energy (BLE) support ■ Bluetooth Packet Loss Concealment (PLC) ■ Multiple simultaneous A2DP audio streams 1.3 Standards Compliance The CYW43438 supports the following standards: ■ Bluetooth 5.1 compliance (Basic Rate, Enhanced Data Rate and Bluetooth Low Energy) ■ IEEE 802.11n—Handheld Device Class (Section 11) ■ IEEE 802.11b ■ IEEE 802.11g ■ IEEE 802.11d ■ IEEE 802.11h ■ IEEE 802.11i ■ The CYW43438 will support the following future drafts/standards: ■ IEEE 802.11r — Fast Roaming (between APs) ■ IEEE 802.11k — Resource Management ■ IEEE 802.11w — Secure Management Frames ■ IEEE 802.11 Extensions: ■ IEEE 802.11e QoS Enhancements (as per the WMM® specification is already supported) ■ IEEE 802.11i MAC Enhancements ■ IEEE 802.11r Fast Roaming Support ■ IEEE 802.11k Radio Resource Measurement The CYW43438 supports the following security features and proprietary protocols: ■ Security: Document Number: 002-14796 Rev. *M Page 6 of 91 PRELIMINARY CYW43438 WEP WPA™ Personal ™ ❐ WPA2 Personal ❐ WMM ❐ WMM-PS (U-APSD) ❐ WMM-SA ❐ WAPI ❐ AES (Hardware Accelerator) ❐ TKIP (host-computed) ❐ CKIP (SW Support) ❐ ❐ ■ Proprietary Protocols: ❐ CCXv2 ❐ CCXv3 ❐ CCXv4 ❐ CCXv5 ■ IEEE 802.15.2 Coexistence Compliance — on silicon solution compliant with IEEE 3-wire requirements. Document Number: 002-14796 Rev. *M Page 7 of 91 PRELIMINARY CYW43438 2. Power Supplies and Power Management 2.1 Power Supply Topology One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43438. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs. A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the CYW43438. Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective circuit blocks out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO can be turned on and off based on the dynamic demands of the digital baseband. The CYW43438 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 provides the CYW43438 with all required voltage, further reducing leakage currents. Note: VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device. Note: VDDIO should be connected to the WCC_VDDIO pin of the device. 2.2 CYW43438 PMU Features The PMU supports the following: ■ VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator ■ VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3 ■ 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO ■ 1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep ■ Additional internal LDOs (not externally accessible) ■ PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode. Figure 3 and Figure 4 show the typical power topology of the CYW43438. Document Number: 002-14796 Rev. *M Page 8 of 91 CYW43438 PRELIMINARY Figure 3. Typical Power Topology (1 of 2) SR_VDDBAT5V VBAT Mini PMU CYW43438 1.2V VBAT: Operational: — Performance: — Absolute Maximum: 5.5V VDDIO Operational: — Core Buck  Int_SR_VBAT Regulator  Peak: 370 mA Avg: 170 mA (320 mA) V V V Internal VCOLDO 80 mA (NMOS) 1.2V WL RF—LOGEN Internal RXLDO 10 mA (NMOS) 1.2V WL RF—RX LNA Internal ADCLDO 10 mA (NMOS) 1.2V WL RF—ADC REF Internal TXLDO 80 mA (PMOS) 1.2V WL RF—TX Internal AFELDO 80 mA (NMOS) 1.2V 1.35V WL RF—AFE and TIA Mini PMU is placed  in WL radio 2.2 uH 0603 LDO_VDD_1P5 SR_VBAT5V SR_PVSS GND VDD1P35 SR_VLX SW1  VBAT WL RF—TX Mixer and PA (not all versions) 4.7 uF 0402 LNLDO (100 mA) 1.2V 600 @ 100 MHz WL RF—XTAL FM_RF_VDD VOUT_LNLDO 2.2 uF 0402 PMU_VSS WLRF_XTAL_ VDD1P2 FM LNA, Mixer, TIA, VCO BTFM_PLL_VDD 6.4 mA BT_IF_VDD WCC_VDDIO (40 mA) LPLDO1 (5 mA) 4.6 mA 0.1 uF 0201 BT_VCO_VDD WCC_VDDIO 10 mA average,  > 10 mA at start‐up WL RF—RFPLL PFD and MMD FM PLL, LOGEN, Audio DAC/BT PLL BT LNA, Mixer, VCO BT ADC, Filter 1.1V WLAN/BT/CLB/Top, Always On VDDC1 1.3V, 1.2V,  CL LDO or 0.95V Peak: 200 mA (AVS) Avg: 80 mA (Bypass in deep‐ VOUT_CLDO sleep) WL_REG_ON BT_REG_ON WL OTP VDDC2 2.2 uF 0402 o_wl_resetb o_bt_resetb Supply ball WL Digital and PHY WL VDDM (SROMs & AOS) Supply bump/pad Power switch BT VDDM Ground ball Ground bump/pad No power switch BT/WLAN reset balls External to chip No dedicated power switch, but internal power ‐ down modes and block ‐specific power switches Document No. Document Number: 002-14796 Rev. *M BT Digital Page 9 of 108 CYW43438 PRELIMINARY Figure 4. Typical Power Topology (2 of 2) CYW43438 1.8V, 2.5V, and 3.3V VBAT LDO_ VDDBAT5V 6.4 mA WL BBPLL/DFLL WL OTP 3.3V LDO3P3 with Back‐Power  VOUT_3P3 Protection 4.7 uF (Peak 450‐800 mA 200 mA Average) 3.3V 0402 480 to 800 mA WLRF_PA_VDD WL RF—PA (2.4 GHz) 1 uF 0201 2.5V Cap‐less  LNLDO (10 mA) 22  ohm 6.4 mA WL RF—ADC, AFE, LOGEN,  LNA, NMOS Mini‐PMU LDOs Placed inside WL Radio BT_PAVDD Peak: 70 mA Average: 15 mA BT Class 1 PA 1 uF 0201 Power switch External to chip No power switch Supply ball No dedicated power switch, but internal power‐ down modes and block‐specific power switches Document No. Document Number: 002-14796 Rev. *M Page 10 of 108 PRELIMINARY CYW43438 2.3 WLAN Power Management The CYW43438 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW43438 integrated RAM is a high volatile memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the CYW43438 includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43438 into various power management states appropriate to the operating environment and the activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible. The CYW43438 WLAN power states are described as follows: ■ Active mode— All WLAN blocks in the CYW43438 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. ■ Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43438 remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current. ■ Deep-sleep mode—Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. To avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wakeup event is triggered by an external interrupt, a host resume through the SDIO bus, or by the PMU timers. ■ Power-down mode—The CYW43438 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-enabling the internal regulators. 2.4 PMU Sequencing The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them. Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. Each resource is in one of the following four states: ■ enabled ■ disabled ■ transition_on ■ transition_off The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. During each clock cycle, the PMU sequencer performs the following actions: ■ Computes the required resource set based on requests and the resource dependency table. ■ Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource and inverts the ResourceState bit. ■ Compares the request with the current resource status and determines which resources must be enabled or disabled. ■ Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents. ■ Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. Document Number: 002-14796 Rev. *M Page 11 of 91 PRELIMINARY CYW43438 2.5 Power-Off Shutdown The CYW43438 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. When the CYW43438 is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the CYW43438 to be effectively off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected to the I/O. During a low-power shutdown state, provided VDDIO remains applied to the CYW43438, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the CYW43438 to be fully integrated in an embedded device and to take full advantage of the lowest power-savings modes. When the CYW43438 is powered on from this state, it is the same as a normal power-up, and the device does not retain any information about its state from before it was powered down. 2.6 Power-Up/Power-Down/Reset Circuits The CYW43438 has two signals (see Table 2) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 20.: “Power-Up Sequence and Timing” . Table 2. Power-Up/Power-Down/Reset Control Signals Signal Description WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal CYW43438 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal CYW43438 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. Document Number: 002-14796 Rev. *M Page 12 of 91 PRELIMINARY CYW43438 3. Frequency References An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. 3.1 Crystal Interface and Clock Generation The CYW43438 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator, including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration. Figure 5. Recommended Oscillator Configuration C WLRF_XTAL_XOP 12 – 27 pF C WLRF_XTAL_XON 12 – 27 pF R Note: Resistor value determined by crystal drive level. See reference schematics for details. The CYW43438 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can operate using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal interfaced directly to the CYW43438. The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and characteristics for the crystal interface are shown in Table 3. Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Broadcom for further details. 3.2 TCXO As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase noise requirements listed in Table 3. If the TCXO is dedicated to driving the CYW43438, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor with value ranges from 200 pF to 1000 pF as shown in Figure 6. Figure 6. Recommended Circuit to Use with an External Dedicated TCXO 200 pF – 1000 pF TCXO WLRF_XTAL_XOP NC Document Number: 002-14796 Rev. *M WLRF_XTAL_XON Page 13 of 91 PRELIMINARY CYW43438 Table 3. Crystal Oscillator and External Clock Requirements and Performance Parameter External Frequency Reference Crystal Conditions/Notes Min. Typ. 1 Max. Min. Typ. Max. Units – – – – MHz Frequency – – 37.4 Crystal load capacitance – – 12 – – – – pF ESR – – – 60 – – – Ω Drive level External crystal must be able to tolerate this drive level. 200 – – – – – μW Resistive – – – 10k 100k – Ω Capacitive – – – – – 7 pF – 1260 mVp-p Input Impedance (WLRF_XTAL_XOP) 2 WLRF_XTAL_XOP input voltage AC-coupled analog signal – – – 400 WLRF_XTAL_XOP input low level DC-coupled digital signal – – – 0 – 0.2 V WLRF_XTAL_XOP input high level DC-coupled digital signal – – – 1.0 – 1.26 V Frequency tolerance Initial + over temperature – –20 – 20 –20 – 20 ppm Duty cycle 37.4 MHz clock – – – 40 50 60 % Phase Noise3, 4, 5 (IEEE 802.11 b/g) 37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz 3, 4, 5 Phase Noise (IEEE 802.11n, 2.4 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz Phase Noise3, 4, 5 (256-QAM) 37.4 MHz clock at 10 kHz offset – – – – – –140 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –147 dBc/Hz 1. The frequency step size is approximately 80 Hz. The CYW43438 does not auto-detect the reference clock frequency; the frequency is specified in the software and/or NVRAM file. 2. To use 256-QAM, a 800 mV minimum voltage is required. 3. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. 4. Phase noise is assumed flat above 100 kHz. 5. The CYW43438 supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table. Document Number: 002-14796 Rev. *M Page 14 of 91 PRELIMINARY CYW43438 3.3 External 32.768 kHz Low-Power Oscillator The CYW43438 uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons. Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table 4. Note: The CYW43438 will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it doesn't sense a clock, it will use its own internal LPO. ■ To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating. ■ To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK. Table 4. External 32.768 kHz Sleep-Clock Specifications Parameter Nominal input frequency Frequency accuracy Duty cycle Input signal amplitude Signal type Input impedance1 Clock jitter LPO Clock Units 32.768 kHz ±200 ppm 30–70 % 200–3300 mV, p-p Square wave or sine wave – >100 kΩ