Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PRELIMINARY
CYW43907
WICED™ IEEE 802.11 a/b/g/n SoC with an
Embedded Applications Processor
The Cypress CYW43907 embedded wireless system-on-a-chip (SoC) is uniquely suited for Internet-of-Things (IoT) applications. It
supports all rates specified in the IEEE 802.11 a/b/g/n specifications.The device includes an Arm® Cortex®-based applications
processor, a single stream IEEE 802.11n MAC/baseband/radio, a dual-band 5 GHz and 2.4 GHz transmit power amplifier (PA), and
a receive low-noise amplifier (LNA). It also supports optional antenna diversity for improved RF performance in difficult environments.
The CYW43907 is an optimized SoC targeting embedded IoT applications in the industrial and medical sensor, home appliance, and
embedded audio markets. Using advanced design techniques and process technology to reduce active and idle power, the device is
designed for embedded applications that require minimal power consumption and a compact size.
The device includes a PMU for simplifying system power topology and allows for direct operation from a battery while maximizing
battery life.
Features
Application Processor Features
■
■
Arm® Cortex®-R4 32-bit RISC processor.
■
2 MB of on-chip SRAM for code and data.
■
An on-chip Cryptography core
■
WICED®
640 KB of ROM containing
as RTOS and TCP/IP stack.
■
Software architecture supported by standard WICED® SDK
allows easy migration from existing discrete MCU designs
and to future devices.
Security support:
❐
SDK components such
❐
WPA and WPA2 (Personal) support for powerful
encryption and authentication.
AES and TKIP in hardware for faster data encryption and
IEEE 802.11i compatibility.
Reference WLAN subsystem provides Cisco compatible
extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, and CCX
5.0).
Wi-Fi Protected Setup and Wi-Fi Easy Setup
■
17 GPIOs supported.
■
Q-SPI serial flash interface to support up to 40 Mbps of peak
transfer.
■
Support for UART (3), SPI/ Cypress Serial Control (CSC)
Master (2), CSC-only (2), and I2S (2) Interfaces. (CSC is an
I2C-compatible Interface.)
■
■
Dedicated fractional PLL for audio clock (MCLK) generation.
General Features
■
USB 2.0 host and device modes.
■
■
SDIO 3.0 host mode.
Supports battery voltage range from 3.0 V to 4.8 V with an
internal switching regulator.
■
Programmable dynamic power management.
■
6 Kb OTP memory for storing board parameters
■
316-bump wafer-level chip-scale package (WLCSP)
(4.583 mm × 5.533mm, 0.2mm pitch)
Key IEEE 801.11x Features
■
IEEE 802.11n compliant.
■
Single-stream spatial multiplexing up to 150 Mbps.
■
Supports 20/40 MHz channels with optional SGI.
■
Full IEEE 802.11 a/b/g legacy compatibility with enhanced
performance.
■
On-chip power and low-noise amplifiers.
■
An internal fractional nPLL allows support for a wide range of
reference clock frequencies.
■
❐
❐
Worldwide regulatory support: Global products supported
with worldwide design approval.
Integrated Arm® Cortex®-R4 processor with tightly coupled
memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for
standard WLAN functions (to further minimize power consumption while maintaining the ability to upgrade to future
features in the field).
Cypress Semiconductor Corporation
Document Number: 002-14829 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised Tuesday, March 23, 2021
PRELIMINARY
CYW43907
n.
Figure 1. Functional Block Diagram
CYW43907
2 MB RAM,
640 KB ROM
USB 2.0
UART
SDIO 3.0
CSC
PWM (6)
PWM
SPI
CSC (2)
USB
SPI (2)
GPIO
Crytography
Engine
AXI
DMA
I2S
Audio PLL
RMII/MII
AXI
Audio
32 kHz
External LPO
®
WLAN Arm
Cortex ® -R4
AXI-to-AXI
Bridge
AXI to AXI
Bridge
JTAG
GPIO (17)
I2S (2)
APPS ARM
Cortex-R4
32 KB (I),
32 KB (D)
ICACHE
SDIO
UART (3)
TCM
512 KB RAM
320 KB ROM
WLAN
IEEE 802.11 MAC
APPS Domain
RF Switch Controls
1 x 1, IEEE 802.11n PHY
Always-On Domain
REG_ON
HIB_REG_ON_IN
AXI
PS RAM
PS
SR_Eng
CSC = Cypress Serial Control. An I2C‐compatible interface.
PMU
TX
Switch
VIO
LNA
PMU
Control
VBAT
37.4 MHz Crystal
2.4 GHz and 5 GHz Radio
AXI-to-AXI
Bridge
2.4 GHz
PA
LNA
5 GHz
PA
TX
Switch
WRF_PAOUT_5G
WRF_RFIN_5G
WRF_PAOUT_2G
WRF_RFIN_2G
Document Number: 002-14829 Rev. *L
Page 2 of 94
PRELIMINARY
CYW43907
Contents
1. Overview ................................................................ 5
1.1
Introduction ..............................................................5
1.1.1
1.2
7.2
Features ...................................................... 5
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
Standards Compliance .............................................6
2. Power Supplies and Management....................... 7
2.1
Power Supply Topology ...........................................7
2.2
CYW43907 Power Management Unit Features .......7
2.3
Power Management ..............................................10
2.4
PMU Sequencing ...................................................10
2.5
Power OFF Shutdown ............................................11
2.6
Power Up/Power Down/Reset Circuits ...................11
3. Frequency References ....................................... 12
3.1
Crystal Interface and Clock Generation .................12
3.2
External Frequency Reference ..............................13
3.3
External 32.768 kHz Low-Power Oscillator (LPO) .14
4. Applications Subsystem .................................... 15
4.1
Overview ................................................................15
4.2
Applications CPU and Memory Subsystem ...........15
4.3
Memory-to-Memory DMA Core ..............................15
4.4
Cryptography Core .................................................15
5. Applications Subsystem External Interfaces ... 16
IEEE 802.11n MAC ................................................ 25
7.2.1 Programmable State Machine (PSM) ......... 26
7.2.2 Wired Equivalent Privacy (WEP) ................ 26
7.3
Transmit Engine (TXE) ............................... 27
Receive engine (RXE) ................................ 27
Interframe-spacing (IFS) ............................. 27
Timing Synchronization Function (TSF) ..... 27
Network Allocation Vector (NAV) ................ 27
MAC-PHY Interface .................................... 28
IEEE 802.11™ a/b/g/n PHY .................................... 28
8. WLAN Radio Subsystem ................................... 29
8.1
Receiver Path ......................................................... 29
8.2
Transmit Path ......................................................... 29
8.3
Calibration .............................................................. 29
9. Pinout and Signal Descriptions........................ 30
9.1
Bump List ............................................................... 31
9.2
Signal Descriptions ................................................ 35
10. GPIO Signals and Strapping Options ............... 41
10.1 Overview ................................................................ 41
10.2 Weak Pull-Down and Pull-Up Resistances ............ 41
10.3 Strapping Options .................................................. 41
10.4 Alternate GPIO Signal Functions ...........................42
11. Pin Multiplexing .................................................. 43
5.1
Ethernet MAC Controller (MII/RMII) .......................16
5.2
GPIO ......................................................................16
12. I/O States ............................................................. 46
5.3
Cypress Serial Control (CSC) ................................16
13. Electrical Characteristics................................... 48
5.4
I2S ..........................................................................16
13.1 Absolute Maximum Ratings ................................... 48
Arm®
5.5
JTAG and
Serial Wire Debug .......................18
13.2 Environmental Ratings ........................................... 48
5.6
Pulse Width Modulation (PWM) .............................18
13.3 Electrostatic Discharge Specifications ................... 49
5.7
SDIO 3.0 - Host Mode ............................................18
5.8
S/PDIF ....................................................................19
13.4 Recommended Operating Conditions and DC ...........
Characteristics 49
5.9
SPI Flash ................................................................19
13.5 Power Supply Segments ........................................ 51
5.10 UART .....................................................................20
13.6 Ethernet MAC Controller (MII/RMII) DC
Characteristics ....................................................... 51
5.11 USB 2.0 ..................................................................20
5.11.1 Overview .....................................................20
5.11.2 USB 2.0 Features ....................................... 22
5.12 SPI .........................................................................22
6. Global Functions................................................. 23
13.7 GPIO, UART, and JTAG Interfaces DC
Characteristics ....................................................... 51
14. WLAN RF Specifications.................................... 52
14.1 Introduction ............................................................ 52
14.2 2.4 GHz Band General RF Specifications .............. 52
6.1
External Coexistence Interface ..............................23
6.2
OTP ........................................................................23
6.3
Hibernation Block ...................................................23
6.4
System Boot Sequence ..........................................24
14.4 WLAN 2.4 GHz Transmitter Performance ..................
Specifications 55
7. Wireless LAN Subsystem................................... 25
14.5 WLAN 5 GHz Receiver Performance
Specifications ......................................................... 56
7.1
WLAN CPU and Memory Subsystem ....................25
Document Number: 002-14829 Rev. *L
14.3 WLAN 2.4 GHz Receiver Performance
Specifications ......................................................... 53
Page 3 of 94
PRELIMINARY
CYW43907
14.6 WLAN 5 GHz Transmitter Performance
Specifications .........................................................58
17.5.3 Memory Fast-Read Timing ......................... 80
14.7 General Spurious Emissions Specifications ...........58
14.7.1 Transmitter Spurious Emissions
Specifications .............................................59
14.7.2 Receiver Spurious Emissions
Specifications .............................................60
17.5.5 SPI Flash Parameters ................................ 82
15. Internal Regulator Electrical Specifications..... 61
15.1 Core Buck Switching Regulator .............................61
17.5.4 Memory-Write Timing ................................. 81
17.6 USB PHY Electrical Characteristics and Timing .... 83
17.6.1 USB 2.0 and USB 1.1 Electrical and
Timing Parameters ..................................... 83
17.6.2 USB 2.0 Timing Diagrams .......................... 85
18. Power-Up Sequence and Timing ....................... 87
15.4 LNLDO ...................................................................64
18.1 Sequencing of Reset and Regulator Control
Signals ................................................................... 87
18.1.1 Description of Control Signals .................... 87
18.1.2 Control Signal Timing Diagrams ................. 87
15.5 BBPLL LDO ............................................................65
19. Thermal Information ........................................... 88
16. System Power Consumption ............................. 66
19.1 Package Thermal Characteristics .......................... 88
16.1 WLAN Current Consumption ..................................66
16.1.1 2.4 GHz Mode ............................................66
16.1.2 5 GHz Mode ...............................................67
19.2 Junction Temperature Estimation and PSIJT Versus .
THETAJC 88
17. Interface Timing and AC Characteristics.......... 68
20. Mechanical Information...................................... 89
17.1 Ethernet MAC (MII/RMII) Interface Timing .............68
17.1.1 MII Receive Packet Timing .........................68
21. Ordering Information.......................................... 90
17.1.2 MII Transmit Packet Timing ........................ 68
22. Additional Information ....................................... 90
15.2 3.3V LDO (LDO3P3) ..............................................62
15.3 CLDO .....................................................................63
19.3 Environmental Characteristics ............................... 88
17.1.3 RMII Receive Packet Timing ...................... 69
22.1 Acronyms and Abbreviations ................................. 90
17.1.4 RMII Transmit Packet Timing ..................... 70
22.2 References ............................................................. 91
I2S
Master and Slave Mode TX Timing ..................71
22.3 IoT Resources ........................................................ 91
17.3 SDIO Interface Timing ............................................73
17.3.1 SDIO Default-Speed Mode Timing .............73
22.4 Errata ..................................................................... 91
17.2
17.3.2 SDIO High-Speed Mode Timing ................. 74
17.3.3 SDIO Bus Timing Specifications in SDR
Modes .........................................................75
17.4 S/PDIF Interface Timing .........................................76
17.5 SPI Flash Timing ....................................................78
17.5.1 Read-Register Timing .................................78
Document History Page ..................................................... 92
Sales, Solutions, and Legal Information .......................... 94
Worldwide Sales and Design Support ............................94
Products ......................................................................... 94
Cypress Developer Community ...................................... 94
Technical Support ........................................................... 94
17.5.2 Write-Register Timing ................................. 79
Document Number: 002-14829 Rev. *L
Page 4 of 94
PRELIMINARY
CYW43907
1. Overview
1.1 Introduction
The Cypress CYW43907 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip with
integrated IEEE 802.11 a/b/g/n MAC/baseband/radio and a separate Arm® Cortex®-R4 applications processor. It provides a small
form-factor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system with
flexibility in size, form, and function. Comprehensive power management circuitry and software ensure that the system can meet the
needs of highly embedded systems that require minimal power consumption and reliable operation.
Figure 2 shows the interconnect of all the major physical blocks in the CYW43907 and their associated external interfaces, which are
described in greater detail in Section 5. “Applications Subsystem External Interfaces”.
Figure 2. Block Diagram and I/O
CYW43907
SPI Flash
GPIO[16:0]
RF TX
APPS Subsystem
WLAN Subsystem
Arm® Cortex®‐R4
Arm® Cortex®‐R4
320 MHz
32 KB I‐cache
32 KB D‐cache
160 MHz
448 KB ROM TCM
576 KB SRAM TCM
2 MB SRAM
640 KB ROM
802.11n
1x1
2.4 GHz and 5 GHz
RF RX
2x 2-Wire UART
4-Wire UART
2x I2S
2x SPI/CSC
2x CSC
JTAG/SWD
10/100 Ethernet
Switch Control
Antenna Diversity
SDIO 3.0/gSPI
VDDIOs
USB 2.0
GND
WAKE
1.1.1 Features
The CYW43907 supports the following features:
■
The applications domain (APPS) Arm® Cortex®-R4 core can be clocked at 60 MHz, 80 MHz, 120 MHz, 160 MHz or 320 MHz.
■
2 MB of SRAM and 640 KB ROM available for the applications processor.
■
One high-speed 4-wire UART Interface with operation up to 3 Mbps.
■
Two low-speed 2-wire UART interfaces multiplexed on general purpose I/O (GPIO) pins.
■
Two dedicated CSC1 interfaces.
■ Two SPI master interfaces with operation up to 24 MHz.
Note: Either or both of the SPI interfaces can be used as CSC master interfaces. This is in addition to the two dedicated CSC
interfaces.
■
One SPI Master Interface for Serial Flash.
■
Six dedicated PWM outputs.
1. Cypress Serial Control (CSC) is an I2C-compatible Interface.
Document Number: 002-14829 Rev. *L
Page 5 of 94
PRELIMINARY
■
Two I2S interfaces.
■
Seventeen GPIOs.
■
IEEE 802.11 a/b/g/n 1×1 2.4 GHz and 5 GHz radio.
■
Single and dual-antenna support.
CYW43907
1.2 Standards Compliance
The CYW43907 supports the following standards:
■
IEEE 802.11n
■
IEEE 802.11b
■
IEEE 802.11g
■
IEEE 802.11d
■
IEEE 802.11h
■
IEEE 802.11i
■
Security:
❐
WEP
❐
WPA Personal
❐
WPA2 Personal
❐
WMM
❐
WMM-PS (U-APSD)
❐
WMM-SA
❐
AES (hardware accelerator)
❐
TKIP (hardware accelerator)
❐
CKIP (software support)
The CYW43907 supports the following additional standards:
■
IEEE 802.11r—Fast Roaming (between APs)
■
IEEE 802.11w—Secure Management Frames
■
IEEE 802.11 Extensions:
❐
IEEE 802.11e QoS enhancements (already supported as per the WMM specification)
❐
IEEE 802.11i MAC enhancements
❐
IEEE 802.11k radio resource measurement
Document Number: 002-14829 Rev. *L
Page 6 of 94
PRELIMINARY
CYW43907
2. Power Supplies and Management
2.1 Power Supply Topology
One core buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43907. All
regulators are programmable via the PMU. These blocks simplify power supply design for application and WLAN functions in
embedded designs.
A single VBAT (3.0V to 4.8V DC maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by
the regulators in the CYW43907.
The REG_ON control signal is used to power up the regulators and take the appropriate sections out of reset. The CBUCK, CLDO,
LNLDO, and other regulators power up when any of the reset signals are deasserted. All regulators are powered down only when
REG_ON is deasserted. The regulators may be turned off/on based on the dynamic demands of the digital baseband.
The CYW43907 provides a low power-consumption mode whereby the CBUCK, CLDO, and LNLDO regulators are shutdown. In this
state, the low-power linear regulator (LPLDO1) supplied by the system VIO supply provides the CYW43907 with all required voltages.
2.2 CYW43907 PMU Features
The CYW43907 supports the following PMU features:
■
VBAT to 1.35Vout (550 mA maximum) core buck (CBUCK) switching regulator
■
VBAT to 3.3Vout (450 mA maximum) LDO3P3
■
1.35V to 1.2Vout (150 mA maximum) LNLDO
■
1.35V to 1.2Vout (350 mA maximum) CLDO with bypass mode for Deep Sleep
■
1.35V to 1.2Vout (55 mA maximum) LDO for BBPLL
■
Additional internal LDOs (not externally accessible)
■
PMU internal timer auto-calibration by the crystal clock for precise wakeup timing from the low power-consumption mode.
Figure 3 and Figure 4 show the regulators and a typical power topology.
Document Number: 002-14829 Rev. *L
Page 7 of 94
PRELIMINARY
CYW43907
Figure 3. Typical Power Topology (Page 1 of 2)
WLRF TX Mixer and PA (not always)
CYW43907 1.2V
VBAT
Operational:
2.3V to 4.8V
Performance:
3.0V to 4.8V
Absolute Maximum: 5.5V
VDDIO
Operational:
3.3V
Cap-less
LNLDO
1.2V
Cap-less
LNLDO
1.2V
Cap-less
VCOLDO
Cap-less
LNLDO
1.2V
Cap-less
LNLDO
1.2V
15 mA
XTAL LDO
1.2V
1.2V
Mini‐PMU
(Inside WL Radio)
VBAT
1.35V
LPLDO1
WLRF LNA
WLRF AFE and TIA
WLRF TX
WLRF ADC REF
WLRF XTAL
WLRF RFPLL, PFD, and MMD
1.2V
LNLDO
Core Buck
Regulator
(CBUCK)
VDDIO
WLRF LOGEN
1.35V
BBPLL
LNLDO
Audio PLL
1.2V
WL BBPLL/DFLL
REG_ON
CLDO
1.3V, 1.2V,
.095V (AVS)
WLAN/CLB/Top, Always On
WL PHY
WL Subcore
Supply ball
Supply bump/pad
Power
switch
Ground ball
Ground bump/pad
No power switch
WLAN reset
ball
External to chip
No dedicated power switch, but internal power‐
down modes and block‐specific power switches
Document Number: 002-14829 Rev. *L
WL VDDM (SRAMS in AOS)
APPS VDDM
APPS SOCSRAM
APPS Subcore
Page 8 of 94
PRELIMINARY
CYW43907
Figure 4. Typical Power Topology (Page 2 of 2)
CYW43907 2.5V and 3.3V
450 to
800 mA
WLRF PA(2.4 GHz and 5 GHz)
3.3V
VBAT
LDO3P3
WLRF Pad (2.4 GHz and 5 GHz)
VDDIO_RF
WL OTP 3.3V
2.5V Cap-less
LNLDO
WL RF RX, TX, NMOS, Mini-PMU LDOs
2.5V Cap-less
LNLDO
2.5V
2.5V Cap-less
LNLDO
2.5V
WL RF VCO
WL RF CP
VCOLDO2P5
Inside WL Radio
Supply ball
Supply bump/pad
Power
switch
Ground ball
Ground bump/pad
No power switch
External to chip
No dedicated power switch, but internal power‐
down modes and block‐specific power switches
Document Number: 002-14829 Rev. *L
Page 9 of 94
PRELIMINARY
CYW43907
2.3 Power Management
The CYW43907 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW43907 includes an advanced PMU sequencer. The PMU sequencer provides significant
power savings by putting the CYW43907 into various power management states appropriate to the environment and activities that
are being performed. The PMU enables and disables internal regulators, switches, and other blocks based on a computation of the
required resources and a table that describes the relationship between resources and the time needed to enable and disable them.
Power up sequences are fully programmable. Configurable, free-running counters (running at a 32.768 kHz LPO clock) in the PMU
sequencer are used to turn on and turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated
altogether) as a function of the mode. Slower clock speeds are used whenever possible.
Table 2 provides descriptions for the CYW43907 power modes.
Table 2. CYW43907 Power Modes
Mode
Description
Active
All WLAN blocks in the CYW43907 are powered up and fully functional with active carrier sensing and frame
transmission and receiving.
All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds
are dynamically adjusted by the PMU sequencer.
Doze
The radio, analog domains, and most of the linear regulators are powered down.
The rest of the CYW43907 remains powered up in an idle state. All main clocks (PLL, crystal oscillator, or TCXO)
are shut down to minimize active power consumption. The 32.768 kHz LPO clock is available only for the PMU
sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active
Mode. In Doze Mode, the primary power consumed is due to leakage current.
Deep Sleep
Most of the chip, including both analog and digital domains and most of the regulators, is powered OFF.
Logic states in the digital core are saved and preserved in a retention memory in the Always-On domain before
the digital core is powered off. Upon a wakeup event triggered by the PMU timers, an external interrupt, or a host
resume through the USB bus, logic states in the digital core are restored to their pre-Deep Sleep settings to avoid
lengthy Hardware reinitialization.
Power Down
The CYW43907 is effectively powered OFF by shutting down all internal regulators.
The chip is brought out of this mode by external logic re-enabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer minimizes system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable
them.
Resource requests can come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource-request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of the following four states:
■
Enabled
■
Disabled
■
Transition_on
■
Transition_off
The timer contains 0 when the resource is enabled or disabled and a nonzero value when in a transition state. The timer is loaded
with the time_on or time_off value of the resource after the PMU determines that the resource must be enabled or disabled and
decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to
enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0
indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence
refer to either the immediate transition or the timer load-decrement sequence.
Document Number: 002-14829 Rev. *L
Page 10 of 94
PRELIMINARY
CYW43907
During each clock cycle, the PMU sequencer performs the following actions:
■
Computes the required resource set based on requests and the resource dependency table.
■
Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit of the resource
and inverts the ResourceState bit.
■
Compares the request with the current resource status and determines which resources must be enabled or disabled.
■
Initiates a disable sequence for each resource that is enabled, is no longer being requested, and has no powered-up dependents.
■
Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
2.5 Power off Shutdown
The CYW43907 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other system
devices remain operational. When the CYW43907 is not needed in the system, VDDIO_RF and VDDC are shutdown while VDDIO
remains powered. This allows the CYW43907 to be effectively off while keeping the I/O pins powered so that they do not draw extra
current from devices connected to the I/O.
During a low-power shutdown state, provided VDDIO remains applied to the CYW43907, all outputs are tristate and most inputs
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW43907 to be fully integrated in an embedded device while
taking full advantage of the lowest power-saving modes.
When the CYW43907 is powered on from this state, it is the same as a normal power-up and does not retain any information about
its state from before it was powered down.
2.6 Power Up/Power Down/Reset Circuits
The CYW43907 has two signals (see Table 3) that enable or disable circuits and the internal regulator blocks, allowing the host to
control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 18. “Power-Up
Sequence and Timing”.
Table 3. Power-Up/Power-Down/Reset Control Signals
Signal
Description
REG_ON
This signal is used by the PMU to power up the CYW43907. It controls the internal CYW43907 regulators.
When this pin is high, the regulators are enabled and the device is out of reset. When this pin is low, the device
is in reset and the regulators are disabled. This pin has an internal 200 k pull-down (PD) resistor that is
enabled by default. It can be disabled through programming.
HIB_REG_ON_IN
This signal is used by the hibernation block to decide whether or not to power down the internal CYW43907
regulators. If HIB_REG_ON_IN is LOW, the regulators will be disabled. For a signal at HIB_REG_ON_IN to
function as intended, HIB_REG_ON_OUT must be connected to REG_ON.
Document Number: 002-14829 Rev. *L
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PRELIMINARY
CYW43907
3. Frequency References
An external crystal is used for generating all radio frequencies and normal-operation clocking. As an alternative, an external frequency
reference can be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW43907 can use an external crystal to provide a frequency reference. The recommended crystal oscillator configuration,
including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration.
Figure 5. Recommended Oscillator Configuration
Device boundary
C
WRF_XTAL_XON
1.3 pF
27 pF
37.4 MHz
C
x ohms
27 pF
Programmable internal shunt caps are
from 0 pF to 7.5 pF in steps of 0.5 pF.
WRF_XTAL_XOP
0.4 pF
External resistor and programmable
internal resistor value is determined
by crystal drive level.
Programmable internal series resistor is from 50 ohms to 500 ohms
in steps of 50 ohms. Boot‐up ROM value is 50 ohms.
Note: A reference schematic is available for further details. Contact your Broadcom FAE.
A fractional-N synthesizer in the CYW43907 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate
using a wide selection of frequency references.
The recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal interface are listed in
Table 4.
Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details.
Document Number: 002-14829 Rev. *L
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PRELIMINARY
CYW43907
3.2 External Frequency Reference
An alternate crystal to the external precision frequency reference can be used, provided that it meets the phase noise requirements
listed in Table 4.
If used, the external clock should be connected to the WRF_XTAL_XON pin through an external 1000 pF coupling capacitor, as shown
in Figure 6. The internal clock buffer connected to this pin will be turned off when the CYW43907 goes into Sleep Mode. When the
clock buffer turns on and off, there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P35 pin.
Figure 6. Recommended Circuit to Use With an External Reference Clock
1000 pF
Reference
Clock
WRF_XTAL_XON
NC
WRF_XTAL_XOP
Table 4. Crystal Oscillator and External Clock—Requirements and Performance
Parameter
Frequency
2.4 GHz and 5 GHz bands:
IEEE 802.11a/b/g/n operation
Frequency tolerance over the
lifetime of the equipment,
Without trimming
including temperaturec
External Frequency
Referenceb c
Crystala
Conditions/Notes
Units
Min.
Typ.
Max.
Min.
Typ.
Max.
–
37.4
–
–
–37.4
–
MHz
–20
–
20
–20
–
20
ppm
Crystal load capacitance
–
–
16
–
–
–
–
pF
ESR
–
–
–
60
–
–
–
Ω
Drive level
External crystal must be able to tolerate
this drive level.
200
–
–
–
–
–
µW
Input impedance
(WRF_XTAL_XON)
Resistive
–
–
–
30k
100k
–
Ω
Capacitive
–
–
7.5
–
–
7.5
pF
WRF_XTAL_XON
Input low level
DC-coupled digital signal
–
–
–
0
–
0.2
V
WRF_XTAL_XON
Input high level
DC-coupled digital signal
–
–
–
1.0
–
1.26
V
WRF_XTAL_XON
input voltage (see Figure 6)
IEEE 802.11a/b/g operation only
–
–
–
400
–
1200
mVp-p
WRF_XTAL_XON
input voltage
(see Figure 6)
IEEE 802.11n AC-coupled analog input
–
–
–
1
–
–
Vp-p
Duty cycle
37.4 MHz clock
–
–
–
40
50
60
%
Phase noised
(IEEE 802.11b/g)
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–129
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–136
dBc/Hz
Phase noised
(IEEE 802.11a)
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–137
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–144
dBc/Hz
Phase noised
(IEEE 802.11n, 2.4 GHz)
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–134
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–141
dBc/Hz
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PRELIMINARY
CYW43907
Table 4. Crystal Oscillator and External Clock—Requirements and Performance (Cont.)
Parameter
Phase noised
(IEEE 802.11n, 5 GHz)
External Frequency
Referenceb c
Crystala
Conditions/Notes
Units
Min.
Typ.
Max.
Min.
Typ.
Max.
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–142
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–149
dBc/Hz
a. (Crystal) Use WRF_XTAL_XON and WRF_XTAL_XOP.
b. See
“External Frequency Reference” for alternative connection methods.
c. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications.
d. Assumes that external clock has a flat phase noise response above 100 kHz.
3.3 External 32.768 kHz Low-Power Oscillator (LPO)
The CYW43907 uses a secondary low frequency clock for low-power-mode timing. Either the internal low-precision LPO or an
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,
voltage, and temperature, which is adequate for some applications. However, one tradeoff caused by this wide LPO tolerance is a
small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in
Table 5.
Table 5. External 32.768 kHz Sleep Clock Specifications
Parameter
LPO Clock
Units
32.768
kHz
Frequency accuracy
±200
ppm
Duty cycle
30–70
%
Nominal input frequency
Input signal amplitude
Signal type
Input impedancea
Clock jitter (during initial start-up)
200–3300
mV, p-p
Square-wave or sine-wave
–
>100 k
1.05 μH,
cap. + board total – ESR < 20 mΩ,
Cout > 1.9 μF, ESL Ttr.
tRC is only relevant for transmitters in Slave mode.
Figure 20 and Table 43 provide the I2S Slave mode receiver timing.
Figure 20. I2S Slave Mode Receiver Timing
T
I2S_SCLK
tHC = 0.35T
V
tLC = 0.35T
tsr = 0.2T
V
H = 2.0V
L = 0.8V
thr = 0
I2S_SDATAI
and I2S_LRCK
T = Clock period.
Tr = Minimum allowed clock period for the transmitter.
T > Tr.
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PRELIMINARY
CYW43907
Table 43. Timing for I2S Transmitters and Receivers
Transmitter
Parameter
Receiver
Lower Limit
Upper Limit
Lower Limit
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Ttr
–
–
–
Ttr
–
Clock period T
Slave Mode:
Clock high, tHC
–
0.35Tr
–
–
–
0.35Tr
Clock low tLC
–
0.35Tr
–
–
–
0.35Tr
Clock rise time, tRC
–
–
0.15Ttr
–
–
–
Transmitter delay, tdtr
–
–
–
0.8T
–
–
Transmitter hold time, thtr
0
–
–
–
–
–
Receiver setup time, tsr
–
–
–
–
–
0.2Tr
Receiver hold time, thr
–
–
–
–
–
0
Table 44 provides the I2S_MCLK specification.
Table 44. I2S_MCLK Specification
Minimum
Typical
Maximum
Unit
Frequency range
Parameter
1
–
40
MHz
Frequency accuracy (with respect to the XTAL frequency)
–
1
–
ppb
Tuning resolution
–
50
–
ppb
Tuning range
–
1000
–
ppm
Tuning step size
–
–
10
ppm
Tuning rate
–
1
–
ppm/ms
Baseband jitter (100 Hz to 40 kHz)
–
–
100
ps rms
Wideband jitter (100 Hz to 1 MHz)
–
–
200
ps rms
Figure 21 shows the I2S frame-level timing.
Figure 21. I2S Frame-Level Timing
1/fs
I2S_LRCLK
Left Channel
Right Channel
I2S_SCLK
1 clock
1
I/O Data
2
1 clock
3
MSB
Document Number: 002-14829 Rev. *L
n– 2 n–1
n
1
LSB
MSB
2
3
n–2 n–1
n
LSB
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CYW43907
17.3 SDIO Interface Timing
17.3.1 SDIO Default-Speed Mode Timing
SDIO default-speed (DS) Mode timing is shown by the combination of Figure 22 and Table 45.
Figure 22. SDIO Bus Timing (DS Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tISU
tIH
Input
Output
tODLY
tODLY
(max)
(min)
Table 45. SDIO Bus Timinga Parameters (DS Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb
Frequency – Data Transfer mode
fPP
0
–
25
MHz
Frequency – Identification mode
fOD
0
–
400
kHz
Clock low time
tWL
10
–
–
ns
Clock high time
tWH
10
–
–
ns
Clock rise time
tTLH
–
–
10
ns
Clock low time
tTHL
–
–
10
ns
Input setup time
tISU
5
–
–
ns
Input hold time
tIH
5
–
–
ns
Output delay time – Data Transfer Mode
tODLY
0
–
14
ns
Output delay time – Identification Mode
tODLY
0
–
50
ns
Inputs: CMD, DAT (referenced to CLK)
Outputs: CMD, DAT (referenced to CLK)
a. Timing is based on CL 40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
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CYW43907
17.3.2 SDIO High-Speed Mode Timing
SDIO high-speed (HS) mode timing is shown by the combination of Figure 23 and Table 46.
Figure 23. SDIO Bus Timing (HS Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tISU
tTLH
tIH
Input
Output
tODLY
tOH
Table 46. SDIO Bus Timinga Parameters (HS Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb
Frequency – Data Transfer Mode
fPP
0
–
50
MHz
Frequency – Identification Mode
fOD
0
–
400
kHz
Clock low time
tWL
7
–
–
ns
Clock high time
tWH
7
–
–
ns
Clock rise time
tTLH
–
–
3
ns
Clock low time
tTHL
–
–
3
ns
Input setup time
tISU
6
–
–
ns
Input hold time
tIH
2
–
–
ns
Inputs: CMD, DAT (referenced to CLK)
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
tODLY
–
–
14
ns
Output hold time
tOH
2.5
–
–
ns
Total system capacitance (each line)
CL
–
–
40
pF
a. Timing is based on CL 40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
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CYW43907
17.3.3 SDIO Bus Timing Specifications in SDR Modes
Clock Timing
SDIO clock timing in the SDR modes is shown by the combination of Figure 24 and Table 47.
Figure 24. SDIO Clock Timing (SDR Modes)
tCLK
SDIO_CLK
tCR
tCF
tCR
Table 47. SDIO Bus Clock Timing Parameters (SDR Modes)
Parameter
Symbol
–
tCLK
–
Clock duty cycle
Minimum
Maximum
Unit
Comments
40
–
ns
SDR12 mode
20
–
ns
SDR25 mode
tCR, tCF
–
0.2 × tCLK
ns
CCARD = 10 pF
–
30
70
%
–
Device Input Timing
SDIO device input timing in the SDR modes is shown by the combination of Figure 25 and Table 48.
Figure 25. SDIO Bus Input Timing (SDR Modes)
SDIO_CLK
tIS
tIH
CMD input
DAT[3:0] input
Table 48. SDIO Bus Input Timing Parameters (SDR Modes)
Symbol
Minimum
Maximum
Unit
tIS
3.00
–
ns
CCARD = 10 pF, VCT = 0.975V
tIH
0.80
–
ns
CCARD = 5 pF, VCT = 0.975V
Document Number: 002-14829 Rev. *L
Comments
Page 75 of 94
PRELIMINARY
CYW43907
Device Output Timing
SDIO device output timing in the SDR modes with clock rates up to 50 MHz is shown by the combination of Figure 26 and Table 49.
Figure 26. SDIO Bus Output Timing (SDR Modes up to 50 MHz)
t C LK
S D IO _ C L K
t O D LY
tOH
C M D in p u t
D A T [3 :0 ] in p u t
Table 49. SDIO Bus Output Timing Parameters (SDR Modes up to 50 MHz)
Symbol
Minimum
Maximum
Unit
Comments
tODLY
–
14.0
ns
tCLK ≥ 20 ns CL= 40 pF
tOH
1.5
–
ns
Hold time at the tODLY (min.) CL= 15 pF
17.4 S/PDIF Interface Timing
The S/PDIF protocol embeds the clock and data within a stream of data using a Biphase Mark Code (BMC).
Figure 27 shows the S/PDIF Interface timing.
Figure 27. S/PDIF Interface Timing
C lo c k
D a ta
1
0
0
1
1
0
1
0
0
1
0
E n c o d e d (B M C )
Figure 28 shows the S/PDIF data output timing.
Figure 28. S/PDIF Data Output Timing
tC LK
S P D IF _ O U T
tC R
Document Number: 002-14829 Rev. *L
tC F
tC R
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CYW43907
Table 50 provides the S/PDIF biphase mark code timing parameters (to be used in conjunction with Figure 28).
Table 50. SPDIF Biphase Mark Code Timing Parameters
Parameter
Symbol
Minimum
Maximum
Unit
–
tCLK
40
–
ns
–
tCR, tCF
–
0.3 × tCLK
ns
–
–
30
70
%
–
Duty cycle
Comments
192 kHz sample rate
Table 51 provides the S/PDIF biphase mark code (BMC) sample rate and receiver clock frequency.
Table 51. SPDIF BMC Sample Rate and Receiver Clock Frequency
Parameter
Sampling frequency
Component clock
frequency
Symbol
Minimum
Maximum
Unit
fS
–
192
kHz
192 kHz sample rate maximum.
fCLOCK
–
25
MHz
Typical is 128 × fS, max is 192 × fS.
Clock is 2× the desired data rate or
2 × 192 kHz × 64 = 24.576 MHz.
Document Number: 002-14829 Rev. *L
Comments
Page 77 of 94
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CYW43907
17.5 SPI Flash Timing
17.5.1 Read-Register Timing
Figure 29 shows the SPI flash extended and quad read-register timing.
Note: Figure 29: All Read Register commands except Read Lock Register are supported. A Read Nonvolatile Configuration Register operation will output data starting from
the least significant byte.
Figure 29. SPI Flash Read-Register Timing
Extended
0
7
8
9
10
11
12
13
14
15
C
LSB
DQ0
Command
MSB
DQ1
LSB
High-Z
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
MSB
Quad
0
1
2
3
C
LSB
DQ[3:0]
Command
MSB
Document Number: 002-14829 Rev. *L
LSB
DOUT
DOUT
DOUT
Don’t care
MSB
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CYW43907
17.5.2 Write-Register Timing
Figure 30 shows the SPI flash extended and quad write-register timing.
Note: Figure 30:
1. All write-register commands except Write Lock Register are supported.
2. The waveform must be extended to 23 for extended write and to five for quad write register timing.
3. A Write Nonvolatile Configuration Register operation requires data being sent starting from the least significant byte.
Figure 30. SPI Flash Write-Register Timing
Extended
0
7
8
9
10
11
12
13
14
15
C
LSB
LSB
DQ0
Command
DIN
MSB
Quad
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
MSB
0
1
2
3
C
LSB
DQ[3:0]
LSB
DIN
Command
MSB
Document Number: 002-14829 Rev. *L
DIN
DIN
MSB
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CYW43907
17.5.3 Memory Fast-Read Timing
Figure 31 shows the SPI flash extended and quad memory fast-read timing.
Note: Figure 31:
1. 24-bit addressing is used, so A[MAX] = A[23] and A[MIN] = A[0].
2. For an extended SPI protocol, Cx = 7 + (A[MAX] + 1).
3. For a quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4.
Figure 31. Memory Fast-Read Timing
Extended
0
7
8
Cx
C
A[MIN]
LSB
Command
DQ0
MSB
DQ1
A[MAX]
LSB
DOUT
High-Z
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
MSB
Dummy Cycles
Quad
0
1
2
Cx
C
LSB
A[MIN]
LSB
DQ[3:0]
Command
MSB
DOUT
A[MAX]
DOUT
MSB
Dummy Cycles
Document Number: 002-14829 Rev. *L
DOUT
Don’t care
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CYW43907
17.5.4 Memory-Write Timing
Figure 32 shows the SPI flash extended and quad memory-write (Page Program) timing.
Note: Figure 32:
1. For an extended SPI protocol, Cx = 7 + (A[MAX] + 1).
2. For a quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4.
Figure 32. Memory-Write Timing
Extended
0
7
8
Cx
C
LSB
A[MIN]
LSB
DIN
Command
DQ0
MSB
Quad
A[MAX]
0
1
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
MSB
2
Cx
C
LSB
A[MIN]
LSB
DQ[3:0]
Command
MSB
Document Number: 002-14829 Rev. *L
DIN
A[MAX]
DIN
DIN
MSB
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17.5.5 SPI Flash Parameters
The combination of Figure 33 and Table 52 provide the SPI flash timing parameters.
Figure 33. SPI Flash Timing Parameters Diagram
T_DVCH
Clock (C)
T_CHDX
Data in (DIN)
(DQ1 in Serial [Extended] mode)
(DQ[3:0] in Quad mode)
T_CLQX
Data out (DOUT)
(DQ0 in Serial [Extended] mode)
(DQ[3:0] in Quad mode)
T_CLQV
Table 52. SPI Flash Timing Parameters
Parameter
Description
Minimum
Maximum
Units
T_DVCH
Data setup time
2
–
ns
T_CHDX
Data hold time
3
–
ns
T_CLQX
Output hold time
1
–
ns
T_CLQV
Output valid time (with a 10 pF load)
–
5
ns
Document Number: 002-14829 Rev. *L
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17.6 USB PHY Electrical Characteristics and Timing
17.6.1 USB 2.0 and USB 1.1 Electrical and Timing Parameters
Table 53 provides electrical and timing parameters for USB 2.0.
Table 53. USB 2.0 Electrical and Timing Parameters
Parameter
Baud rate
Unit interval
Symbol
Minimum
Typical
Maximum
Units
Conditions
BPS
–
480
–
Mbps
–
UI
–
2083
–
ps
–
VHSDI
300
–
–
mV
Receiver – HS Mode
Differential input voltage sensitivity
Input common mode voltage range
VHSCM
Static | VIDP – VIDN |
–50
–
500
mV
–
THSRX
–0.15
–
0.15
UI
–
RIN
40.5
45
49.5
Ω
Output high voltage
VHSOH
360
400
440
mV
Static condition
Output low voltage
VHSOL
–10
0
10
mV
Static condition
Output rise time
THSR
500
–
–
ps
10% to 90%
Output fall time
THSF
500
–
–
ps
90% to 10%
Receiver jitter tolerance
Input impedance
Single ended
Transmitter – HS Mode
THSTX
–0.05
–
0.05
UI
Transmit output jitter
RO
40.5
45
49.5
Ω
Single ended
Chirp-J output voltage (differential)
VCHIRPJ
700
–
1100
mV
HS termination disabled. 1.5
kΩ ± 5% PU resistor
connected.
Chirp-K output voltage (differential)
VCHIRPK
–900
–
–500
mV
HS termination disabled. 1.5
kΩ ± 5% PU resistor
connected.
Transmitter jitter
Output impedance
Note: Refer to Section 7 of the USB 2.0 specification for more information on the receiver eye diagram template.
Document Number: 002-14829 Rev. *L
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Table 54 provides electrical and timing parameters for USB 1.1.
Table 54. USB 1.1 FS/LS Electrical and Timing Parameters a
Parameter
Symbol
Value
Minimum
Typical
Maximum
Unit
Condition
Baud Rate
FS
BPS
–
12
–
Mbps
–
LS
BPS
–
1.5
–
Mbps
–
Unit Interval
FS
UI
–
83.33
–
ns
–
LS
UI
–
666.67
–
ns
–
Differential input sensitivity
VFSDI
200
–
–
mV
Input common mode range
Receiver
Static |VIDP – VIDN |
VFSCM
0.8
–
2.5
V
–
Input impedance
ZIN
300
–
–
kΩ
–
Input high voltage
VFSIH
2.0
–
–
V
Static
Input low voltage
VFSIL
–
–
0.8
V
Static
Output high voltage
VFSOH
2.8
–
–
V
Static
Output low voltage
VFSOL
–
–
0.3
V
Static
Output rise/fall time for fast speed
TR,TF
4
–
20
ns
10 to 90%
TR,TF
75
–
300
ns
10 to 90%
–2
–
2
ns
Transmitter
Output rise/fall time for low speed
Fast-speed jitter
Low-speed jitter
Output impedance
FSTX
LSTX
–25
–
25
ns
–
RO
28
–
44
Ω
Single ended
–
a. For more details, refer to the USB 1.1 Specification.
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17.6.2 USB 2.0 Timing Diagrams
Figure 34 shows the important timing parameters associated with a post-reset transition to HS operation.
Figure 34. USB 2.0 Bus Reset to HS Mode Operation
40 to 60 μs
< 100 μs
DP
100 to 500 μs
Idle
HS Data
HighSpeed
Chirp
DM
Device
K-Chirp
Idle
3 to 3.125 ms
HS Data
> 1.0 ms
100 to
875 μs
< 7 ms
> 10 ms
Start of
Reset
Start of Host
(Hub) Chirp
Device Goes
into FullSpeed Mode
End of Host
(Hub) Chirp
End of
Reset
Device Tests for
Single-Ended Zero
(SE0) State
Figure 35 shows the USB 2.0 HS Mode transmit timing.
Figure 35. USB 2.0 HS Mode Transmit Timing
96 bits
DP/DM
Latency = 42 bits
CLK60
TXDATA
PID
B0
B1
TXVALID
TXREADY
XVERSEL
00
OPMODE
00
TERMSEL
0
TX driver is enabled here.
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Figure 36 shows the USB 2.0 HS Mode receive timing.
Figure 36. USB 2.0 HS Mode Receive Timing
Latency = 72 bits
64 bits
DP/DM
CLK60
RXACTIVE
RXVALID
B0
RXDATA
XVERSEL
00
OPMODE
00
TERMSEL
0
Document Number: 002-14829 Rev. *L
B1
B2
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18. Power-Up Sequence and Timing
18.1 Sequencing of Reset and Regulator Control Signals
The CYW43907 has two signals that allow the host to control power consumption by enabling or disabling the internal regulator blocks.
These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various
operational states (see Figure 37 and Figure 38). The timing values indicated are minimum required values; longer delays are also
acceptable.
18.1.1 Description of Control Signals
■
REG_ON: Used by the PMU to power-up the CYW43907. It controls the internal CYW43907 regulators. When this pin is high, the
regulators are enabled and the device is out of reset. When this pin is low the regulators are disabled.
HIB_REG_ON_IN: Used by the Hibernation (HIB) block to power up the internal CYW43907 regulators. If the HIB_REG_ON_IN
pin is low, the regulators are disabled. For the HIB_REG_ON_IN pin to work as designed, HIB_REG_ON_OUT must be connected
to REG_ON.
Notes:
1. The CYW43907 has an internal POR circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO
have both passed the POR threshold.
2. The 10%–90% VBAT rise time should not be faster than 40 microseconds. VBAT should be up before or at the same time as
VDDIO. VDDIO should not be present first or be held high before VBAT is high.
■
18.1.2 Control Signal Timing Diagrams
Figure 37. REG_ON = HIGH, No HIB_REG_ON_OUT Connection to REG_ON
3 2 .6 7 8 k H z
S le e p C lo c k
VBAT
V D D IO
> 2 S le e p C y c le s
R EG _O N
H IB _ R E G _ O N _ IN
Figure 38. HIB_REG_ON_IN = HIGH, HIB_REG_ON_OUT Connected to REG_ON
32.678 kHz
Sleep Clock
VBAT
VDDIO
> 2 Sleep Cycles
HIB_REG_ON_IN
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19. Thermal Information
19.1 Package Thermal Characteristics
Table 55. Package Thermal Characteristicsa
Characteristic
WLCSP
JA (°C/W) (value in still air)
JB (°C/W)
JC (°C/W)
33.74
JT (°C/W)
JB (°C/W)
5.86
11.52
Maximum Junction Temperature Tj (°C)
116.7
Maximum power dissipation (W)
1.38
5.5
1.74
a. No heat sink, TA = 70°C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD51–7. Air velocity is 0 m/s.
19.2 Junction Temperature Estimation and PSIJT Versus THETAJC
Package thermal characterization parameter PSI–JT (JT) yields a better estimation of actual junction temperature (TJ) versus using
the junction-to-case thermal resistance parameter Theta–JC (JC). The reason for this is that JC assumes that all the power is
dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom
and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation
for calculating the device junction temperature is:
TJ = TT + P x JT
Where:
■
TJ = Junction temperature at steady-state condition (°C)
■
TT = Package case top center temperature at steady-state condition (°C)
■
P = Device power dissipation (Watts)
■
JT = Package thermal characteristics; no airflow (°C/W)
19.3 Environmental Characteristics
For environmental characteristics data, see Table 16: “Environmental Ratings”.
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CYW43907
20. Mechanical Information
Figure 39. WLCSP Package
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CYW43907
21. Ordering Information
Package
Description
Operating Ambient
Temperature
4.583 mm x 5.533 mm, 316-pin WLCSP
–
–30°C to +85°C
Part Number
CYW43907KWBG
Note: Add a "T" suffix to the part number to order in Tape and Reel"
22. Additional Information
22.1 Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined upon first use. For a more complete list of acronyms and other terms used in
Cypress documents, go to: http://www.cypress.com/glossary.
.
Term
Term
Description
Description
AES
Advanced Encryption Standard
LCU
AES-CTR
Advanced Encryption Standard-Counter Mode
LDO
low drop-out
AHB
advanced high-performance bus
MIB
Management Information Base
ALU
Arithmetic logic unit
OFDM
Orthogonal Frequency Division Multiplexing
APB
advanced peripheral bus
PDM
pulse density modulation
APU
audio processing unit
PLL
phase locked loop
CBC-MAC
Cipher Block Chaining Message Authentication
Code
POR
power-on reset
CCK
Complementary Code Keying
CCM
Counter with Cipher block chaining Message
authentication code
CSC
Cypress Serial Control
CTS
Clear to Send
DMA
direct memory access
DSSS
Direct Sequence Spread Spectrum
EBI
external bus interface
HCI
Host Control Interface
HV
high voltage
IDC
initial digital calibration
IRQ
interrupt request
JTAG
Joint Test Action Group
Document Number: 002-14829 Rev. *L
link control unit
RC oscillator A resistor-capacitor oscillator is a circuit
composed of an amplifier, which provides the
output signal, and a resistor-capacitor network,
which controls the frequency of the signal.
RMII
Reduced Media Independent Interface
RTS
Request to Send
RX/TX
receive, transmit
SDIO
Secure Digital Input Output
SPI
serial peripheral interface
SWD
serial wire debug
TXOP
Transmit Opportunity
UART
universal asynchronous receiver/transmitter
WD
watchdog
WEP
wired equivalent privacy
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22.2 References
The references in this section may be used in conjunction with this document.
Note: Cypress provides customer access to technical documentation and software through its Customer Support Portal (CSP) and
Downloads and Support site (see IoT Resources).
Document (or Item) Name
1. USB 2.0 specification
Source
www.usb.org
22.3 IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website
(https://community.cypress.com/)
22.4 Errata
1. The RTC block has been deprecated from this datasheet in revision *A and later. This block is used by Cypress for internal
testing/validation/verification and is not intended for customers to use.
2. The details of the SPI hardware blocks were missing from this datasheet till revision *H. Revision *I adds this in section 5.12.SPI
Note that the SPI hardware blocks can only support a hold time of 25 ns and a fixed SPI mode (CPHA=0, CPOL = 0). For slaves
that require higher hold times or a different mode a bit banging based SPI driver is recommended.
3. The clock for the SPI Flash block needs to be constrained to ~26.67MHz for reliable operation at high operating temperatures.
The throughput of the SPI Flash block is therefore restricted to ~13 MBps for Quad mode and ~3 MBps for single mode. (Added
in Rev *J).
4. USB Host and USB Device functionality require the WLAN domain to be powered on to ensure that USB transactions are completed successfully. Note that though WLAN domain is powered on the radios can be clock gated.
5. The SDIO device mode has been deprecated from this datasheet in Rev *F and beyond. Cypress's WICED® SDK does not provide the drivers for the SDIO device mode functionality. SDIO device mode block is used by Cypress for internal testing/validation/verification and is not intended for customers to use.
Document Number: 002-14829 Rev. *L
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Document History Page
Document Title: CYW43907 WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor
Document Number: 002-14829
Revision
ECN
Submission
Date
Description of Change
**
-
11/03/2014
43907-DS100-R
Initial release
*A
-
03/10/2015
43907-DS101-R
See the revision history of the applicable release.
*B
-
10/15/2015
43907-DS102-R
Updated:
Figure 3: “Typical Power Topology (Page 1 of 2)”.
Table 3: “Crystal Oscillator and External Clock — Requirements and Performance”
“Transmit Path”.
Figure 14: “Radio Functional Block Diagram”.
“Calibration”.
Table 17: “Strapping Options”.
Table 23: “ESD Specifications”.
Table 24: “Recommended Operating Conditions and DC Characteristics”.
“Introduction”.
Table 31: “WLAN 2.4 GHz Transmitter Performance Specifications”.
Table 32: “WLAN 5 GHz Receiver Performance Specifications”.
Table 33: “WLAN 5 GHz Transmitter Performance Specifications”.
Section 18: “System Power Consumption”
Table 56: “SDIO Bus Input Timing Parameters (SDR Modes)”.
Table 64: “Package Thermal Characteristics”.
*C
-
11/03/2015
43907-DS103-R
Updated:
Table 21: “Absolute Maximum Ratings”.
Table 24: “Recommended Operating Conditions and DC Characteristics”
Table 30: “WLAN 2.4 GHz Receiver Performance Specifications”
Table 31: “WLAN 2.4 GHz Transmitter Performance Specifications”.
Table 32: “WLAN 5 GHz Receiver Performance Specifications”.
Table 33: “WLAN 5 GHz Transmitter Performance Specifications”.
*D
-
03/12/2016
43907-DS104-R
Updated:
General edits
*E
5525655
11/17/2016
Added Cypress Part Numbering Scheme and Mapping Table
Updated to Cypress template.
*F
5553590
01/17/2017
Updated: Two SPI master interfaces with operation up to 24 MHz. in page 5.
*G
5730057
05/10/2017
Updated Cypress Logo and Copyright.
07/14/2017
Replaced BSC to CSC throughout the datasheet.
Updated Figure 1, Figure 2, Table 4, Table 13.
Removed 3.3 Frequency Selection.
Updated 5.9 SPI Flash:
- Replaced Quad I/O, which Provides increased throughput to 40 MB/s to Increased
Throughput to 40 MBps in Quad-mode or upto 10 MBps in single Mode.
Added Footnote for Table 13.
Updated Contents in the Table 28, Table 29, Table 30.
Updated Table 17 on page 49.
*H
5812137
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CYW43907
Document Title: CYW43907 WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor
Document Number: 002-14829
Revision
*I
*J
ECN
5954959
5999198
Submission
Date
Description of Change
11/02/2017
Added SPI section.
Added a Note: “The SPI blocks can be re-purposed as I2C, however the WICED SDK
does not support this. Certain I2C features may be unavailable when using the SPI blocks
as I2C. Therefore Cypress recommends using the the CSC blocks or a bit banging I2C
driver over GPIOs instead.” below Table 10 on page 35.
Added a 22.4.Errata section.
Replaced BCS to CSC throughout the document.
12/22/2017
Updated Revisions details in the section 22.4.Errata.
Updated Note “Note that the clock needs to be constrained to ~26.67MHz for reliable
operation at high operating temperatures. The throughput of the SPI Flash block is
therefore restricted to ~13 MBps for Quad mode and ~3 MBps for single mode” for
5.9.SPI Flash.
Replaced “ARM Cortex-R4 clocked at 160 MHz (in 1× mode) or up to 320 MHz (in 2×
mode)” with “The APPS ARM Cortex-R4 core can be clocked at 60 MHz, 80 MHz, 120
MHz, 160 MHz or 320 MHz” in the Features section.
Updated the URL “www.usb.org” to “http://www.usb.org/developers/docs/usb20_docs/
usb_20_020718.zip”.
Updated Figure 37 on page 87 and Figure 38 on page 87.
Removed RTC from Figure 1 on page 2.
Removed Proprietary Protocols from Standards Compliance section.
Added "Note: Add a "T" suffix to the part number to order in Tape and Reel" below
Ordering Information table.
Updated section SDIO 3.0 - Host Mode.
Interchanged the description of GPIO_7 and GPIO_11 in Table 11.
Updated Table 26.
Updated the link for USB 2.0 and USB 1.1 as “http://www.usb.org/developers/docs/
usb20_docs/usb_20_020718.zip”.
Added Acronym table in Acronyms and Abbreviations section.
Added in the 22.4.Errata section: 4. USB Host and USB Device functionality require the
WLAN domain to be powered on to ensure that USB transactions are completed
successfully. Note that though WLAN domain is powered on the radios can be clock
gated.
5. The SDIO device mode has been deprecated from this datasheet in Rev *K and
beyond. Cypress's WICED SDK does not provide the drivers for the SDIO device mode
functionality. SDIO device mode block is used by Cypress for internal testing/validation/
verification and is not intended for customers to use”.
*K
6279518
08/16/2018
*L
7109428
03/23/2021
Document Number: 002-14829 Rev. *L
Removed Cypress Part Numbering Scheme.
Updated Features and IEEE 802.11™ a/b/g/n PHY.
Page 93 of 94
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CYW43907
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2014-2021. This document is the property of Cypress Semiconductor Corporation, and Infineon Technologies company, and its affiliates (“Cypress”). This
document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and
other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the
Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in
source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form
externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction,
modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively,
“Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security
Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the
extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of
any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes.
It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk
Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and
other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the HighRisk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any
use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, including its affiliates, and its directors, officers, employees, agents, distributors, and
assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from
any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the
limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance
written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, and combinations thereof, WICED, ModusToolBox, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress or a subsidiary
of Cypress in the United States or in other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-14829 Rev. *L
Revised March 23, 2021
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