C9630CY

APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications Product Features • • • • • • • • • • • • • Supports PentiumIII, K6, and Socket 7 CPU’s Designed to SiS630 & SiS540 Chipset requirements 3 copies of CPU Clock (CPU[0:2] ) 14 copies of SDRAM Clock (SDRAM[0:13] 7 copies of PCI Clock 2 REF(0:1) Clock outputs 1 USB Clock (Non SSC), 48MHz 1 programmable SIO (Non SSC), 24/48MHz 133 MHz SDRAM support Cypress Spread Spectrum for best EMI reduction SMBus Support with read back capabilities. Dial-a-Frequency™ Feature 48 Pin SSOP package. Frequency Table (MHz) FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 66.6 100.0 150.0 133.3 66.8 100.0 100.0 133.3 66.9 97.2 70.0 95.0 95.0 112.0 97.0 96.0 SDRAM 100.0 100.0 100.0 100.0 133.6 133.3 150.0 133.3 66.9 97.2 105.0 95.0 126.7 112.0 129.3 96.0 PCICLK 33.3 33.3 37.5 33.3 33.4 33.3 37.5 33.3 33.4 32.4 35.0 31.6 31.6 37.3 32.4 32.0 Block Diagram 30pF Xin 300K 1 30pF VDD Xout 1 REF0/S3 VDD REF1 Table 1 Note: *Programmable to 48 MHz via SMBus Pin Configuration VDD S3 / REF0 VSS XIN XOUT VDD S1/ PCI0 S2 / PCI1 PCI2 VSS PCI3 PCI4 PCI5 PCI6 VDD VSS SDRAM0 SDRAM1 VDD SDRAM2 SDRAM3 VSS SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1 VDDC CPU0 CPU1 VSS CPU2 VDD SDRAM13 SDRAM12 VSS SDRAM11 SDRAM10 VDD SDRAM9 SDRAM8 VSS SDRAM7 SDRAM6 VDD SDRAM5 SDRAM4 VDD S0 / 48MHz 24_48MHz VDDcpu Rin cpu 3 CPU(0:2) VDD s3 s2 s1 s0 DATA SCLK sdata sclk PLL1 sdram 14 VDD 5 pci 1 VDD PCI0/S1 PCI(2:6) SDRAM(0:13) VDD 1 PCI1/S2 Rin i2c-clk i2c-data 48 1 VDD VDD 1 48MHz/S0 24 or 48 PLL2 24_48MHz Fig.1 Fig.2 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07035 Rev. ** 05/02/2001 Page 1 of 18 APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications Pin Description PIN No. 2 Pin Name S3/ REF0 PWR VDD I/O I/O Description 3.3V 14.318 MHz clock output. This Is a power on bi-directional pin. During power up, this pin is an input “S3” for setting the CPU frequency (see table1, page 1) (see app note, page 5). When the power reaches the rail, this pin becomes a buffered output of the signal applied at Xin (typically 14.318 MHz). This pin is a buffered output of the signal applied at Xin (typically 14.318) 14.318MHz Crystal input 14.318MHz Crystal output This is a power on bi-directional pin. During power up, this pin is an input “S1” for setting the CPU frequency (see table1, page 1) (see app not, page 5). When the power reaches the rail, this pin becomes a PCI0 clock output. This is a power on bi-directional pin. During power up, this pin is an input “S2” for setting the CPU frequency (see table1, page 1) (see app not, page 5). When the power reaches the rail, this pin becomes a PCI1 clock output. 3.3V PCI clock outputs. This pin is programmable to 24MHz or 48 MHz clock output through SMBus. It defaults to 24MHz at power up. This is a power on bi-directional pin. During power up, this pin is an input “S0” for setting the CPU frequency (see table1, page 1) (see app note, page 5). When the power reaches the rail, this pin becomes a 48MHz clock output. This clock conforms to the USB spec. of +167ppm. SMBus compatible SDATA input. Has an internal pull-up (>100KΩ) SMBus compatible SCLK input. Has an internal pull-up (>100KΩ) 3.3V SDRAM clock outputs. See table1, p.1 for frequency selection. 48 4 5 7 REF1 XIN XOUT S1/ PCI0* VDD VDD VDD VDD O I O I/O 8 S2/ PCI1* VDD I/O 9,11,12,13, 14 25 26 PCI(2:6) 24/48MHz S0 / 48MHz* VDD VDD VDD O O I/O 28 29 17,18,20,21, 28,29,31,32, 34,35,37,38, 40,41 43,45,46 1,6,15,19, 27, 30,36,42 47 3,10,16,22, 33,39,44 SDATA SCLK SDRAM(0:13) VDD VDD VDD I I O CPU(0:2) VDD VDDC VSS VDDC - O 2.5V or 3.3V Host bus clock outputs. See table 1, page 1 for frequency selection. 3.3V Common Power Supply 2.5V or 3.3V Power Supply’s for CPU (0:2) clock outputs. Common Ground pin. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. *Note: These pins have pulldown resistors, typical value 250 Ω. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07035 Rev. ** 05/02/2001 Page 2 of 18 APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications Device Clock Phase Relationships Condition 1: CPU Frequency = SDRAM Frequency Applicable to the follow ing selections: S(4:0) = 00001, 00111, 01000, 01001, 01011, 01101, 01111, 10001, 10111,11010, 11011, 11100, 11101, 11110, 11111 Internal VCO SDRAM to CPU or CPU to SDRAM TSkew 3 Condition 2: CPU Frequency = 1.5 X SDRAM Frequency or SDRAM Frequency = 1.5 X CPU Frequency Applicable to the follow ing selections: S(4:0) = 00000, 00010, 00110, 01010, 10000, 10010, 10101 Internal VCO SDRAM to CPU or CPU to SDRAM TSkew 3 Condition 3: CPU Frequency = 1.3 X SDRAM Frequency or SDRAM Frequency = 1.3 X CPU Frequency Applicable to the follow ing selections: S(4:0) = 00011, 00101, 01100, 01110, 10011, 10100, 10110, 11000, 11001 Internal VCO SDRAM to CPU or CPU to SDRAM TSkew 3 Condition 4: SDRAM Frequency = 2 X CPU Frequency Applicable to the follow ing selection: S(4:0) = 00100 Internal VCO SDRAM CPU TSkew 3 Fig.3 Frequency Smooth Switching Groups Group 2 3 S(4:0) 00000, 00011, 00110, 01010, 10000, 10101 00100, 00101, 01000, 01001, 01011, 01100, 01110, 01111, 10011, 10100, 10110, 11000, 11001 Table 2 Table 2 above describes 3 different groups of frequencies. Within the same group, frequency may be switched through SMBus byte 0 without causing any glitching or clock discontinuity at the CPU(0:2) outputs, therefore allowing frequency smooth switching of the clock. Switching frequency from one group to another is permitted but will cause the CPU(0:2) clocks to jump immediately to the next frequency. (non smooth switching.). Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07035 Rev. ** 05/02/2001 Page 3 of 18 APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications Power on Bi-Directional Pins Power Up Condition: Pins 2,7,8,and 26 are Power up bi-directional pins used for selecting the host frequency in page 1, table 1. During power-up of the device, these pins are in input mode (see Fig 4, below), therefore; they are considered input select pins internal to the IC. After a settling time, the selection data is latch into the internal control register and these pins become a clock outputs. ower Supply amp VDD Rail REF0 / S3 PCI0 / S1 PCI1 / S2 48MHZ / S0 Hi-Z Input - Toggle Outputs Select data is latched into register, then pin becomease ref clock output signal. Fig.4 VDD Strapping Resistor Options: The power up bi-directional pins have a large value pulldown each (250KΩ), therefore, a selection “0” is the default. If the system uses a slow power supply (over 5mS settling time), then it is recommended to use an external Pull-Down (Rdn) in order to insure a Low selection. In this case, the designer may choose one of two configurations, see Fig.5A and B. Fig. 5A represents an additional pull down resistor Rdn = 50KΩ connected from the pin to the ground plane, which allows a faster pull to a low level. If a selection “1” is desired, then a jumper is placed on JP1 to a Rup = 10KΩ resistor as implemented as shown in Fig.5A. Please note the selection resistors (Rup and Rdn) are placed before the Damping resistor (Rd) close to the pin. Fig. 5B represent a single resistor 10KΩ connected to a 3-way jumper, JP2. When a “1” selection is desired, a jumper is placed between leads1 and 3. When a “0” selection is desired, a jumper is placed between leads 3 and 2. 10K JP1 IMIC9630 Bidirectional Rd 50K Load Fig.5A VDD 1 JP2 2 3 IMIC9630 Bidirectional 10K Load Rd Fig.5B Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07035 Rev. ** 05/02/2001 Page 4 of 18 APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications 2-Wire SMBus Control Interface The 2-wire control interface implements a read/write slave only interface according to SMBus specification (IC12, 1996). The device can be read back by using standard SMBus command bytes. Sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported. During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode. R/W# = 0 in write mode. A maximum of 10 bytes of data may be written/Read Data is transferred MSB first at a max rate of 100kbits/S.The device will not respond to any other control interface conditions. In the Write mode (See fig6A, p.9), the clock gen. acknowledges Address Byte, D2, then receives two additional bytes: 1) “Command Code “ byte, and 2) “Byte Count” byte. Must be programmed to FF for correct operation. Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged. Subsequently, the below-described sequence (Byte 0, Byte 1, Byte2,) will be valid and acknowledged. In the Read Mode (See fig6B, p.9), the clock gen. acknowledges Address D3, and immediately transmits data starting with Byte count, then Byte 0, 1, 2, ... After each transmitted byte, this device waits for an acknowledge before transmitting the next byte. Serial Control Registers NOTE: Power up conditions for each bit are listed in the “@Pup” column. Byte 0: Frequency, Function Select Register Bit @Pup Pin# Description, see page 8 for SSCG description. 7 0 n/a S4 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1 6 0 n/a S2 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1 5 0 n/a S1 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1 4 0 n/a S0 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1 3 0 n/a 0 = frequency selected by hardware, pins 1 = frequency selection via SMBus byte0. 2,7,8,26 bits 4,5,6,2,7 2 0 n/a S3 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1 1 0 n/a 0 = Spread Spectrum disabled 1 = Spread spectrum enabled 0 0 n/a 0 = Running 1 = Test mode. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07035 Rev. ** 05/02/2001 Page 5 of 18 APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) S4 Bit7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S3 Bit2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 Bit6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 Bit5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 Bit4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description CPU 66.6 100.0 150.0 133.3 66.8 100.0 100.0 133.3 66.8 97.0 70.0 95.0 95.0 112.0 97.0 96.2 66.8 100.2 166.0 100.2 75.0 83.3 105.0 133.6 110.3 115.0 120.0 138.0 140.0 145.0 147.5 160.0 SDRAM 100.0 100.0 100.0 100.0 133.6 133.3 150.0 133.3 66.8 97.0 105.0 95.0 126.7 112.0 129.3 96.2 100.2 100.2 110.7 133.6 100.0 125.0 140.0 133.6 147.0 153.3 120.0 138.0 140.0 145.0 147.5 160.0 Table 3. PCI 33.3 33.3 37.5 33.3 33.4 33.3 37.5 33.3 33.4 32.3 35.0 31.7 31.7 37.3 32.3 32.1 33.4 33.4 33.3 33.4 37.5 31.3 35.0 33.4 36.8 38.3 30.0 34.5 35.0 36.3 29.5 32 Spread Spectrum, MBS0 = MBS1 = 1, SSTS = 1 0 to –0.5% 0 to –0.5% +/- 0.25% 0 to –0.5% 0 to –0.5% 0 to –0.5% +/- 0.25% 0 to –0.5% +/- 0.25% 0 to –0.5% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% 0 to –0.5% 0 to –0.5% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% TEST Function Table: Applicable only when bit0=1 in Byte0. CPU (0:2) = Xin / 3 PCI (0:6) = Xin / 6 SDRAM (0:13) = Xin / 2 REF(0,1) = Xin 48MHz = Xin 24_48MHz = Xin / 2 Test Clock should be applied at Xin pin. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07035 Rev. ** 05/02/2001 Page 6 of 18 APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications Serial Control Registers (Cont.) Byte 1: CPU Clock Register (1 = enable, 0 = Stopped) Bit @Pup Pin# Description 7 1 Selects Frequency at pin 25 1 = selects 24MHz (default) 0 = selects 48MHz 6 1 SSTS, See Table 4, p 11 5 1 Reserved for IMI test^ 4 1 Reserved for IMI test^ 3 1 43 CPU2 enable/Stopped 2 1 45 CPU1 enable/Stopped 1 1 46 CPU0 enable/Stopped 0 1 Reserved for IMI test^ Byte 2: PCI Clock Register (1 = enable, 0 = Stopped) Bit @Pup Pin# Description 7 1 Reserved 6 1 14 PCI6 enable/Stopped 5 1 13 PCI5 enable/Stopped 4 1 12 PCI4 enable/Stopped 3 1 11 PCI3 enable/Stopped 2 1 9 PCI2 enable/Stopped 1 1 8 PCI1 enable/Stopped 0 1 7 PCI0 enable/Stopped Byte 3: SDRAM Clock Register (1 = enable, 0 = Stopped) Bit @Pup Pin# Description 7 1 32 SDRAM7 enable/Stopped 6 1 31 SDRAM6 enable/Stopped 5 1 29 SDRAM5 enable/Stopped 4 1 28 SDRAM4 enable/Stopped 3 1 21 SDRAM3 enable/Stopped 2 1 20 SDRAM2 enable/Stopped 1 1 18 SDRAM1 enable/Stopped 0 1 17 SDRAM0 enable/Stopped Byte 4: Additional SDRAM Clock Register (1=enable, 0=Stopped) Bit @Pup Pin# Description 7 1 25 24_48MHz enable/Stopped 6 1 26 48 MHz enable/Stopped 5 1 41 SDRAM13 enable/Stopped 4 1 40 SDRAM12 enable/Stopped 3 1 38 SDRAM11 enable/Stopped 2 1 37 SDRAM10 enable/Stopped 1 1 35 SDRAM9 enable/Stopped 0 1 34 SDRAM8 enable/Stopped Byte 5: Peripheral Control (1 = enable, 0 = Stopped) Bit @Pup Pin# Description 7 1 MBS1, See table 4, p. 11 for Spread Spectrum 6 1 MBS0, See table 4, p.11 for Spread Spectrum 5 1 S3# * 4 1 S2# * 3 1 S1# * 2 1 S0# * 1 1 48 REF1 enable/Stopped 0 1 2 REF0 enable/Stopped *Inverted read back of hardware settings. Byte 6: Reserved Register (1 = enable, 0 = Stopped) Bit @Pup Pin# Description 7 0 Reserved for IMI test^ 6 0 5 0 4 0 Reserved for IMI test^ 3 0 Reserved for IMI test 2 1 Reserved for IMI test 1 0 N9, MSB 0 0 N8 Byte 7: Dial-a-Frequency® N Register (1 = enable, 0 = Stopped) Bit @Pup Pin# Description 7 0 N7 6 0 N6 5 0 N5 4 0 N4 3 0 N3 2 0 N2 1 0 N1 0 0 N0, LSB Byte 8: Dial-a-Frequency® R Register (1 = enable, 0 = Stopped) Bit @Pup Pin# Description 7 0 R6, MSB 6 0 R5 5 0 R4 4 0 R3 3 0 R2 2 0 R1 1 0 R0, LSB 0 0 1 = Enable SMBus N and R Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07035 Rev. ** 05/02/2001 Page 7 of 18 APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications Dial-a-Frequency™ Feature SMBus Dial-a-frequency feature is available in this device via byte7, and byte 8 These bytes allow the user to enter the N and R values that will allow them to program any CPU frequency desired following the formula: ™ Fcpu = P× N R Where N and R values are programmed in binary into byte 7 for N and byte 8 for R. See table below for min and max allowed values. R 42 43 44 45 46 47 48 49 50 51 Min N 44 45 46 47 48 49 50 51 52 53 Max N 87 90 92 94 96 98 100 102 104 107 P is a large value PLL constant that depends on the last frequency selection achieved through the hardware selectors (S3, S2, S1, S0) or through the software selectors (byte0 , bits 7,6,5,4,2). P value may be determined from the following table: S(4:0) 00001, 00010, 00111, 01101, 10001, 10010, 10111, 11010, 11011, 11100, 11101, 11110, 11111 00000, 00011, 00110, 01010, 10000, 10101 00100, 00101, 01000, 01001, 01011, 01100, 01110, 01111, 10011, 10100, 10110, 11000, 11001 6 P 96016000 64010667 48008000 Therefore, if a 145MHz (use 145x10 )value is desired, then we should apply 145 into equation 1, and start by choosing R to be 47 (assume the last frequency selection has the value P = 96016000): 145X10 = 96016000 X N 47 6 => N = 70.97775371 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07035 Rev. ** 05/02/2001 Page 8 of 18 APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications Dial-a-Frequency™ Feature (Cont.) Since this N number must be entered in Binary, it can only be an integer, so it must be rounded up or down. Here we can rounded it up to 71, which will give us an exact CPU frequency of: Fcpu = 96016000 X N = 145.045 MHz (accuracy + 310 ppm) 47 If the above frequency is not accurate enough, then you must choose another R value and start from the beginning. For example choose R = 49 and this will yield an N = 73.99808365, which is rounded to 74. If the 74 is applied in the formula 1, then Fcpu = 145.0038 MHz (accuracy + 26 ppm). Other R values within the above limits may also be evaluated. SMBus Communication Waveform IMI Device Master Device SDATA MSB LSB ACK ACK BYTE COUNT (Don’t Care) ACK BYTE 0 (Valid) ACK BYTE N (Valid) ACK 1 1 0 1 0 0 1 0 COMMAND BYTE (Don’t Care) SCLK 8 START IMI Device 8 8 8 STOP CONDITION Fig.6a (WRITE) ACK BYTE COUNT BYTE 0 ACK (Valid) (Valid) ACK (Valid) BYTE1 ACK BYTE N NO ACK (Valid) Master Device SDATA 1 1 0 1 0 0 1 1 MSB LSB SCLK START CONDITION 8 8 8 8 STOP CONDITION Fig.6b (READ) Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07035 Rev. ** 05/02/2001 Page 9 of 18 APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications SMBus Test Circuitry + 5V 2.2 K Device under Test SDATA DATAIN + 5V 2.2 K + 5V 2.2 K SCLK DATAOUT CLOCK Fig.7 Note: Buffer is 7407 with VCC @ 5.0 V Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from (Fig.8A) or around the center (Fig.8B) of its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). In this device, Spread Spectrum is enabled by setting I²C byte0, bit1 = 1. The default of the device at power up keeps the Spread Spectrum disabled, it is therefore, important to have I²C accessibility to turn-on the Spread Spectrum function. Once the Spread Spectrum is enabled, the spread bandwidth option is selected by MBS(0:1) in I²C byte 5, bit6 and bit 7, and SSTS Byte1, Bit6 following table 4 below. In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by ½ of the total spread %. (eg.: assuming the center frequency is 100MHz in non-spread mode; when down spread of –0.5% is enabled, the center frequency shifts to 99.75MHz.). Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07035 Rev. ** 05/02/2001 Page 10 of 18 APPROVED PRODUCT C9630 PC133 Clock Generator for SiS630/Pentium®III & SiS540/Socket7 Applications Spread Spectrum Clock Generation (SSCG) (Cont.) In Center Spread mode, the Center frequency remains the same as in the non-spread mode. Down Spread Center Spread Fig.8A Fig.8B Spread Spectrum Selection Table SSTS 0 0 0 0 1 1 1 1 MBS 1 0 0 1 1 0 0 1 1 MBS 0 0 1 0 1 0 1 0 1 Table 4 Spread% - 0.5 +/- 0.125 +/- 0.5 +/- 0.25 -0.5 +/- 0.125 +/- 0.5 See table 3, (default) Maximum Ratings Maximum Input Voltage Relative to VSS: VSS - 0.3V Maximum Input Voltage Relative to VDD: VDD + 0.3V Storage Temperature: Operating Temperature: Maximum ESD protection Maximum Power Supply: -65ºC to + 150ºC 0ºC to +70ºC 2KV 5.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS