C9827H

Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer Product Features • • • Supports Pentium 4 Type CPUs 3.3 Volt Power Supply 10 Copies of PCI Clocks ® • • • • • • 3 Differential CPU Clocks SMBus Support with Read-back Capabilities Spread Spectrum EMI Reduction Dial-a-Frequency™ Features Dial-a-dB™ Features 56 Pin SSOP and TSSOP Package Frequency Table S2 1 1 1 1 0 0 0 0 M M M M S1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 CPU (0:2) 66M 100M 200M 133M 66M 100M 200M 133M Hi-Z TCLK/2 150M 166.6M 3V66 66M 66M 66M 66M 66M 66M 66M 66M Hi-Z TCLK/4 50M 55.5M 66BUFF(0:2)/ 3V66(0:4) 66IN 66IN 66IN 66IN 66M 66M 66M 66M Hi-Z TCLK/4 50M 55.5M 66IN/ 3V66-5 66MHz clock input 66MHz clock input 66MHz clock input 66MHZ clock input 66M 66M 66M 66M Hi-Z TCLK/4 50M 55.5M PCI_F PCI 66IN/2 66IN/2 66IN/2 66IN/2 33 M 33 M 33 M 33 M Hi-Z TCLK/8 25M 27.7M REF 14.318M 14.318M 14.318M 14.318M 14.318M 14.318M 14.318M 14.318M Hi-Z TCLK 14.318M 14.318M USB/ DOT 48M 48M 48M 48M 48M 48M 48M 48M Hi-Z TCLK/2 48M 48M Note: TCLK is a test clock over driven on the XTAL_IN input during test mode. M= driven to a level between 1.0 and 1.8 Volts If the S2 pin is at a M level during power up, a 0 state will be latched into the devices internal state register. Block Diagram XIN XOUT PLL1 CPU_STP# IREF VSSIREF S(0:2) MULT0 VTT_PG# PCI_STP# PLL2 PD# WD Logic SDATA SCLK VDDA I2C Logic 66B[0:2]/3V66[2:4] Power Up Logic 66IN/3V66-5 /2 Pin Configuration REF VDD XIN XOUT VSS PCIF0 PCIF1 PCIF2 VDD VSS PCI0 PCI1 PCI2 PCI3 VDD VSS PCI4 PCI5 PCI6 VDD VSS 66B0/3V66_2 66B1/3V66_3 66B2/3V66_4 66IN/3V66_5 PD# VDDA VSSA VTT_PG# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF S1 S0 CPU_STP# CPU0 CPU/0 VDD CPU1 CPU/1 VSS VDD CPU2 CPU/2 MULT0 IREF VSSIREF S2 48MUSB 48MDOT VDD VSS 3V66_1/VCH PCI_STP# 3V66_0 VDD VSS SCLK SDATA CPU(0:2) CPU/(0:2) 3V66_0 3V66_1/VCH PCI(0:6) PCI_F(0:2) 48M USB 48M DOT C9827 Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 1 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer Pin Description PIN 2 3 52, 51, 49, 48, 45, 44 10, 11, 12, 13, 16, 17, 18 5, 6, 7 NAME XIN XOUT CPU, CPU/ (0:2) PCI(0:6) PCIF (0:2) PWR VDD VDD VDDP VDD I/O I O O O O Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN. Differential host output clock pairs. See the frequency table on page one of this data sheet for frequencies and functionality. PCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See Frequency Table on page one of this data sheet. 33Mhz PCI clocks, which are ÷2 copies of 66IN or 3V66 clocks, may be free running (not stopped when PCI_STP# is asserted low) or may be stoppable depending on the programming of SMBus register Byte3, Bits (3:5). Buffered Output copy of the device’s XIN clock. Current reference programming input for CPU buffers. A resistor is connected between this pin and VSSIREF. See CPU Clock current Select Table in page 18 of this data sheet. Qualifying input that latches S (0:2) and MULT0. When this input is at a logic low, the S (0:2) and MULT0 are latched Fixed 48MHz USB Clock Outputs. Fixed 48MHZ DOT Clock Outputs. 3.3 Volt 66 MHz fixed frequency clock. 3.3 volt clock selectable with SMBus byte0, Bit5, when Byte5, Bit5. When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When byte0, Bit5 is a logic 0, then this is a 66M output clock (default). This pin is a power down mode pin. A logic low level causes the device to enter a power down state. All internal logic is turned off except for the SMBus logic. All output buffers are stopped. See the Power Down section of this data sheet. Programming input selection for CPU clock current multiplier. See CPU Clock Current Select Function Table. Frequency Select Inputs. See Frequency Table on page 1. Serial Data Input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. See application note AN-0022 Serial Clock Input. Conforms to the SMBus specification. See application note AN-0022. Frequency Select input. See Frequency Table on page 1. This is a Tri level input that is driven high, low or driven to a intermediate level. PCI Clock Disable Input. When asserted low, PCI (0:6) clocks are synchronously disabled in a low state. This pin does not effect PCIF (0:2) clocks’ outputs if they are programmed to be PCIF clocks via the device’s SMBus interface. 56 42 REF IREF VDD VDD O I 28 39 38 33 35 VTT_PG# 48MUSB 48MDOT 3V66_0 3V66_1/VCH VDD VDD48 VDD48 VDD VDD I O O O O 25 PD# VDD I PU 43 55, 54 29 MULT0 S(0,1) SDATA I I I PU I I 30 40 34 SCLK S2 PCI_STP# I VDD VDD I I T I PU Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 2 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer Pin Description (Cont.) PIN 53 NAME CPU_STP# PWR VDD I/O I PU I/O O PWR PWR PWR Description CPU Clock Disable Input. When asserted low, CPU (0:2) clocks are synchronously disabled in a high state and CPU/(0:2) clocks are synchronously disabled in a low state. Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or output clock for fixed 66 MHz clock if S2=0. See table on page 1 3.3 volt clock outputs. These clocks are buffered copies of the 66IN clock or fixed at 66 MHz. See table on page 1 3.3V Power Supply Common Ground Current reference programming input for CPU buffers. A resistor is connected between this pin and IREF. See CPU Clock current Select Table in page 18 of this data sheet. This pin should also be returned to device VSS. Analog power input. Used for PLL and internal analog circuits. Is also specifically used to detect and determine when power is at an acceptable level to enable the device to operate. 24 21, 22, 23 1, 8, 14, 19, 32, 37, 46, 50 4, 9, 15, 20, 27, 31, 36, 47 41 66IN/3V66_5 66B(0:2)/ 3V66(2:4) VDD VSS VSSIREF VDD VDD 26 VDDA - PWR PU = Internal Pull-Up. PD = Internal Pull-Down. T = Tri level logic input with valid logic voltages of LOW=2.0V 2-Wire SMBus Control Interface The 2-wire control interface implements a read/write slave only interface according to SMBus specification. (See Application Note AN-0022). The device will accept data written to the D2 address and data may read back from address D3. It will not respond to any other addresses, and previously set control registers are retained as long as power in maintained on the device. Serial Control Registers Following the acknowledge of the Address Byte, two additional bytes must be sent: 1) “Command Code “ byte, and 2) “Byte Count” byte. Although the data (bits) in the command is considered “don’t care”; it must be sent and will be acknowledged. After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2) described below will be valid and acknowledged. Note: The Pin# column lists the relevant pin number where applicable. The @Pup column gives the default state at power up. Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 3 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer Serial Control Registers (Cont.) Byte 0: CPU Clock Register Bit 7 @Pup 0 Pin# Description Spread Spectrum Enable 0 = Spread Off, 1 = Spread On This is a Read and Write control bit. Reserved 3V66_1/VCH frequency Select 0 = 66M selected, 1 = 48M selected This is a Read and Write control bit. CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read Only. Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a logical AND function of the internal SMBus register bit and the external PCI_STP# pin. Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read Only. Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read Only. Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read Only. 6 5 0 0 35 4 3 2 1 0 Pin 53 Pin 34 Pin 40 Pin 55 Pin 54 44,45,48,49, 51,52 10,11,12,13, 16,17,18 - Byte 1: CPU Clock Register Bit 7 6 5 @Pup Pin 43 0 0 Pin# 44,45 Description MULT0 (Pin 43) Value. This bit is Read Only. Reserved Controls CPU2 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. Controls CPU1 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. Controls CPU0 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. CPU2 Output Control, 1 = enabled, 0 = disable HIGH and CPU/2 disables LOW This is a Read and Write control bit. CPU1 Output Control, 1 = enabled, 0 = disable HIGH and CPU/1 disables LOW This is a Read and Write control bit. CPU0 Output Control, 1 = enabled, 0 = disable HIGH and CPU/0 disables LOW This is a Read and Write control bit. Byte 3: PCI_F Clock and 48M Control Register (all bits are read and write functional) Bit 7 6 5 @Pup 1 1 0 Pin# 38 39 7 Description 48MDOT Output Control 1 = enabled, 0 = forced LOW 48MUSB Output Control 1 = enabled, 0 = forced LOW PCI_STP#, control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW PCI_STP#, control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW PCI_STP#, control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW PCI_F2 Output Control 1=running, 0=forced LOW PCI_F1 Output Control 1= running, 0=forced LOW PCI_F0 Output Control 1= running, 0=forced LOW 12/26/2002 Page 4 of 25 4 0 48,49 3 0 51,52 2 1 0 1 1 1 44,45 48,49 51,52 Byte 2: PCI Clock Control Register (all bits are read and write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 Pin# 18 17 16 13 12 11 10 Description Reserved PCI6 Output Control 1 = enabled, 0 = forced LOW PCI5 Output Control 1 = enabled, 0 = forced LOW PCI4 Output Control 1 = enabled, 0 = forced LOW PCI3 Output Control 1 = enabled, 0 = forced LOW PCI2 Output Control 1 = enabled, 0 = forced LOW PCI1 Output Control 1 = enabled, 0 = forced LOW PCI0 Output Control 1 = enabled, 0 = forced LOW 4 0 6 3 0 5 2 1 0 1 1 1 7 6 5 Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer Byte 4: DRCG Control Register (all bits are read and write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 1 1 1 1 1 1 Pin# 33 35 24 23 22 21 Description SS2 Spread Spectrum control bit (0=down spread, 1=Center spread) Reserved 3V66_0 Output Enabled 1 = enabled, 0 = disabled 3V66_1/VCH Output Enable 1 = enabled, 0 = disabled 3V66_5 Output Enable 1 = enabled, 0 = disabled 66B2/3V66_4 Output Enabled 1 = enabled, 0 = disabled 66B1/3V66_3 Output Enabled 1 = enabled, 0 = disabled 66B0/3V66_2 Output Enabled 1 = enabled, 0 = disabled Byte 5: Clock control register (all bits are read and write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 0 0 0 0 Pin# Description SS1 Spread Spectrum control bit SS0 Spread Spectrum control bit 66IN to 66M delay Control MSB, See table 66IN to 66M delay Control LSB, See table Reserved 48MDOT edge rate control. When set to 1, the edge is slowed by 15%. Reserved USB edge rate control. When set to 1, the edge is slowed by 15% Byte 7: Watch Dog Time Stamp Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte 6: Silicon Signature Register (all bits are read only) Bit @Pup Pin# Description 7 0 Vendor Code 6 0 011 = IMI 5 0 4 0 3 0 2 0 1 1 0 1 Note: When writing to this register the device will acknowledge the write operation, but the data itself will be ignored. Byte 8: Dial-a-Frequency™ Control Register N (all bits are read and write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# 0 0 0 0 0 0 0 0 Description N7, MSB N6 N5 N4 N3 N2 N3 N0, LSB Byte 9: Dial-a-Frequency™ Control Register R (all bits are read and write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# Description R6 MSB R5 R4 R3 R2 R1 R0, LSB R and N register load gate 0=gate closed (data is latched), 1=gate open (data is loading from SMBus registers into R and N) 66IN to 66M Delay Control Table Byte5 Bit5 Bit4 0 0 0 1 1 0 1 1 Delay (ns) 4.29 4.43 3.95 (default) 3.95 Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 5 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer Dial-a-Frequency ™ Feature SMBus Dial-a-frequency feature is available in this device via Byte8 and Byte9. See our App Note AN-0025 for details on our Dial-a-Frequency™ feature. P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from the following table: S(1:0) 00 01 10 11 Table 1 P 32005333 48008000 96016000 64010667 Dial-a-dB™ Features SMBus Dial-a-dB™ feature is available in this device via Byte8 and Byte9. See our App Note AN-0026 for details on the Dial-a-dB™. Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique used to minimizing Electro-Magnetic Interference (EMI) radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control Bytes. See applications note AN-0024 for a more in depth description of Spread spectrum modulation and see the SMBus register section of this data sheet for the exact bit and byte functionally. The following table is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Spread Mode Down Down Down Down Center Center Center Center Spread % +0.00, -0.25 +0.00, -0.50 +0.00, -0.75 +0.00-1.00 +0.13, -0.13 +0.25, -0.25 +0.37, -0.37 +0.50 -1.50 Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 6 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer AC Parameters Symbol TDC TPeriod VHIGH VLOW Tr / Tf TCCJ Parameter Xin Duty Cycle Xin period Xin High Voltage Xin Low Voltage Xin rise and fall times Xin Cycle to Cycle Jitter Any CPU to CPU clock Skew CPU Cycle to Cycle Jitter CPU and CPU# Duty Cycle CPU and CPU# period CPU and CPU# rise and fall times Rise.Fall Matching Rise Time Variation Fall Time Variation crossing point voltage at 0.7 V swing Any CPU to any CPU clock Skew CPU Cycle to Cycle Jitter CPU and CPU# Duty Cycle CPU and CPU# period CPU and CPU# rise and fall times Absolute Singleended rise/fall waveform symmetry Cross point at 1.0 Volt swing 3V66 Duty Cycle 3V66 period 3V66 high time 3V66 low time 3V66 rise and fall times 3V66 to 3V66 clock skew 3V66 to 3V66 clock skew DRCG Cycle to Cycle Jitter 66 MHz Min Max 47.5 69.841 .7Vdd 0 52.5 71.0 Vdd .3Vdd 10.0 500 100 MHz Min Max 47.5 69.841 .7Vdd 0 52.5 71.0 Vdd .3Vdd 10.0 500 133 MHz Min Max 47.5 69.841 .7Vdd 0 52.5 71.0 Vdd .3Vdd 10.0 500 200 MHz Min Max 47.5 69.841 .7Vdd 0 52.5 71.0 Vdd .3Vdd 10.0 500 Units % nS Volts Volts nS pS Notes 1, 11, 14 1, 2, 4, 11 13 2, 5, 11 TSKEW TCCJ TDC TPeriod Tr / Tf 45 14.85 175 280 100 150 55 15.3 700 20% 125 125 430 - CPU at 0.7 Volts Timing 100 150 55 10.2 700 20% 125 125 430 45 7.35 175 100 150 55 7.65 700 20% 125 125 430 - 100 150 pS pS % nS ps ps ps mV 2, 5, 17 2, 17, 22 5, 17, 22 5, 17, 22 5, 6, 25 6, 21, 22 6, 22 6, 22 5, 22 45 9.85 175 280 45 4.85 175 280 55 5.1 700 20% 125 125 430 DeltaTr DeltaTf Vcross 280 TSKEW TCCJ TDC TPeriod Differential Tr / Tf SEDeltaSlew 45 14.85 175 100 150 55 15.3 467 325 - CPU at 1.0 Volts Timing 100 150 55 10.2 467 325 45 7.35 175 100 150 55 7.65 467 325 - 100 150 pS pS % nS ps ps 2, 5, 17 2, 17 5, 17 5, 17 5, 25 7, 26 45 9.85 175 45 4.85 175 55 5.1 467 325 Vcross 510 760 510 760 510 760 510 760 mV 26 TDC TPeriod THIGH TLOW Tr / Tf Tskew Unbuffered Tskew Buffered TCCJ 45 15.0 4.95 4.55 0.5 - 55 15.3 2.0 500 250 250 45 15.0 4.95 4.55 0.5 - 55 15.3 2.0 500 250 250 45 15.0 4.95 4.55 0.5 - 55 15.3 2.0 500 250 250 45 15.0 4.95 4.55 0.5 - 55 15.3 2.0 500 250 250 % nS nS nS nS pS pS pS 2, 4 1, 2, 4 19 20 3 2, 4 2, 4 2, 4 Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 7 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer AC Parameters (Cont.) Symbol TDC Tr / Tf TSKEW Tpd TCCJ Parameter 66B(0:2) Duty Cycle 66B(0:2) rise and fall times Any 66B to any 66B Skew 66IN to 66B(0:2) propagation delay 66B(0:2) Cycle to Cycle Jitter PCI_F(0:2) PCI (0:6) Duty Cycle PCI_F(0:2) PCI (0:6) period PCI_F(0:2) PCI (0:6) high time PCI_F(0:2) PCI (0:6) low time PCI_F(0:2) PCI (0:6) rise and fall times Any PCI clock to Any PCI clock Skew PCI_F(0:2) PCI (0:6) Cycle to Cycle Jitter USB48M Duty Cycle USB48M period USB48M rise and fall times USB48M Cycle to Cycle Jitter DOT48 Duty Cycle DOT48 period DOT48 rise and fall times DOT48Cycle to Cycle Jitter 66 MHz Min Max 45 0.5 2.5 55 2.0 175 4.5 100 100 MHz Min Max 45 0.5 2.5 55 2.0 175 4.5 100 133 MHz Min Max 45 0.5 2.5 55 2.0 175 4.5 100 200 MHz Min Max 45 0.5 55 2.0 175 2.5 4.5 100 Units % nS pS nS pS Notes 2, 4 2, 3 2, 4 2, 4 2, 4, 18 TDC TPeriod THIGH TLOW Tr / Tf 45 30.0 12.0 12.0 0.5 55 2.0 45 30.0 12.0 12.0 0.5 55 2.0 45 30.0 12.0 12.0 0.5 55 2.0 45 30 12.0 12.0 0.5 55 2.0 % nS nS nS nS 2, 4 1, 2, 4 19 20 3 TSKEW - 500 - 500 - 500 - 500 pS 2, 4 TCCJ - 250 - 250 - 250 - 250 pS 2, 4 TDC TPeriod Tr / Tf TCCJ 45 20.8299 1.0 - 55 20.8333 2.0 350 45 20.8299 1.0 - 55 20.8333 2.0 350 45 20.8299 1.0 - 55 20.8333 2.0 350 45 20.8299 1.0 - 55 20.8333 2.10 350 % nS nS pS 2, 4 2, 4 2, 3 1, 2, 4 TDC TPeriod Tr / Tf TCCJ 45 20.837 0.5 - 55 45 20.837 0.5 - 55 45 20.837 0.5 - 55 45 20.837 0.5 - 55 % nS nS pS 2, 4 2, 4 2, 4 2, 4 1.0 350 1.0 350 1.0 350 1.0 350 Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 8 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer AC Parameters (Cont.) Symbol TDC TPeriod Tr / Tf TCCJ Parameter REF Duty Cycle REF period REF rise and fall times REF Cycle to Cycle Jitter Output enable delay (all outputs) Output disable delay (all outputs) All clock Stabilization from power-up Stopclock Set Up Time Stopclock Hold Time Oscillator startup time 66 MHz Min Max 45 69.8413 1.0 55 71.0 4.0 1000 100 MHz Min Max 45 69.8413 1.0 55 71.0 4.0 1000 133 MHz Min Max 45 69.8413 1.0 55 71.0 4.0 1000 200 MHz Min Max 45 69.8413 1.0 55 71.0 4.0 1000 Units % nS nS pS Notes 2, 4 2, 4 2, 3 2, 4 tpZL, tpZH tpLZ, tpZH tstable 1.0 1.0 - 10.0 10.0 3 1.0 1.0 - 10.0 10.0 3 1.0 1.0 - 10.0 10.0 3 1.0 1.0 - 10.0 10.0 3 nS nS mS 11 11 11 tss tsh tsu 10.0 0 - X 10.0 0 - X 10.0 0 - X 10.0 0 - X nS nS mS 10 10 12 (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C) This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz All outputs loaded as per table 5 below. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement setup section of this data sheet) Note 4: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals (see test and measurement setup section of this data sheet). Note 5: This measurement is applicable with Spread ON or Spread OFF. Note 6: Measured from Vol = 0.175V to Voh = 0.525V. Note 7: Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the instantaneous difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is designed form waveform symmetry. Note 8: The time specified is measured from when all VDD’s reach their supply rail (3.3V) till the frequency output is stable and operating within the specifications. Note 9: Measured from when both SEL1 and SEL0 are low Note 10: CPU_STP# and PCI_STP# setup time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock’s rising edge. Note 11: When Xin is driven from an external clock source. Note 12: When Crystal meets minimum 40 ohm device series resistance specification. Note 13: Measured between 0.2Vdd and .7Vdd Note 14: This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within data sheet specifications. Note 15: Vpullup(external)=1.5V, Min=(Vpullup(external)/2)-150mV, Max=(Vpullup(external)/2)+150mV Note 16: Vp = V pull-up (external), Vdif specifies the minimum input differential voltage (Vtr-Vcp) required for switching, where Vtr is the true input level and Vcp is the compliment input level. Note 17: Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0 volts. Note 18: This figure is additive to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500 ps jitter figure is specified. Note 19: THIGH is measured at 2.4V for non host outputs. Note 20: TLOW is measured at 0.4V for all outputs. Note 21: Determined as a fraction of 2*(Trise-Tfall)/ (Trise+Tfall). Note 22: Test load is Rta=33.2 ohms, Rd=49.9 ohms. Note 23: These crossing points refer to only crossing points containing a rising edge of a Host output. Note 24: This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Note 25: Measurement taken from differential waveform, from –0.35V to +0.35V. Note 26: Measured in absolute voltage, i.e. single-ended measurement. Cypress Semiconductor Corporation http://www.cypress.com Note 1: Note 2: Note 3: Document#: 38-07106 Rev. *A 12/26/2002 Page 9 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer Maximum Lumped Capacitive Output Loads Clock PCI Clocks 3V66 (0,1) 66B(0:2) 48MUSB Clock 48MDOT REF Clock Max Load 30 30 30 20 10 30 Table 5 Units pF pF pF pF pF pF Maximum Ratings¹ Input Voltage Relative to VSS: Storage Temperature: Operating Temperature: Maximum Power Supply: VSS-0.3V -65°C to + 150°C 0°C to +85°C 3.5V Input Voltage Relative to VDDQ or AVDD: VDD+0.3V Note 1: The voltage on any input or I/o pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Test and Measurement Setup For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs. TPCB CLK RtA1 Mult0 TPCB RtA2 RLA2 RLB2 RtB2 RLA1 RLB1 RD RtB1 CLK Measurement Point CLA CLK Measurement Point CLK# CLB Rref Lumped Test Load Configuration Component RtA1, RtA2 RLA1, RLA2 TPCB RLB1, RLB2 RD RtB1, RtB2 CLA, CLB Rref 0.7 Volt Amplitude Value 33 Ω 49.9 Ω 3” 50 ΩZ ∞ ∞ 0Ω 2pF 475 Ω w/mult0=1 1.0 Volt Amplitude Value 0Ω ∞ 3” 50 ΩZ 63 Ω 470 Ω 33 Ω 2 pF 221 Ω w/mult0=0 Document#: 38-07106 Rev. *A 12/26/2002 Page 10 of 25 Cypress Semiconductor Corporation http://www.cypress.com Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer Test and Measurement Setup (Cont.) For single Ended Output Signals Output under Test Probe Load Cap 3.3V signals tDC - 3.3V 2.4V 1.5V 0.4V 0V Tr Tf Buffer Characteristics Current Mode CPU Clock Buffer Characteristics The current mode output buffer detail and current reference circuit details are contained in the previous table of this data sheet. The following parameters are used to specify output buffer characteristics: 1. 2. 3. 4. Output impedance of the current mode buffer circuit - Ro (see figure below). Minimum and maximum required voltage operation range of the circuit – Vop (see figure below). Series resistance in the buffer circuit – Ros (see figure below). Current accuracy at given configuration into nominal test load for given configuration. Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 11 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer VDD3 (3.3V +/- 5%) Ro Iout Slope ~ 1/R0 Ros 0V Iout 1.2V Vout = 1.2V max Vout Host Clock (HCSL) Buffer Characteristics Characteristic Minimum Maximum Ro 3000 Ohms (recommended) N/A Ros Vout N/A 1.2V Iout is selectable depending on implementation. The parameters above apply to all configurations. Vout is the voltage at the pin of the device. The various output current configurations are shown in the host swing select functions table. For all configurations, the deviation from the expected output current is +/- 7% as shown in the current accuracy table. CPU Clock Current Select Function Mult0 Board Target Trace/Term Z 0 50 Ohms 1 50 Ohms Reference R, Iref – Vdd (3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 4*Iref Ioh = 6*Iref Voh @ Z 1.0V @ 50 0.7V @ 50 Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 12 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer Group Timing Relationship and Tolerances Offset 3V66 to PCI USB to DOT 48M Skew 66B(0:2) to PCI offset 2.5 nS 0.0 nS 2.5 nS Tolerance ±1.0 nS ±1.0 nS ±1.0 nS Conditions 3V66 Leads PCI (un-buffered mode) 0 degrees phase shift 66B leads PCI (buffered mode) USB and DOT 48M Phase Relationship The 48MUSB and 48MDOT clocks are in phase. It is understood that the difference in edge rate will introduce some inherent offset. When 3V66_1/VCH clock is configured for VCH (48MHz) operation it is also in phase with the USB and DOT outputs. USB48M DOT48M 48MUSB and 48MDOT Phase Relationship Figure 66IN to 66B(0:2) Buffered Prop Delay The 66IN to 66B(0:2) output delay is shown below. 66IN Tpd 66CB0:2) 66IN to 66B(0:2) Output Delay Figure The Tpd is the prop delay from the input pin (66IN) to the output pins (66B[0:2]). The outputs’ variation of Tpd is described in the AC parameters section of this data sheet. The measurement taken at 1.5 volts. Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 13 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer 66BUF to PCI Buffered Clock Skew The following figure shows the difference (skew) between the 3V33(0:5) outputs when the 66M clocks are connected to 66IN. This offset is described in the Group Timing Relationship and Tolerances section of this data sheet. The measurements were taken at 1.5 volts. 66BUF(0:2) PCI(0:6) PCIF(0:2) 1.53.5ns Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship 3V66 to PCI Un-Buffered Clock Skew The following figure show the timing relationship between 3V66_(0:5) and PCI(0:6) and PCIF(0:2) when configured to run in the un-buffered mode. 3V66_(0:5) PCI(0:6) PCIF(0:2) 1.53.5ns Un-buffered Mode - 3V66_(0:5) to PCI (0:6) and PCIF(0:2) Phase Relationship Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 14 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer Special Functions PCI_F and IOAPIC Clock Outputs The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. ANY 2 of the PCI_F clock outputs can be used as IOAPIC 33Mhz clock outputs. They are 3.3V outputs will be divided down via a simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event these clocks are not required, then these clocks can be used as general PCI clocks or disabled via the assertion of the PCI_STP# pin. 3V66_1/VCH Clock Output The 3V66_1/VCH pin has a dual functionality, which is selectable via SMBus. Configured as DRCG (66M), SMBus Byte0, Bit 5 = ‘0’ The default condition for this pin is to power up in a 66M operation. In 66M operation this output is SSCG capable and when spreading is turned on, this clock will be modulated. Configured as VCH (48M), SMBus Byte0, Bit 5 = ‘1’ In this mode, the output is configured as a 48Mhz non-spread spectrum output. This output is phase aligned with the other 48M outputs (USB and DOT), to within 1ns pin to pin skew. The switching of 3V66_1/VCH into VCH mode occurs at system power on. When the SMBus Bit 5 of Byte 0 is programmed from a ‘0’ to a ‘1’, the 3V66_1/VCH output may glitch while transitioning to 48M output mode. CPU_STP# Clarification The CPU_STP# signal is an active low input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 15 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer CPU_STP# - Assertion (transition from logic ‘1’ to logic ‘0’) When CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by 2 falling CPU clock edges. The final state of the stopped CPU signals is CPU = high and CPU0# = Low. There is no change to the output drive current values during the stopped state. The CPU is driven high with a current value equal to (Mult 0 ‘select’) x (Iref), and the CPU# signal will not be driven. Due to external pulldown circuitry CPU# will be low during this stopped state. CPU_STP# CPU CPU# Assertion CPU_STP# Waveform Figure CPU_STP# Functionality Table CPU_STP# CPU#4 CPU 1 Normal Normal 0 Iref*Mult Float DRCG 66M 66M 66CLK(0:2) 66Input 66Input PCI_F/PCI 66Input/2 66Input/2 PCI 66Input/2 66Input/2 USB/DOT 48M 48M CPU_STP# De-assertion (transition from logic ‘0’ to logic ‘1’) The de-assertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produces when the clock resumes. The maximum latency from the de-assertion to active outputs is no more than 2 CPU clock cycles. Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 16 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer PCI_STP# Clarification The PCI_STP# signal is an active low input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The setup time for capturing PCI_STP# going low is 10 nsec (tsetup). The PCI_F (0:2) clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free running. t setup PCI_STP# PCI_F(0:2) 33M PCI(0:6) 33M PCI_S TP# Waveform Figure PCI_STP# - De-assertion (transition from logic ‘0’ to logic ‘1’) The de-assertion of the PCI_STP# signal will cause all PCI(0:6) and stoppable PCI_F(0:2) clocks to resume running in a synchronous manner within 2 PCI clock periods after PCI_STP# transitions to a high level. Note that the PCI STOP function is controlled by 2 inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These 2 inputs to the function are logically ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set low thereby indicating the devices stoppable PCI clocks are not running. Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 17 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer PD# (Power Down) Clarification The PD# (Power Down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active low input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a low value and held there and the VCO and PLL’s are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ‘stopped’ state. PD# Functionality PD# CPU 1 Normal 0 Iref*2 CPU# Normal Float Low DRCG 66M Low 66CLK (0:2) 66Input Low PCI_F/PCI 66Input/2 Low PCI 66Input/2 Low USB/DOT 48M Low PD# - Assertion (transition from logic ’l’ to logic ‘0’)- Buffered Mode When PD# is sampled low by two consecutive rising edges of the CPU# clock, then on the next high to low transition of PCIF, the PCIF clock is stopped low. On the next high to low transition of 66Buff, the 66Buff clock is stopped low. From this time, each clock will stop low on it’s next high to low transition, except the CPU clock. The CPU clocks are held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# un-driven. After the last clock has stopped, the rest of the generator will be shut down. 66Buff[0..2] PCIF PWRDWN# CPU 133MHz CPU# 133MHz 3V66 66In USB 48MHz REF 14.318MHz Power Down Assertion Timing Waveforms Figure – Buffered Mode Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 18 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer PCI 33MHz PWRDWN# CPU 133MHz CPU# 133MHz 3V66 USB 48MHz REF 14.318MHz Power Down Assertion Timing Waveforms Figure – Non-Buffered Mode Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07106 Rev. *A 12/26/2002 Page 19 of 25 Approved Product C9827H High Performance Pentium® 4 Clock Synthesizer PD# - De-assertion (transition from logic ‘0’ to logic ‘1’) The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 mS.