Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
64-Kbit (8K × 8) SPI nvSRAM
64-Kbit (8K × 8) SPI nvSRAM
■
■
■
64-Kbit nonvolatile static random access memory (nvSRAM)
internally organized as 8K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
❐ Support automatic STORE on power-down with a small
capacitor (except for CY14MX064Q1B)
High reliability
Infinite read, write, and RECALL cycles
1million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 C
■ High speed serial peripheral interface (SPI)
❐ 40-MHz clock rate SPI write and read with zero cycle delay
❐ Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
❐
❐
■
■
■
SPI access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8-byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
Industry standard configurations
❐ Operating voltages:
• CY14MB064Q1B/CY14MB064Q2B: VCC = 2.7 V to 3.6 V
• CY14ME064Q1B/CY14ME064Q2B: VCC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 8-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Functional Description
The Cypress CY14MX064Q combines a 64-Kbit nvSRAM with a
nonvolatile element in each memory cell with serial SPI interface.
The memory is organized as 8K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down (except for CY14MX064Q1B). On power-up, data
is restored to the SRAM from the nonvolatile memory (RECALL
operation). You can also initiate the STORE and RECALL
operations through SPI instruction.
For a complete list of related documentation, click here.
Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4, 1/2, or entire array
Configuration
Low power consumption
❐ Average active current of 3 mA at 40 MHz operation
❐ Average standby mode current of 120 A
❐ Sleep mode current of 8 A
Feature
CY14MX064Q1B
CY14MX064Q2B
AutoStore
No
Yes
Software STORE
Yes
Yes
Logic Block Diagram
Serial Number
8x8
Manufacturer ID /
Product ID
Status Register
QuantumTrap
8Kx8
WRSR/RDSR/WREN
SI
RDSN/WRSN/RDID
CS
READ/WRITE
SCK
SPI Control Logic
Write Protection
Instruction decoder
STORE/RECALL/ASENB/ASDISB
Memory
Data & Address
Control
SRAM
8Kx8
STORE
RECALL
WP
SO
VCC
VCAP
Power Control Block
Cypress Semiconductor Corporation
Document Number: 001-70382 Rev. *L
SLEEP
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 27, 2019
Not Recommended for New Designs
Features
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Write ................................................................. 4
SRAM Read ................................................................ 4
STORE Operation ....................................................... 4
AutoStore Operation .................................................... 4
Software STORE Operation ........................................ 5
RECALL Operation ...................................................... 5
Hardware RECALL (Power-Up) .................................. 5
Software RECALL ....................................................... 5
Disabling and Enabling AutoStore ............................... 5
Serial Peripheral Interface ............................................... 6
SPI Overview ............................................................... 6
SPI Modes ................................................................... 7
SPI Operating Features .................................................... 8
Power-Up .................................................................... 8
Power-Down ................................................................ 8
Active Power and Standby Power Modes ................... 8
SPI Functional Description .............................................. 9
Status Register ............................................................... 10
Read Status Register (RDSR) Instruction ................. 10
Write Status Register (WRSR) Instruction ................ 10
Write Protection and Block Protection ......................... 11
Write Enable (WREN) Instruction .............................. 11
Write Disable (WRDI) Instruction .............................. 11
Block Protection ........................................................ 12
Hardware Write Protection (WP) ............................... 12
Memory Access .............................................................. 12
Read Sequence (READ) Instruction .......................... 12
Write Sequence (WRITE) Instruction ........................ 12
nvSRAM Special Instructions ........................................ 14
Software STORE (STORE) Instruction ..................... 14
Software RECALL (RECALL) Instruction .................. 14
AutoStore Enable (ASENB) Instruction ..................... 14
Document Number: 001-70382 Rev. *L
AutoStore Disable (ASDISB) Instruction ................... 15
Special Instructions ....................................................... 15
SLEEP Instruction ..................................................... 15
Serial Number ................................................................. 15
WRSN (Serial Number Write) Instruction .................. 15
RDSN (Serial Number Read) Instruction ................... 16
Device ID ......................................................................... 16
RDID (Device ID Read) Instruction ........................... 17
HOLD Pin Operation ................................................. 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
DC Electrical Characteristics ........................................ 18
Data Retention and Endurance ..................................... 20
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 20
AC Test Conditions ........................................................ 20
AC Switching Characteristics ....................................... 21
Switching Waveforms .................................................... 22
AutoStore or Power-Up RECALL .................................. 23
Software Controlled STORE and RECALL Cycles ...... 24
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagrams .......................................................... 26
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Page 2 of 29
Not Recommended for New Designs
Contents
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Pinout
Figure 1. 8-pin SOIC pinout [1, 2]
1
8
SO
2
WP
3
CY14MX064Q1B 7
Top View
6
not to scale
VSS
4
5
VCC
CS
1
8
HOLD
SO
2
VCAP
3
CY14MX064Q2B 7
Top View
6
not to scale
VSS
4
SCK
SI
5
VCC
HOLD
SCK
SI
Pin Definitions
Pin Name [1, 2]
I/O Type
Description
CS
Input
Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low
power standby mode.
SCK
Input
Serial Clock. Runs at speeds up to a maximum of fSCK. Serial input is latched at the rising edge of
this clock. Serial output is driven at the falling edge of the clock.
Serial Input. Pin for input of all SPI instructions and data.
SI
Input
SO
Output
WP
Input
Write Protect. Implements hardware write protection in SPI.
HOLD
Input
HOLD Pin. Suspends serial operation.
VCAP
NC
Serial Output. Pin for output of data through SPI.
Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to ground.
No connect
No Connect: This pin is not connected to the die.
VSS
Power supply Ground
VCC
Power supply Power supply
Notes
1. CY14MX064Q1B part does not have VCAP pin and does not support AutoStore.
2. CY14MX064Q2B part does not have WP pin.
Document Number: 001-70382 Rev. *L
Page 3 of 29
Not Recommended for New Designs
CS
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
CY14MX064Q is a 64-Kbit serial (SPI) nvSRAM memory with a
nonvolatile element in each memory cell. All the reads and writes
to nvSRAM happen to the SRAM, which gives nvSRAM the
unique capability to handle infinite writes to the memory. The
data in SRAM is secured by a STORE sequence which transfers
the data in parallel to the nonvolatile QuantumTrap cells. A small
capacitor (VCAP) is used to AutoStore the SRAM data in
nonvolatile cells when power goes down providing power-down
data security. The QuantumTrap nonvolatile elements built in the
reliable SONOS technology make nvSRAM the ideal choice for
secure data storage.
The 64-Kbit memory array is organized as 8K words × 8 bits. The
memory can be accessed through a standard SPI interface that
enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.
The device is enabled using the Chip Select (CS) pin and
accessed through Serial Input (SI), Serial Output (SO), and
Serial Clock (SCK) pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (1/4, 1/2, or full
array) using BP0 and BP1 pins in the Status Register. Further,
the HOLD pin is used to suspend any serial communication
without resetting the serial sequence.
CY14MX064Q uses the standard SPI opcodes for memory
access. In addition to the general SPI instructions for read and
write, it provides four special instructions that allow access to
four nvSRAM specific functions: STORE, RECALL, AutoStore
Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable you to choose a part which fits in best in their application.
The feature summary is given in Table 1.
Table 1. Feature Summary
Feature
CY14MX064Q1B
CY14MX064Q2B
WP
Yes
No
VCAP
No
Yes
AutoStore
No
Yes
Power-Up RECALL
Yes
Yes
Software STORE
Yes
Yes
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
allows you to perform infinite write operations. A write cycle is
Document Number: 001-70382 Rev. *L
performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed. The data is read
out with zero cycle delay after the READ instruction is executed.
The READ instruction is issued through the SI pin of the nvSRAM
and consists of the READ opcode and two bytes of address. The
data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device STOREs data to the
nonvolatile cells using one of the two STORE operations:
AutoStore, activated on device power-down; and Software
STORE, activated by a STORE instruction. During the STORE
cycle, an erase of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements. After a
STORE cycle is initiated, read/write to CY14MX064Q is inhibited
until the cycle is completed.
The RDY bit in the Status Register can be monitored by the
system to detect if a STORE or Software RECALL cycle is in
progress. The busy status of nvSRAM is indicated RDY bit being
set to ‘1’. To avoid unnecessary nonvolatile STOREs, AutoStore
operation is ignored unless at least one write operation has taken
place since the most recent STORE or RECALL cycle. However,
software initiated STORE cycles are performed regardless of
whether a write operation has taken place.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
Page 4 of 29
Not Recommended for New Designs
Device Operation
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
(AutoStore Disable (ASDISB) Instruction on page 15). If
AutoStore is enabled without a capacitor on the VCAP pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This will corrupt the data stored in
nvSRAM, Status Register as well as the serial number and it will
unlock the SNL bit. To resume normal functionality, the WRSR
instruction must be issued to update the nonvolatile bits BP0,
BP1, and WPEN in the Status Register.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. Refer to DC Electrical
Characteristics on page 18 for the size of the VCAP.
Note CY14MX064Q1B does not support AutoStore operation.
You must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
Figure 2. AutoStore Mode
VCC
10 kOhm
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power-up
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
Hardware RECALL (Power-Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time.
Software RECALL
Software RECALL allows you to initiate a RECALL operation to
restore the content of nonvolatile memory on to the SRAM. A
Software RECALL is issued by using the SPI instruction for
RECALL.
0.1 uF
VCC
CS
RECALL Operation
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
VCAP
Disabling and Enabling AutoStore
VCAP
VSS
Software STORE Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
A STORE cycle takes tSTORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register may be polled to find the Ready or Busy
status of the nvSRAM. After the tSTORE cycle time is completed,
the SRAM is activated again for read and write operations.
Document Number: 001-70382 Rev. *L
If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power-down.
AutoStore can be re enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if you need
this setting to survive the power cycle, a STORE operation must
be performed following AutoStore Disable or Enable operation.
Note CY14MX064Q2B comes with the factory with autoStore
enabled and CY14MX064Q1B/CY14MX064Q2B with 0x00
written in all cells. In CY14MX064Q1B, VCAP pin is not present
and AutoStore option is not available.
Note If AutoStore is disabled and VCAP is not required, then the
VCAP pin must be left open. The VCAP pin must never be
connected to ground. The Power-Up RECALL operation cannot
be disabled in any case.
Page 5 of 29
Not Recommended for New Designs
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Serial Peripheral Interface
Serial Clock (SCK)
SPI Overview
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
CY14MX064Q enables SPI modes 0 and 3 for data
communication. In both these modes, the inputs are latched by
the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of SPI instruction on the
SI pin. Further, all data inputs and outputs are synchronized with
SCK.
Data Transmission - SI/SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14MX064Q has two separate pins for SI and SO, which can
be connected with the master as shown in Figure 3 on page 7.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
The 64-Kbit serial nvSRAM requires a 2-byte address for any
read or write operation. However, since the address is only
13 bits, it implies that the first three bits which are fed in are
ignored by the device. Although these three bits are ‘don’t care’,
Cypress recommends that these bits are treated as 0s to enable
seamless transition to higher memory densities.
Serial Opcode
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
CY14MX064Q operates as a SPI slave and may share the SPI
bus with other SPI slave devices.
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14MX064Q uses the standard opcodes for memory
accesses. In addition to the memory accesses, it provides
additional opcodes for the nvSRAM specific functions: STORE,
RECALL, AutoStore Enable, and AutoStore Disable. Refer to
Table 2 on page 9 for details.
Chip Select (CS)
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tri-stated.
For selecting any slave device, the master needs to pull-down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW. When the device is
not selected, data through the SI pin is ignored and the serial
output pin (SO) remains in a high impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Document Number: 001-70382 Rev. *L
Invalid Opcode
Status Register
CY14MX064Q has an 8-bit Status Register. The bits in the Status
Register are used to configure the SPI bus. These bits are
described in the Table 4 on page 10.
Page 6 of 29
Not Recommended for New Designs
The SPI is a four- pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
CY14MX064Q provides serial access to nvSRAM through SPI
interface. The SPI bus on CY14MX064Q can run at speeds up
to 40 MHz.
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Figure 3. System Configuration Using SPI nvSRAM
SCK
M OSI
M IS O
SCK
SI
SO
SCK
SI
SO
u C o n tro lle r
CY14MX064Q
CS
HO LD
CS
HO LD
Not Recommended for New Designs
CY14MX064Q
CS1
HO LD 1
CS2
HO LD 2
SPI Modes
CY14MX064Q may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
■
SPI Mode 0 (CPOL = 0, CPHA = 0)
■
SPI Mode 3 (CPOL = 1, CPHA = 1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles, is considered. The output data
is available on the falling edge of SCK.
Figure 4. SPI Mode 0
CS
0
SI
7
The two SPI modes are shown in Figure 4 and Figure 5. The
status of clock when the bus master is in standby mode and not
transferring data is:
■
SCK remains at 0 for Mode 0
■
SCK remains at 1 for Mode 3
CPOL and CPHA bits must be set in the SPI controller for either
Mode 0 or Mode 3. The device detects the SPI mode from the
status of SCK pin when the device is selected by bringing the CS
pin LOW. If SCK pin is LOW when the device is selected, SPI
Mode 0 is assumed and if SCK pin is HIGH, it works in SPI
Mode 3.
1
3
4
5
6
7
6
5
4
3
2
1
0
MSB
LSB
Figure 5. SPI Mode 3
CS
0
1
2
3
4
5
6
7
SCK
SI
7
MSB
Document Number: 001-70382 Rev. *L
2
SCK
6
5
4
3
2
1
0
LSB
Page 7 of 29
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Power-Up
Power-up is defined as the condition when the power supply is
turned on and VCC crosses Vswitch voltage.
As described earlier, at power-up nvSRAM performs a Power-Up
RECALL operation for tFA duration during which, all memory
accesses are disabled.
The following are the device status after power-up.
■
Selected (Active power mode) if CS pin is LOW
■
Deselected (Standby power mode) if CS pin is HIGH
■
Not in the Hold condition
Status Register state:
❐ Write Enable (WEN) bit is reset to ‘0’.
❐ WPEN, BP1, BP0 unchanged from previous STORE
operation.
The WPEN, BP1, and BP0 bits of the Status Register are
non-volatile bits and remain unchanged from the previous
STORE operation.
■
Document Number: 001-70382 Rev. *L
Power-Down
At power-down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress and the last data bit D0 has been
received when the power goes down, it is allowed tDELAY time to
complete the write. After this, all memory accesses are inhibited
and a conditional AutoStore operation is performed (AutoStore is
not performed if no writes have happened since the last RECALL
cycle). This feature prevents inadvertent writes to nvSRAM from
happening during power-down.
However, to completely avoid the possibility of inadvertent writes
during power-down, ensure that the device is deselected and is
in standby power mode, and the CS follows the voltage applied
on VCC.
Active Power and Standby Power Modes
When CS is LOW, the device is selected and is in the active
power mode. The device consumes ICC current, as specified in
DC Electrical Characteristics on page 18. When CS is HIGH, the
device is deselected and the device goes into the standby power
mode after tSB time if a STORE or RECALL cycle is not in
progress. If a STORE/RECALL cycle is in progress, the device
goes into the standby power mode after the STORE or RECALL
cycle is completed. In the standby power mode, the current
drawn by the device drops to ISB.
Page 8 of 29
Not Recommended for New Designs
SPI Operating Features
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
SPI Functional Description
The CY14MX064Q uses an 8-bit instruction register. Instructions
and their opcodes are listed in Table 2. All instructions,
addresses, and data are transferred with the MSB first and start
with a HIGH to LOW CS transition. There are, in all, 14 SPI
instructions which provide access to most of the functions in
nvSRAM. Further, the WP, and HOLD pins provide additional
functionality driven through hardware.
Table 2. Instruction Set
Instruction Category
Instruction Name
Opcode
Operation
Status Register access
Write protection and block
protection
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
WREN
0000 0110
Set write enable latch
WRDI
0000 0100
Reset write enable latch
READ
0000 0011
Read data from memory array
WRITE
0000 0010
Write data to memory array
STORE
0011 1100
Software STORE
RECALL
0110 0000
Software RECALL
SRAM Read/Write Instructions
Memory access
Special NV Instructions
nvSRAM special functions
ASENB
0101 1001
AutoStore Enable
ASDISB
0001 1001
AutoStore Disable
Sleep
SLEEP
1011 1001
Sleep mode enable
Serial number
WRSN
1100 0010
Write serial number
RDSN
1100 0011
Read serial number
RDID
1001 1111
Read manufacturer JEDEC ID and product ID
Special Instructions
Device ID read
Reserved Instructions
Reserved
0001 1110
0000 1001
- Reserved -
0000 1011
1100 1001
1001 1001
The SPI instructions are divided based on their functionality in
the following types:
❐ Status Register control instructions:
• Status Register access: RDSR and WRSR instructions
• Write protection and block protection: WREN and WRDI
instructions along with WP pin and WEN, BP0, and BP1
bits
❐ SRAM read/write instructions
• Memory access: READ and WRITE instructions
Document Number: 001-70382 Rev. *L
Special NV instructions
• nvSRAM special instructions: STORE, RECALL, ASENB,
and ASDISB
❐ Special instructions
• SLEEP, WRSN, RDSN, RDID
❐
Page 9 of 29
Not Recommended for New Designs
Status Register Control Instructions
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Status Register
from the factory for WEN, BP0, BP1, bits 4–5, SNL and WPEN
is ‘0’.
The Status Register bits are listed in Table 3. The Status Register
consists of a Ready bit (RDY) and data protection bits BP1, BP0,
WEN, and WPEN. The RDY bit can be polled to check the Ready
or Busy status while a nvSRAM STORE or Software RECALL
cycle is in progress. The Status Register can be modified by
WRSR instruction and read by RDSR instruction. However, only
the WPEN, BP1, and BP0 bits of the Status Register can be
modified by using the WRSR instruction. The WRSR instruction
has no effect on WEN and RDY bits. The default value shipped
SNL (bit 6) of the Status Register is used to lock the serial
number written using the WRSN instruction. The serial number
can be written using the WRSN instruction multiple times while
this bit is still ‘0’. When set to ‘1’, this bit prevents any modification
to the serial number. This bit is factory programmed to ‘0’ and
can only be written to once. After this bit is set to ‘1’, it can never
be cleared to ‘0’.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN (0)
SNL (0)
X (0)
X (0)
BP1 (0)
BP0 (0)
WEN (0)
RDY
Table 4. Status Register Bit Definition
Bit
Definition
Description
Bit 0 (RDY)
Ready
Read only bit indicates the ready status of device to perform a memory access. This bit is
set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress.
Bit 1 (WEN)
Write Enable
WEN indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEN = ‘1’ --> Write enabled
WEN = ‘0’ --> Write disabled
Bit 2 (BP0)
Block Protect bit ‘0’
Used for block protection. For details see Table 5 on page 12.
Bit 3 (BP1)
Block Protect bit ‘1’
Used for block protection. For details see Table 5 on page 12.
Bit 4–5
Don’t care
These bits are non-writable and always return ‘0’ upon read.
Bit 6 (SNL)
Serial Number Lock
Set to ‘1’ for locking serial number
Bit 7 (WPEN)
Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 6 on page 12.
Read Status Register (RDSR) Instruction
The Read Status Register instruction provides access to the
Status Register. This instruction is used to probe the Write
Enable status of the device or the Ready status of the device.
RDY bit is set by the device to 1 whenever a STORE or Software
RECALL cycle is in progress. The block protection and WPEN
bits indicate the extent of protection employed.
This instruction is issued after the falling edge of CS using the
opcode for RDSR.
Write Status Register (WRSR) Instruction
The WRSR instruction enables the user to write to the Status
Register. However, this instruction cannot be used to modify bit
0 (RDY), bit 1 (WEN) and bits 4–5. The BP0 and BP1 bits can be
used to select one of four levels of block protection. Further,
WPEN bit must be set to ‘1’ to enable the use of Write Protect
(WP) pin.
Document Number: 001-70382 Rev. *L
WRSR instruction is a write instruction and needs writes to be
enabled (WEN bit set to ‘1’) using the WREN instruction before
it is issued. The instruction is issued after the falling edge of CS
using the opcode for WRSR followed by eight bits of data to be
stored in the Status Register. WRSR instruction can be used to
modify only bits 2, 3, 6 and 7 of the Status Register.
Note In CY14MX064Q, the values written to Status Register are
saved to nonvolatile memory only after a STORE operation. If
AutoStore is disabled (or while using CY14MX064Q1B), any
modifications to the Status Register must be secured by
performing a Software STORE operation.
Note CY14MX064Q2B does not have WP pin. Any modification
to bit 7 of the Status Register has no effect on the functionality of
CY14MX064Q2B.
Page 10 of 29
Not Recommended for New Designs
Table 3. Status Register Format
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Figure 6. Read Status Register (RDSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
0
1
2
3
4
5
6
7
SCK
Op-Code
0
0
0
0
0
1
0
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Data
Not Recommended for New Designs
SI
Figure 7. Write Status Register (WRSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data in
Opcode
SI
SO
0
0
0
0
0
0
0
1 D7 X
MSB
X
X D3 D2 X
X
LSB
HI-Z
Write Protection and Block Protection
CY14MX064Q provides features for both software and hardware
write protection using WRDI instruction and WP. Additionally, this
device also provides block protection mechanism through BP0
and BP1 pins of the Status Register.
The write enable and disable status of the device is indicated by
WEN bit of the Status Register. The write instructions (WRSR,
WRITE and WRSN) and nvSRAM special instruction (STORE,
RECALL, ASENB and ASDISB) need the write to be enabled
(WEN bit = ‘1’) before they can be issued.
Write Enable (WREN) Instruction
On power-up, the device is always in the write disable state. The
following WRITE, WRSR, WRSN, or nvSRAM special instruction
must therefore be preceded by a Write Enable instruction. If the
device is not write enabled (WEN = ‘0’), it ignores the write
instructions and returns to the standby state when CS is brought
HIGH. A new CS falling edge is required to re-initiate serial
communication. The instruction is issued following the falling
edge of CS. When this instruction is used, the WEN bit of Status
Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up.
Note After completion of a write instruction (WRSR, WRITE,
WRSN) or nvSRAM special instruction (STORE, RECALL,
ASENB, and ASDISB) instruction, WEN bit is cleared to ‘0’. This
is done to provide protection from any inadvertent writes.
Therefore, WREN instruction needs to be used before a new
write instruction is issued.
Figure 8. WREN Instruction
CS
0
2
3
4
5
6
7
SCK
0
SI
0
0
0
0
1
1
0
HI-Z
SO
Write Disable (WRDI) Instruction
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ in order to protect the device against inadvertent writes.
This instruction is issued following the falling edge of CS followed
by opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 9. WRDI Instruction
CS
0
1
2
3
4
5
6
7
SCK
SI
SO
Document Number: 001-70382 Rev. *L
1
0
0
0
0
0
1
0
0
HI-Z
Page 11 of 29
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Block Protection
Memory Access
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 5 shows the function of
Block Protect bits.
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the Status Register.
Level
Status Register
Bits
Array Addresses Protected
BP1
BP0
0
0
0
None
1 (1/4)
0
1
0x1800–0x1FFF
2 (1/2)
1
0
0x1000–0x1FFF
3 (All)
1
1
0x0000–0x1FFF
Hardware Write Protection (WP)
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the Status Register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This allows you to install the device in a system
with the WP pin tied to ground, and still write to the Status
Register.
WP pin can be used along with WPEN and Block Protect bits
(BP1 and BP0) of the Status Register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to the Status Register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the Status Register bits, providing hardware
write protection.
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the Status Register.
Note CY14MX064Q2B does not have WP pin and therefore
does not provide hardware write protection.
Table 6 summarizes all the protection features of this device.
Table 6. Write Protection Operation
Unprotected Status
WEN Protected
Blocks
Blocks
Register
WPEN
WP
X
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
LOW
1
Protected
Writable
Protected
1
HIGH
1
Protected
Writable
Writable
Document Number: 001-70382 Rev. *L
The read operations on this device are performed by giving the
instruction on the SI pin and reading the output on SO pin. The
following sequence needs to be followed for a read operation:
After the CS line is pulled LOW to select a device, the read
opcode is transmitted through the SI line followed by two bytes
of address (A12–A0). The most significant address bits
(A15–A13) are don’t cares. After the last address bit is
transmitted on the SI pin, the data (D7–D0) at the specific
address is shifted out on the SO line on the falling edge of SCK
starting with D7. Any other data on SI line after the last address
bit is ignored.
CY14MX064Q allows reads to be performed in bursts through
SPI which can be used to read consecutive addresses without
issuing a new READ instruction. If only one byte is to be read,
the CS line must be driven HIGH after one byte of data comes
out. However, the read sequence may be continued by holding
the CS line LOW and the address is automatically incremented
and data continues to shift out on SO pin. When the last data
memory address (0x1FFF) is reached, the address rolls over to
0x0000 and the device continues to read.
Write Sequence (WRITE) Instruction
The write operations on this device are performed through the SI
pin. To perform a write operation, if the device is write disabled,
then the device must first be write enabled through the WREN
instruction. When the writes are enabled (WEN = ‘1’), WRITE
instruction is issued after the falling edge of CS. A WRITE
instruction constitutes transmitting the WRITE opcode on SI line
followed by two bytes of address (A12–A0) and the data (D7–D0)
which is to be written. The most significant address bits
(A15–A13) are don’t cares.
CY14MX064Q enables writes to be performed in bursts through
SPI which can be used to write consecutive addresses without
issuing a new WRITE instruction. If only one byte is to be written,
the CS line must be driven HIGH after the D0 (LSB of data) is
transmitted. However, if more bytes are to be written, CS line
must be held LOW and address is incremented automatically.
The following bytes on the SI line are treated as data bytes and
written in the successive addresses. When the last data memory
address (0x1FFF) is reached, the address rolls over to 0x0000
and the device continues to write. The WEN bit is reset to ‘0’ on
completion of a WRITE sequence.
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
Page 12 of 29
Not Recommended for New Designs
Table 5. Block Write Protect Bits
Read Sequence (READ) Instruction
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Figure 10. Read Instruction Timing
CS
2
3
4
5
6
0
7
1
2
3
4
5
6
0
0
0
0
0
12 13 14 15
0
1
2
3
4
5
6
7
13-bit Address
Op-Code
SI
7
0
1
1
X
X A12 A11 A10 A9 A8
X
MSB
A3 A2 A1 A0
LSB
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Data
Figure 11. Burst Mode Read Instruction Timing
1
2
3
4
5
6
0
7
1
2
3
4
5
6
7
Op-Code
0
0
0
0
0
0
1
2
3
4
5
6
7
0
7
0
1
2
3
4
5
6
7
13-bit Address
0
1
1
X
X
X A12 A11 A10 A9 A8
MSB
~
~
SI
12 13 14 15
~
~
0
SCK
~
~
CS
A3 A2 A1 A0
LSB
Data Byte N
~
~
Data Byte 1
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
LSB
LSB
Figure 12. Write Instruction Timing
CS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Op-Code
SI
0
0
0
0
0
0
~
~ ~
~
0
SCK
12 13 14 15
0
1
2
3
4
5
6
7
13-bit Address
1
0
X
X
X
12 11 10
9
MSB
SO
Document Number: 001-70382 Rev. *L
8
3
2
1
0
D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
Data
LSB
HI-Z
Page 13 of 29
Not Recommended for New Designs
1
~
~ ~
~
0
SCK
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Figure 13. Burst Mode Write Instruction Timing
CS
3
4
5
6
0
7
1
2
3
4
5
6
7
12 13 14 15
0
1
2
3
4
5
6
7
0
7
0
1
0
0
0
0
1
0
X
X
X A12 A11 A10 A9 A8
MSB
4
5
6
7
~
~
0
13-bit Address
~
~
0
SI
3
Data Byte N
Data Byte 1
Op-Code
2
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
LSB
HI-Z
SO
nvSRAM Special Instructions
CY14MX064Q provides four special instructions which enables
access to the nvSRAM specific functions: STORE, RECALL,
ASDISB, and ASENB. Table 7 lists these instructions.
Figure 15. Software RECALL Operation
Table 7. nvSRAM Special Instructions
Function Name
Opcode
STORE
0011 1100
RECALL
The instruction is performed by transmitting the RECALL opcode
on the SI pin following the falling edge of CS. The WEN bit is
cleared on the positive edge of CS following the RECALL
instruction.
Operation
CS
0
Software STORE
0110 0000
Software RECALL
ASENB
0101 1001
AutoStore Enable
ASDISB
0001 1001
AutoStore Disable
1
2
3
SI
0
1
1
0
0
5
6
7
0
0
0
HI-Z
SO
Software STORE (STORE) Instruction
4
SCK
When a STORE instruction is executed, nvSRAM performs a
Software STORE operation. The STORE operation is performed
irrespective of whether a write has taken place since the last
STORE or RECALL operation.
AutoStore Enable (ASENB) Instruction
To issue this instruction, the device must be write enabled (WEN
bit = ‘1’). The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the STORE
instruction.
To issue this instruction, the device must be write enabled
(WEN = ‘1’). The instruction is performed by transmitting the
ASENB opcode on the SI pin following the falling edge of CS.
The WEN bit is cleared on the positive edge of CS following the
ASENB instruction.
Figure 14. Software STORE Operation
CS
0
1
2
3
4
5
6
7
SCK
SI
SO
The AutoStore Enable instruction enables the AutoStore on
CY14MX064Q2B. This setting is not nonvolatile and needs to be
followed by a STORE sequence to survive the power cycle.
Note If ASDISB and ASENB instructions are executed in
CY14MX064Q2B, the device is busy for the duration of software
sequence processing time (tSS). However, ASDISB and ASENB
instructions have no effect on CY14MX064Q1B as AutoStore is
internally disabled.
Figure 16. AutoStore Enable Operation
0
0
1
1
1
1
0
0
HI-Z
CS
0
1
2
3
4
5
6
7
SCK
Software RECALL (RECALL) Instruction
When a RECALL instruction is executed, nvSRAM performs a
Software RECALL operation. To issue this instruction, the device
must be write enabled (WEN = ‘1’).
Document Number: 001-70382 Rev. *L
SI
SO
0
1
0
1
1
0
0
1
HI-Z
Page 14 of 29
Not Recommended for New Designs
2
~
~
1
~
~
0
SCK
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
AutoStore Disable (ASDISB) Instruction
to the SRAM has been performed since the last STORE or
RECALL cycle.
AutoStore is enabled by default in CY14MX064Q2B. The
ASDISB instruction disables the AutoStore. This setting is not
nonvolatile and needs to be followed by a STORE sequence to
survive the power cycle.
To issue this instruction, the device must be write enabled
(WEN = ‘1’). The instruction is performed by transmitting the
ASDISB opcode on the SI pin following the falling edge of CS.
The WEN bit is cleared on the positive edge of CS following the
ASDISB instruction.
Figure 18. Sleep Mode Entry
t
SLEEP
CS
0
2
3
4
5
6
0
0
0
1
1
0
0
4
5
6
7
0
1
1
1
0
0
1
HI-Z
Serial Number
The serial number is an 8 byte programmable memory space
provided to you uniquely identify this device. It typically consists
of a two byte Customer ID, followed by five bytes of unique serial
number and one byte of CRC check. However, nvSRAM does
not calculate the CRC and it is up to the system designer to utilize
the eight byte memory space in whatever manner desired. The
default value for eight byte locations are set to ‘0x00’.
1
HI-Z
SO
1
SO
7
SCK
SI
3
Special Instructions
SLEEP Instruction
WRSN (Serial Number Write) Instruction
SLEEP instruction puts the nvSRAM in sleep mode. When the
SLEEP instruction is issued, the nvSRAM takes tSS time to
process the SLEEP request. Once the SLEEP command is
successfully registered and processed, the nvSRAM performs a
STORE operation to secure the data to nonvolatile memory and
then enters into SLEEP mode. The device starts consuming IZZ
current after tSLEEP time from the instance when SLEEP
instruction is registered. The device is not accessible for normal
operations after SLEEP instruction is issued. Once in sleep
mode, the SCK and SI pins are ignored and SO will be Hi-Z but
device continues to monitor the CS pin.
To wake the nvSRAM from the sleep mode, the device must be
selected by toggling the CS pin from HIGH to LOW. The device
wakes up and is accessible for normal operations after tWAKE
duration after a falling edge of CS pin is detected.
The serial number can be written using the WRSN instruction. To
write serial number the write must be enabled using the WREN
instruction. The WRSN instruction can be used in burst mode to
write all the 8 bytes of serial number.
The serial number is locked using the SNL bit of the Status
Register. Once this bit is set to ‘1’, no modification to the serial
number is possible. After the SNL bit is set to ‘1’, using the
WRSN instruction has no effect on the serial number.
A STORE operation (AutoStore or Software STORE) is required
to store the serial number in nonvolatile memory. If AutoStore is
disabled, you must perform a Software STORE operation to
secure and lock the serial Number. If SNL bit is set to ‘1’ and is
not stored (AutoStore disabled), the SNL bit and serial number
defaults to ‘0’ at the next power cycle. If SNL bit is set to ‘1’ and
is stored, the SNL bit can never be cleared to ‘0’. This instruction
requires the WEN bit to be set before it can be executed. The
WEN bit is reset to ‘0’ after completion of this instruction.
Note Whenever nvSRAM enters into sleep mode, it initiates
nonvolatile STORE cycle which results in an endurance cycle per
sleep command execution. A STORE cycle starts only if a write
Figure 19. WRSN Instruction
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI
1
1
0
0
0
0
1
0
Document Number: 001-70382 Rev. *L
Byte - 1
D7 D6 D5 D4 D3 D2 D1 D0
MSB
SO
56 57 58 59 60 61 62 63
Byte - 8
Op-Code
~
~
0
SCK
~
~
CS
D7 D6 D5 D4 D3 D2 D1 D0
8-Byte Serial Number
LSB
HI-Z
Page 15 of 29
Not Recommended for New Designs
SI
CS
1
2
SCK
Figure 17. AutoStore Disable Operation
0
1
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
RDSN (Serial Number Read) Instruction
the device does not loop back. RDSN instruction can be issued
by shifting the op-code for RDSN in through the SI pin of
nvSRAM after CS goes LOW. This is followed by nvSRAM
shifting out the eight bytes of serial number through the SO pin.
The serial number is read using RDSN instruction. A serial
number read may be performed in burst mode to read all the
eight bytes at once. After the last byte of serial number is read,
Figure 20. RDSN Instruction
CS
1
2
1
1
0
3
4
5
6
7
0
1
2
3
4
5
6
7
56 57 58 59 60 61 62 63
~
~
0
SCK
0
0
0
1
1
Byte - 1
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
~
~
Byte - 8
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0
LSB
8-Byte Serial Number
Device ID
Device ID is 4-byte read only code identifying a type of product uniquely. This includes the product family code, configuration and
density of the product.
Table 8. Device ID
Device ID description
Device
Device ID
(4 bytes)
31–21
(11 bits)
20–7
(14 bits)
6–3
(4 bits)
2–0
(3 bits)
Manufacture ID
Product ID
Density ID
Die Rev
CY14MB064Q1B
0x06810889
00000110100
00001000010001
0001
001
CY14MB064Q2B
0x06818809
00000110100
00001100010000
0001
001
CY14ME064Q1B
0x06811089
00000110100
00001000100001
0001
001
CY14ME064Q2B
0x06819009
00000110100
00001100100000
0001
001
The device ID is divided into four parts as shown in Table 8:
2. Product ID (14 bits)
1. Manufacturer ID (11 bits)
The product ID is defined as shown in the Table 8.
This is the JEDEC assigned manufacturer ID for Cypress.
JEDEC assigns the manufacturer ID in different banks. The first
three bits of the manufacturer ID represent the bank in which ID
is assigned. The next eight bits represent the manufacturer ID.
3. Density ID (4 bits)
Cypress’s manufacturer ID is 0x34 in bank 0. Therefore the
manufacturer ID for all Cypress nvSRAM products is:
Cypress ID - 000_0011_0100
Document Number: 001-70382 Rev. *L
The 4 bit density ID is used as shown in Table 8 for indicating the
64 Kb density of the product.
4. Die Rev (3 bits)
This is used to represent any major change in the design of the
product.
The die rev is defined as shown in the Table 8.
Page 16 of 29
Not Recommended for New Designs
Op-Code
SI
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
RDID (Device ID Read) Instruction
This instruction is used to read the JEDEC assigned
manufacturer ID and product ID of the device. This instruction
can be used to identify a device on the bus. RDID instruction can
be issued by shifting the op-code for RDID in through the SI pin
of nvSRAM after CS goes LOW. This is followed by nvSRAM
shifting out the four bytes of device ID through the SO pin.
Figure 21. RDID instruction
CS
0 1
2
3 4
5
6
7 0 1
2
3 4
5
6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Op-Code
1 0 0 1 1 1 1
1
Byte - 4
SO
HI-Z
Byte - 3
Byte - 2
Byte - 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
4-Byte Device ID
HOLD Pin Operation
This pin can be used by the master with the CS pin to pause the
serial communication by bringing the pin HOLD LOW and
deselecting an SPI slave to establish communication with
another slave device, without the serial communication being
reset. The communication may be resumed at a later point by
selecting the device and setting the HOLD pin HIGH.
Document Number: 001-70382 Rev. *L
Figure 22. HOLD Operation
CS
SCK
~
~
~ ~
The HOLD pin is used to pause the serial communication. When
the device is selected and a serial sequence is underway, HOLD
is used to pause the serial communication with the master device
without resetting the ongoing serial sequence. To pause, the
HOLD pin must be brought LOW when the SCK pin is LOW. To
resume serial communication, the HOLD pin must be brought
HIGH when the SCK pin is LOW (SCK may toggle during HOLD).
While the device serial communication is paused, inputs to the
SI pin are ignored and the SO pin is in the high impedance state.
HOLD
SO
Page 17 of 29
Not Recommended for New Designs
SI
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Supply voltage on VCC relative to VSS
CY14MB064Q: VCC = 2.7 V to 3.6 V ...........–0.5 V to +4.1 V
CY14ME064Q: VCC = 4.5 V to 5.5 V ...........–0.5 V to +7.0 V
DC voltage applied to outputs
in High Z state .................................... –0.5 V to VCC + 0.5 V
Input voltage ....................................... –0.5 V to VCC + 0.5 V
Package power dissipation capability
(TA = 25 °C) ................................................................. 1.0 W
Surface mount lead soldering temperature
(3 seconds) .............................................................. +260 °C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Device
CY14MB064Q
Ambient
Temperature
Range
Industrial
VCC
–40 °C to +85 °C 2.7 V to 3.6 V
CY14ME064Q
4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VCC
ICC1
Min
Typ [3]
Max
Unit
CY14MB064Q
2.7
3.0
3.6
V
CY14ME064Q
4.5
5.0
5.5
V
fSCK = 40 MHz; Values obtained CY14MB064Q
without output loads
CY14ME064Q
(IOUT = 0 mA)
–
–
3
mA
–
–
4
mA
Description
Test Conditions
Power supply
Average VCC current
ICC2
Average VCC current during
STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
3
mA
ICC3
Average VCC current,
fSCK = 1 MHz,
VCC = VCC(Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA)
–
–
1
mA
ICC4
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current for duration
tSTORE
–
–
3
mA
ISB
VCC standby current
CY14MB064Q
CS > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
CY14ME064Q
Standby current level after
nonvolatile cycle is complete.
Inputs are static. fSCK = 0 MHz.
–
–
120
A
–
–
150
A
tSLEEP time after SLEEP Instruction is registered.
All inputs are static and configured at CMOS logic
level.
–
–
8
A
IZZ
Sleep mode current
Note
3. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested.
Document Number: 001-70382 Rev. *L
Page 18 of 29
Not Recommended for New Designs
Storage temperature ................................ –65 °C to +150 °C
Maximum accumulated storage time
At 150 °C ambient temperature ...................... 1000 h
At 85 °C ambient temperature .................... 20 Years
Maximum junction temperature ................................. 150 °C
Transient voltage (< 20 ns)
on any pin to ground potential ............ –2.0 V to VCC + 2.0 V
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min
Typ [3]
Max
Unit
IIX
Input leakage current
–1
–
+1
A
IOZ
Off-state output leakage
current
–1
–
+1
A
VIH
Input HIGH voltage
2.0
–
VCC + 0.5
V
VIL
Input LOW voltage
Vss – 0.5
–
0.8
V
VOH
Output HIGH Voltage
2.4
–
–
V
–
–
–
0.4
V
42
47
180
F
CY14MB064Q
–
–
VCC
V
CY14ME064Q
–
–
VCC– 0.5
VOL
[4]
VCAP
VVCAP
[5, 6]
IOUT = –2 mA
CY14MB064Q
Output LOW voltage
IOUT = 4 mA
CY14ME064Q VCC – 0.4
–
Storage capacitor
Between VCAP pin and VSS
Maximum voltage driven on
VCAP pin by the device
VCC = Max
Notes
4. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor
on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore
it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options.
5. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating
temperature range should be higher than the VVCAP voltage.
6. These parameters are guaranteed by design and are not tested.
Document Number: 001-70382 Rev. *L
Page 19 of 29
Not Recommended for New Designs
Over the Operating Range
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Data Retention and Endurance
Over the Operating Range
Parameter
Description
DATAR
Data retention
NVC
Nonvolatile STORE operations
Min
Unit
20
Years
1,000
K
Max
Unit
7
pF
7
pF
Test Conditions
8-pin SOIC
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
101.08
C/W
37.86
C/W
Parameter [7]
Description
CIN
Input capacitance
COUT
Output pin capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(Typ)
Thermal Resistance
Parameter [7]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 23. AC Test Loads and Waveforms
For 3 V (CY14MB064Q1B/CY14MB064Q2B):
577
577
3.0 V
3.0 V
R1
For Tri-state specs
R1
OUTPUT
OUTPUT
R2
789
30 pF
R2
789
5 pF
For 5 V (CY14ME064Q1B/CY14ME064Q2B):
963
963
5.0 V
5.0 V
R1
For Tri-state specs
R1
OUTPUT
OUTPUT
30 pF
R2
512
5 pF
R2
512
AC Test Conditions
Input pulse levels.................................................... 0 V to 3 V
Input rise and fall times (10% to 90%)......................... < 3 ns
Input and output timing reference levels........................ 1.5 V
Note
7. These parameters are guaranteed by design and are not tested.
Document Number: 001-70382 Rev. *L
Page 20 of 29
Not Recommended for New Designs
Capacitance
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
AC Switching Characteristics
Over the Operating Range
Parameters [8]
Alt. Parameter
Min
Max
Unit
fSCK
fSCK
Clock frequency, SCK
–
40
MHz
tCL[9]
tCH[9]
tWL
Clock pulse width LOW
11
–
ns
tWH
Clock pulse width HIGH
11
–
ns
tCS
tCE
CS HIGH time
20
–
ns
tCSS
tCES
CS setup time
10
–
ns
tCSH
tCEH
CS hold time
10
–
ns
tSD
tSU
Data in setup time
5
–
ns
tHD
tH
Data in hold time
5
–
ns
tHH
tHD
HOLD hold time
5
–
ns
tSH
tCD
HOLD setup time
5
–
ns
tCO
tV
Output Valid
–
9
ns
tHHZ[9]
tHLZ[9]
tHZ
HOLD to output HIGH Z
–
15
ns
tLZ
HOLD to output LOW Z
–
15
ns
tOH
tHO
Output hold time
0
–
ns
tHZCS[9]
tDIS
Output disable time
–
20
ns
Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 23.
9. These parameters are guaranteed by design and are not tested.
Document Number: 001-70382 Rev. *L
Page 21 of 29
Not Recommended for New Designs
Cypress
Parameter
40 MHz
Description
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Switching Waveforms
Figure 24. Synchronous Data Timing (Mode 0)
tCS
CS
tCSS
tCH
tCL
tCSH
SCK
SI
tHD
VALID IN
VALID IN
VALID IN
tOH
tCO
SO
HI-Z
tHZCS
HI-Z
~
~
~ ~
Figure 25. HOLD Timing
CS
SCK
tHH
tHH
tSH
tSH
HOLD
tHHZ
tHLZ
SO
Document Number: 001-70382 Rev. *L
Page 22 of 29
Not Recommended for New Designs
tSD
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
AutoStore or Power-Up RECALL
Over the Operating Range
CY14MX064Q
Description
Unit
Min
Max
Power-Up RECALL duration
–
20
ms
STORE cycle duration
–
8
ms
tDELAY [12, 13]
Time allowed to complete SRAM write cycle
–
25
ns
VSWITCH
Low voltage trigger level
CY14MB064Q
–
2.65
V
CY14ME064Q
–
4.40
V
150
–
s
tFA [10]
tSTORE
[11]
tVCCRISE
[13]
VCC rise time
tWAKE
Time for nvSRAM to wake up from SLEEP mode
–
20
ms
tSLEEP
Time to enter SLEEP mode after issuing SLEEP instruction
–
8
ms
Time to enter into standby mode after CS going HIGH
–
100
µs
tSB
[13]
Switching Waveforms
Figure 26. AutoStore or Power-Up RECALL [14]
VCC
VSWITCH
t VCCRISE
Note
11
11
t STORE
Note
tSTORE
AutoStore
tDELAY
tDELAY
POWERUP
RECALL
tFA
tFA
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
10. tFA starts from the time VCC rises above VSWITCH.
11. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore is not initiated.
12. On a Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.
13. These parameters are guaranteed by design and are not tested.
14. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
Document Number: 001-70382 Rev. *L
Page 23 of 29
Not Recommended for New Designs
Parameter
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Software Controlled STORE and RECALL Cycles
Over the Operating Range
Parameter
CY14MX064Q
Description
Min
Max
Unit
tRECALL
RECALL duration
–
600
s
tSS [15, 16]
Soft sequence processing time
–
500
s
Figure 27. Software STORE Cycle [16]
CS
CS
0
1
2
3
4
5
6
7
0
SCK
SI
Figure 28. Software RECALL Cycle [16]
1
2
3
4
5
6
7
SCK
0
0
1
1
1
1
0
0
SI
0
1
1
0
0
0
0
0
tRECALL
tSTORE
HI-Z
RWI
RDY
RDY
Figure 29. AutoStore Enable Cycle
CS
0
1
2
3
4
5
6
Figure 30. AutoStore Disable Cycle
CS
7
0
SCK
SI
HI-Z
RWI
1
2
3
4
5
6
7
SCK
0
1
0
1
1
0
0
1
SI
0
0
0
1
1
0
0
1
tSS
RWI
tSS
HI-Z
RDY
RWI
HI-Z
RDY
Notes
15. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
16. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document Number: 001-70382 Rev. *L
Page 24 of 29
Not Recommended for New Designs
Switching Waveforms
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Ordering Information
Package
Diagram
Ordering Code
CY14MB064Q2B-SXI
Operating
Range
Package Type
51-85066 8-pin SOIC (with VCAP)
CY14MB064Q2B-SXIT
Industrial
8-pin SOIC (with VCAP)
The above part is Pb-free. This table contains final information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
Not Recommended for New Designs
CY 14 M B 064 Q 2 B - S X I T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
I - Industrial (–40 °C to 85 °C)
Pb-free
Package:
S - 8-pin SOIC
Die revision:
Blank - No Rev
B - 2nd Rev
1 - With WP
2 - With VCAP
Q - Serial (SPI) nvSRAM
Density:
064 - 64 Kb
Metering
Voltage:
B - 3.0 V
E - 5.0 V
14 - nvSRAM
Cypress
Document Number: 001-70382 Rev. *L
Page 25 of 29
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Package Diagrams
Not Recommended for New Designs
Figure 31. 8-pin SOIC (150 Mils) Package Outline, 51-85066
51-85066 *I
Document Number: 001-70382 Rev. *L
Page 26 of 29
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Acronym
Document Conventions
Description
Units of Measure
CPHA
Clock Phase
CPOL
Clock Polarity
°C
degree Celsius
CMOS
Complementary Metal Oxide Semiconductor
Hz
hertz
CRC
Cyclic Redundancy Check
kHz
kilohertz
EEPROM
Electrically Erasable Programmable Read-Only
Memory
k
kilohm
MHz
megahertz
EIA
Electronic Industries Alliance
A
microampere
I/O
Input/Output
mA
milliampere
JEDEC
Joint Electron Devices Engineering Council
F
microfarad
LSB
Least Significant Bit
s
microsecond
MSB
Most Significant Bit
ms
millisecond
nvSRAM
nonvolatile Static Random Access Memory
ns
nanosecond
RWI
Read and Write Inhibit
ohm
RoHS
Restriction of Hazardous Substances
%
percent
SNL
Serial Number Lock
pF
picofarad
SPI
Serial Peripheral Interface
V
volt
W
watt
SONOS
Silicon-Oxide-Nitride-Oxide Semiconductor
SOIC
Small Outline Integrated Circuit
SRAM
Static Random Access Memory
Document Number: 001-70382 Rev. *L
Symbol
Unit of Measure
Not Recommended for New Designs
Acronyms
Page 27 of 29
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Document History Page
Document Title: CY14MB064Q1B/CY14MB064Q2B/CY14ME064Q1B/CY14ME064Q2B, 64-Kbit (8K × 8) SPI nvSRAM
Document Number: 001-70382
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
3291153
GVCH
06/23/2011
New data sheet.
*A
3403128
GVCH
10/12/2011
Updated SPI Operating Features:
Updated Power-Up:
Updated description.
Updated SPI Functional Description:
Updated Table 2.
Updated Special Instructions:
Updated SLEEP Instruction:
Updated description.
Updated Figure 18.
*B
3514367
GVCH
02/01/2012
Removed Best Practices.
Updated Ordering Information:
Updated part numbers.
*C
3539393
GVCH
03/16/2012
Updated AutoStore or Power-Up RECALL:
Referred Note 13 in tSB parameter.
*D
3605955
GVCH
05/02/2012
No technical updates.
*E
3702613
GVCH
08/03/2012
Updated DC Electrical Characteristics:
Added VVCAP parameter and its details.
Added Note 5 and referred the same note in VVCAP parameter.
Referred Note 6 in VVCAP parameter.
*F
3759535
GVCH
09/28/2012
Updated Maximum Ratings:
Removed “Ambient temperature with power applied” and its corresponding
details.
Added “Maximum junction temperature” and its corresponding details.
*G
3823702
GVCH
11/28/2012
Changed status from Preliminary to Final.
Updated Ordering Information:
Updated part numbers.
*H
3988751
GVCH
05/06/2013
Updated Package Diagrams:
spec 51-85066 – Changed revision from *E to *F.
Completing Sunset Review.
*I
4108522
GVCH
08/29/2013
Added watermark “Not Recommended for New Designs” across the document.
Updated to new template.
*J
4568786
GVCH
11/11/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Updated part numbers.
*K
6276095
GVCH
08/08/2018
Removed watermark “Not Recommended for New Designs” across the
document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *F to *I.
Updated to new template.
*L
6577088
GVCH
05/27/2019
Added watermark “Not Recommended for New Designs” across the document.
Updated to new template.
Document Number: 001-70382 Rev. *L
Page 28 of 29
Not Recommended for New Designs
Description of Change
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2011–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
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reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
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the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
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responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-70382 Rev. *L
Revised May 27, 2019
Page 29 of 29
Not Recommended for New Designs
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