CY14V101NA

CY14V101LA CY14V101NA 1-Mbit (128 K × 8/64 K × 16) nvSRAM 1-Mbit (128 K × 8/64 K × 16) nvSRAM Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The Cypress CY14V101LA/CY14V101NA is a fast static RAM, with a non-volatile element in each memory cell. The memory is organized as 128 K bytes of 8 bits each or 64 K words of 16 bits each. The embedded non-volatile elements incorporate QuantumTrap technology, producing the world’s most reliable non-volatile memory. The SRAM provides infinite read and write cycles, while independent non-volatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the non-volatile elements (the STORE operation) takes place automatically at power down. On power-up, data is restored to the SRAM (the RECALL operation) from the non-volatile memory. Both the STORE and RECALL operations are also available under software control. 25 ns and 45 ns access times Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16 (CY14V101NA) Hands off automatic STORE on power down with only a small capacitor STORE to QuantumTrap non-volatile elements initiated by software, device pin, or AutoStore on power down RECALL to SRAM initiated by software or power up Infinite read, write, and recall cycles 1 million STORE cycles to QuantumTrap 20 year data retention Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V Industrial temperature 48-ball fine-pitch ball grid array (FBGA) package Pb-free and restriction of hazardous substances (RoHS) compliance Logic Block Diagram [1, 2, 3] A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 R O W D E C O D E R Quatrum Trap 1024 X 1024 STORE RECALL STATIC RAM ARRAY 1024 X 1024 STORE/RECALL CONTROL HSB VCC VCCQ VCAP POWER CONTROL SOFTWARE DETECT A14 - A2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0 A1 A2 A3 A4 A10 A11 CE BLE I N P U T B U F F E R S COLUMN I/O COLUMN DEC OE WE BHE Notes 1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration. 2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 3. BHE and BLE are applicable for × 16 configuration only. Cypress Semiconductor Corporation Document #: 001-53953 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 4, 2011 [+] Feedback CY14V101LA CY14V101NA Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Device Operation .............................................................. 4 SRAM Read ....................................................................... 4 SRAM Write ....................................................................... 4 AutoStore Operation ........................................................ 4 Hardware STORE Operation ............................................ 4 Hardware RECALL (Power-Up) ....................................... 5 Software STORE ............................................................... 5 Software RECALL ............................................................. 5 Preventing AutoStore ....................................................... 6 Data Protection ................................................................. 6 Noise Considerations ....................................................... 6 Best Practices ................................................................... 7 Maximum Ratings ............................................................. 8 Operating Range ............................................................... 8 DC Electrical Characteristics .......................................... 8 Data Retention and Endurance ....................................... 9 Capacitance ...................................................................... 9 Thermal Resistance .......................................................... 9 AC Test Loads ................................................................ 10 AC Test Conditions ........................................................ 10 AC Switching Characteristics ....................................... 11 SRAM Read Cycle .................................................... 11 SRAM Write Cycle ..................................................... 11 Switching Waveforms .................................................... 11 AutoStore/Power-up RECALL ....................................... 14 Switching Waveforms .................................................... 14 Software Controlled STORE/RECALL Cycle ................ 15 Switching Waveforms .................................................... 15 Hardware STORE Cycle ................................................. 16 Switching Waveforms .................................................... 16 Truth Table For SRAM Operations ................................ 17 Ordering Information ...................................................... 18 Ordering Code Definitions ......................................... 18 Package Diagrams .......................................................... 19 Acronyms ........................................................................ 20 Document Conventions ................................................. 20 Units of Measure ....................................................... 20 Document History Page ................................................. 21 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC Solutions ......................................................... 22 Document #: 001-53953 Rev. *H Page 2 of 22 [+] Feedback CY14V101LA CY14V101NA Pinouts Figure 1. Pin Diagram – 48-ball FBGA (× 8) (× 16) Top View (not to scale) 1 NC NC DQ0 VSS VCCQ DQ3 NC [5] NC Top View (not to scale) 6 VCC NC DQ4 VCCQ VSS DQ7 NC NC [6] 2 OE NC NC DQ1 DQ2 NC HSB A8 3 A0 A3 A5 [4] NC 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE NC DQ5 DQ6 NC WE A11 1 A B C D E F G H 2 OE BHE 3 A0 A3 A5 4 A1 A4 A6 A7 5 A2 CE DQ1 6 VCC DQ0 DQ2 A B C D E F G H BLE DQ8 DQ9 DQ10 VSS [5] DQ11 NC DQ3 VCCQ VSS DQ6 DQ7 NC VCAP A14 A12 A9 VCCQ DQ12 DQ14 DQ13 DQ15 HSB NC [6] [4] VCAP NC DQ4 A14 A 12 A9 A15 A13 A10 DQ5 WE A11 A8 Pin Definitions Pin Name I/O Type Description Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for × 8 configuration. A0–A16 Input A0–A15 Address inputs. Used to select one of the 65,536 words of the nvSRAM for × 16 configuration. Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation. DQ0–DQ7 Input/Output DQ0–DQ15 Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation. WE Input Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. Input Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. CE Input Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles. OE I/O pins are tri-stated on deasserting OE HIGH. Input Byte high enable, active LOW. Controls DQ15–DQ8. BHE Input Byte low enable, active LOW. Controls DQ7–DQ0. BLE VSS Ground Ground for the device. Must be connected to the ground of the system. VCC Power supply Power supply inputs to the core of the device. VCCQ Power supply Power supply inputs for the inputs and outputs of the device. HSB Input/Output Hardware STORE busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress. When pulled LOW, external to the chip, it initiates a non-volatile STORE operation. After each hardware and software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional). Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to non-volatile elements. No connect No connect. This pin is not connected to the die. VCAP NC Notes 4. Address expansion for 2-Mbit. NC pin not connected to die. 5. Address expansion for 4-Mbit. NC pin not connected to die. 6. Address expansion for 8-Mbit. NC pin not connected to die. Document #: 001-53953 Rev. *H Page 3 of 22 [+] Feedback CY14V101LA CY14V101NA Device Operation The CY14V101LA/CY14V101NA nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a non-volatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the non-volatile cell (the STORE operation), or from the non-volatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14V101LA/CY14V101NA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the non-volatile cells and up to 1 million STORE operations. Refer to the Truth Table For SRAM Operations on page 17 for a complete description of read and write modes. AutoStore on page 6. If AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This corrupts the data stored in nvSRAM. Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical Characteristics on page 8 for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. Place a pull-up on WE to hold it inactive during power up. This pull-up is only effective if the WE signal is tristate during power up. Many MPUs tristate their controls on power-up. This must be verified when using the pull-up. When the nvSRAM comes out of power-on-RECALL, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary non-volatile stores, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 2. AutoStore Mode VCCQ VCC SRAM Read The CY14V101LA/CY14V101NA performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0–16 or A0–15 determines which of the 131,072 data bytes or 65,536 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. 0.1 uF 10 kOhm VCCQ VCC 0.1 uF SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–15 are written into the memory if the data is valid tSD before the end of a WE-controlled write or before the end of a CE-controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. WE VCAP VCAP VSS AutoStore Operation The CY14V101LA/CY14V101NA stores data to the nvSRAM using one of the following three storage operations: Hardware STORE activated by HSB; Software STORE activated by an address sequence; AutoStore on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14V101LA/CY14V101NA. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Note If a capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing Document #: 001-53953 Rev. *H Hardware STORE Operation The CY14V101LA/CY14V101NA provides the HSB pin to control and acknowledge the STORE operations. Use the HSB pin to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14V101LA/CY14V101NA conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k pull-up resistor. Page 4 of 22 [+] Feedback CY14V101LA CY14V101NA SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14V101LA/CY14V101NA. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the CY14V101LA/CY14V101NA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used. To initiate the Software STORE cycle, the following read sequence must be performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8FC0 Initiate STORE Cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Hardware RECALL (Power-Up) During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB is driven LOW by the HSB driver. Software RECALL Data is transferred from the non-volatile memory to the SRAM by a software address sequence. A Software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, the following sequence of CE or OE controlled read operations must be performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the non-volatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the non-volatile elements. Software STORE Data is transferred from the SRAM to the non-volatile memory by a software address sequence. The CY14V101LA/CY14V101NA Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous non-volatile data is first performed, followed by a program of the non-volatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. Table 1. Mode Selection CE H L L L WE X H L H OE X L X L BHE, BLE[7] X L L X A15–A0[8] X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Mode Not selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable I/O Output High Z Output data Input data Output data Output data Output data Output data Output data Output data Power Standby Active Active Active[9] Notes 7. BHE and BLE are applicable for x16 configuration only. 8. While there are 17 address lines on the CY14V101LA (16 address lines on the CY14V101NA), only the 13 address lines (A14–A2) are used to control software modes. Rest of the address lines are don’t care. 9. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle. Document #: 001-53953 Rev. *H Page 5 of 22 [+] Feedback CY14V101LA CY14V101NA Table 1. Mode Selection (continued) CE L WE H OE L BHE, BLE[7] X A15–A0[8] 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Non-volatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Non-volatile RECALL I/O Output data Output data Output data Output data Output data Output data Power Active[10] L H L X Active ICC2[10] Output data Output data Output data Output data Output data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Active[10] L H L X Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is reenabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the Software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or reenabled, a manual STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled. Data Protection The CY14V101LA/CY14V101NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14V101LA/CY14V101NA is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). When VCCQ < VIODIS, I/Os are disabled (no STORE takes place). This protects against inadvertent writes during brown out conditions on VCCQ supply. Noise Considerations Refer to CY application note AN1064. Note 10. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle. Document #: 001-53953 Rev. *H Page 6 of 22 [+] Feedback CY14V101LA CY14V101NA Best Practices nvSRAM products have been used effectively for over 26 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ ■ The non-volatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. Power up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autoStore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this maximum VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period. ■ Document #: 001-53953 Rev. *H Page 7 of 22 [+] Feedback CY14V101LA CY14V101NA Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................–65 C to +150 C Maximum accumulated storage time: At 150 C ambient temperature ...................... 1000 h At 85 C ambient temperature ..................... 20 Years Ambient temperature with power applied ...................................–55 C to +150 C Supply voltage on VCC relative to VSS .......... –0.5 V to 4.1 V Supply voltage on VCCQ relative to VSS ...... –0.5 V to 2.45 V Voltage applied to outputs in High Z State .................................. –0.5 V to VCCQ + 0.5 V Input voltage ..................................... –0.5 V to VCCQ + 0.5 V Transient voltage (< 20 ns) on any pin to ground potential ............... –2.0 V to VCCQ + 2.0 V Package power dissipation capability (TA = 25 °C) ..................................................1.0 W Surface mount Pb soldering temperature (3 seconds) ..........................................+260 C DC output current (1 output at a time, 1s duration) ..................................15 mA Static discharge voltage (per MIL-STD-883, Method 3015) ......................... > 2001 V Latch up current ................................................... > 140 mA Operating Range Range Industrial Ambient Temperature VCC VCCQ –40 C to +85 C 3.0 V to 3.6 V 1.65 V to 1.95 V DC Electrical Characteristics Over the Operating Range Parameter VCC VCCQ ICC1 ICCQ1 ICC2 ICC3 ICCQ3 ICC4 ISB Average VCC current Average VCCQ current Average VCC current during STORE Average VCC current at tRC= 200 ns, VCC(Typ), 25 °C Average VCCQ current at tRC= 200 ns, VCCQ(Typ), 25 °C Average VCAP current during AutoStore cycle VCC standby current tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) All inputs don’t care, VCC = Max Average current for duration tSTORE All inputs cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA) All inputs don’t care. Average current for duration tSTORE CE > (VCCQ – 0.2 V). VIN < 0.2 V or > (VCCQ – 0.2 V). Standby current level after non-volatile cycle is complete. Inputs are static. f = 0 MHz VCCQ = Max, VSS < VIN < VCCQ VCCQ = Max, VSS < VIN < VCCQ Description Power supply voltage Test Conditions Min 3.0 1.65 – – – – – – – – – Typ [11] 3.3 1.8 – – – – – 35 5 – – Max 3.6 1.95 70 52 25 15 10 – – 8 8 Unit V V mA mA mA mA mA mA mA mA mA IIX[12] Input leakage current (except HSB) Input leakage current (for HSB) –1 –100 – – +1 +1 µA µA Notes 11. Typical values are at 25 °C, VCC = VCC(Typ) and VCCQ= VCCQ(Typ). Not 100% tested. 12. The HSB pin has IOUT = –4 µA for VOH of 1.07 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. Document #: 001-53953 Rev. *H Page 8 of 22 [+] Feedback CY14V101LA CY14V101NA DC Electrical Characteristics (continued) Over the Operating Range Parameter IOZ Description Test Conditions Min –1 Typ [11] – Max +1 Unit µA Off-state output leakage current VCCQ = Max, VSS < VOUT < VCCQ, CE or OE > VIH or BHE/BLE > VIH or WE < VIL VIH VIL VOH VOL VCAP[13] Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage Storage capacitor – – IOUT = –1 mA IOUT = 2 mA Between VCAP pin and VSS, 5 V Rated 0.7 VCCQ – 0.3 VCCQ – 0.45 – 61 – – – – 68 VCCQ + 0.3 0.3 VCCQ – 0.45 180 V V V V µF Data Retention and Endurance Parameter DATAR NVC Data retention Non-volatile STORE operations Description Min 20 1,000 Unit Years K Capacitance Parameter[14] CIN Description Input capacitance (except BHE, BLE and HSB) Input capacitance (for BHE, BLE and HSB) COUT Output capacitance (except HSB) Output capacitance (for HSB) Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(Typ), VCCQ = VCCQ(Typ) Max 7 8 7 8 Unit pF pF pF pF Thermal Resistance Parameter[14] Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 48-ball FBGA Unit 48.19 6.5 C/W C/W JA JC Notes 13. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options. 14. These parameters are guaranteed by design and are not tested. Document #: 001-53953 Rev. *H Page 9 of 22 [+] Feedback CY14V101LA CY14V101NA AC Test Loads Figure 3. AC Test Loads 1.8 V OUTPUT 30 pF 450  R1 R2 450  1.8 V OUTPUT 5 pF 450  R1 for tri-state specs R2 450  AC Test Conditions Input pulse levels................................................. 0 V to 1.8 V Input rise and fall times (10% to 90%)...................... < 1.8 ns Input and output timing reference levels ....................... 0.9 V Document #: 001-53953 Rev. *H Page 10 of 22 [+] Feedback CY14V101LA CY14V101NA AC Switching Characteristics Over the Operating Range Parameters [15] Cypress Alt Parameters Parameters SRAM Read Cycle tACE tACS [16] tRC tRC tAA[17] tDOE tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS 25 ns Description Min – 25 – – 3 3 – 0 – 0 – – 0 – 25 20 20 10 0 20 0 0 – 3 20 Max 25 – 25 12 – – 10 – 10 – 25 12 – 10 – – – – – – – – 10 – – Min – 45 – – 3 3 – 0 – 0 – – 0 – 45 30 30 15 0 30 0 0 – 3 30 45 ns Max 45 – 45 20 – – 15 – 15 – 45 20 – 15 – – – – – – – – 15 – – Unit Chip enable access time Read cycle time Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active Output disable to output inactive Chip enable to power active Chip disable to power standby Byte enable to data valid Byte enable to output active Byte disable to output inactive Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Output active after end of write Byte enable to end of write ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tLZCE[18, 19] tHZCE[18, 19] tLZOE[18, 19] tHZOE[18, 19] tPU[18] tPD[18] tDBE[[18] tLZBE[18] tHZBE[18] tOHA[17] – – – SRAM Write Cycle tWC tWC tPWE tWP tCW tSCE tSD tDW tHD tDH tAW tAW tSA tAS tHA tWR [18, 19, 20] t tHZWE WZ tLZWE[18, 19] tBW – tOW Switching Waveforms Figure 4. SRAM Read Cycle #1 (Address Controlled) [16, 17, 21] tRC Address Address Valid tAA Data Output Previous Data Valid tOHA Notes 15. Test conditions assume signal transition time of 1.8 ns or less, timing reference levels of VCCQ/2, input pulse levels of 0 to VCC Q(typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 3 on page 10. 16. WE must be HIGH during SRAM read cycles. 17. Device is continuously selected with CE, OE and BHE / BLE LOW. 18. These parameters are guaranteed by design and are not tested. 19. Measured ±200 mV from steady state output voltage. 20. If WE is low when CE goes low, the outputs remain in the high-impedance state. 21. HSB must remain HIGH during READ and WRITE cycles. Output Data Valid Document #: 001-53953 Rev. *H Page 11 of 22 [+] Feedback CY14V101LA CY14V101NA Switching Waveforms (continued) Figure 5. SRAM Read Cycle #2 (CE and OE Controlled) [22, 23, 24] Address Address Valid tRC tACE CE tAA tLZCE OE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance tPU ICC Standby Active Output Data Valid tPD tDOE tHZBE tHZOE tHZCE Figure 6. SRAM Write Cycle #1 (WE Controlled) [22, 24, 25, 26] tWC Address Address Valid tSCE CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input tHZWE Data Output Previous Data tHD Input Data Valid tLZWE High Impedance tHA Notes 22. BHE and BLE are applicable for × 16 configuration only. 23. WE must be HIGH during SRAM read cycles. 24. HSB must remain HIGH during READ and WRITE cycles. 25. If WE is low when CE goes low, the outputs remain in the high impedance state. 26. CE or WE must be > VIH during address transitions. Document #: 001-53953 Rev. *H Page 12 of 22 [+] Feedback CY14V101LA CY14V101NA Switching Waveforms (continued) Figure 7. SRAM Write Cycle #2 (CE Controlled) [27, 28, 29, 30] tWC Address tSA CE tBW BHE, BLE tPWE WE tSD Data Input Data Output Input Data Valid High Impedance tHD Address Valid tSCE tHA Figure 8. SRAM Write Cycle #3 (BHE and BLE Controlled) [27, 28, 29, 30] tWC Address tSCE CE tSA BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output tBW tHA Address Valid Notes 27. BHE and BLE are applicable for x16 configuration only. 28. HSB must remain HIGH during READ and WRITE cycles. 29. If WE is low when CE goes low, the outputs remain in the high impedance state. 30. CE or WE must be > VIH during address transitions. Document #: 001-53953 Rev. *H Page 13 of 22 [+] Feedback CY14V101LA CY14V101NA AutoStore/Power-up RECALL Over the Operating Range Parameter tHRECALL [31] tSTORE [32] Description Power-up RECALL duration STORE cycle duration Time allowed to complete SRAM write cycle Low voltage trigger level for VCC I/O disable voltage on VCCQ VCC rise time HSB output disable voltage on VCC HSB to output active time HSB high active time CY14V101LA/CY14V101NA Min Max – 20 – – – – 150 – – – 8 25 2.90 1.50 – 1.9 5 500 Unit ms ms ns V V µs V µs ns tDELAY VSWITCH VIODIS[34] VHDIS[35] [33] tVCCRISE[35] tLZHSB[35] tHHHD[35] Switching Waveforms Figure 9. AutoStore or Power-up RECALL[36] VCC VSWITCH VHDIS VCCQ VIODIS 32 32 t VCCRISE tHHHD HSB OUT VCCQ Note 37 Note tSTORE t HHHD Note tSTORE Note 37 tDELAY tLZHSB tDELAY POWERUP RECALL Read & Write Inhibited (RWI) POWER-UP RECALL Read & Write VCC BROWN OUT AutoStore Read POWER POWER-UP Read & DOWN & RECALL Write V Write AutoStore CCQ BROWN OUT I/O Disable t LZHSB AutoStore tHRECALL tHRECALL Notes 31. tHRECALL starts from the time VCC rises above VSWITCH. 32. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place. 33. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 34. HSB is not defined below VIODIS voltage. 35. These parameters are guaranteed by design and are not tested. 36. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 37. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document #: 001-53953 Rev. *H Page 14 of 22 [+] Feedback CY14V101LA CY14V101NA Software Controlled STORE/RECALL Cycle Over the Operating Range Parameters[38, 39] tRC tSA tCW tHA tRECALL Description STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration 25 ns Min 25 0 20 0 – Max – – – – 200 Min 45 0 30 0 – 45 ns Max – – – – 200 Unit ns ns ns ns µs Switching Waveforms Figure 10. CE and OE Controlled Software STORE/RECALL Cycle [39] tRC Address tSA CE tSA Address #1 tCW tRC Address #6 tCW tHA tHA tHA tHA OE tHZCE tSS Note 40 tLZCE DQ (DATA) t DELAY Figure 11. AutoStore Enable / Disable Cycle tRC Address tSA CE tSA OE tHHHD HSB (STORE only) DQ (DATA) tLZCE tHZCE t DELAY Note 40 tRC Address #6 tCW Address #1 tCW tHA tHA tHA tHA tLZHSB High Impedance tSTORE/tRECALL RWI Notes 38. The software sequence is clocked with CE controlled or OE controlled reads. 39. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles. 40. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time. Document #: 001-53953 Rev. *H Page 15 of 22 [+] Feedback CY14V101LA CY14V101NA Hardware STORE Cycle Over the Operating Range Parameters tDHSB tPHSB tSS [41, 42] Description HSB to output active time when write latch not set Hardware STORE pulse width Soft sequence processing time CY14V101LA/CY14V101NA Min – 15 – Max 25 – 100 Unit ns ns s Switching Waveforms Figure 12. Hardware STORE Cycle [43] Write Latch set HSB (IN) tDELAY HSB (OUT) SO RWI tSTORE ~ ~ tPHSB tHHHD ~ ~ ~ ~ tLZHSB Write Latch not set HSB (IN) ~ ~ tPHSB HSB pin is driven high to VCCQ only by Internal 100 K resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW. tDHSB HSB (OUT) tDELAY tDHSB RWI Figure 13. Soft Sequence Processing [41, 42] Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 Address #6 tCW tSS CE VCC Notes 41. This is the amount of time it takes to take action on a soft sequence command. VCC and VCCQ power must remain HIGH to effectively register command. 42. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 43. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place. Document #: 001-53953 Rev. *H ~ ~ Page 16 of 22 [+] Feedback CY14V101LA CY14V101NA Truth Table For SRAM Operations HSB must remain HIGH for SRAM operations. Table 2. Truth Table for × 8 Configuration CE H L L L WE X H H L OE X L H X High Z Data out (DQ0–DQ7) High Z Data in (DQ0–DQ7) Inputs/Outputs[44] Read Output disabled Write Mode Deselect / Power-down Standby Active Active Active Power Table 3. Truth Table for × 16 Configuration CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE[45] X H L H L L H L L H L BLE[45] X H L L H L L H L L H Inputs/Outputs[44] High Z High Z Data out (DQ0–DQ15) Data out (DQ0–DQ7); DQ8–DQ15 in High Z Data out (DQ8–DQ15); DQ0–DQ7 in High Z High Z High Z High Z Data in (DQ0–DQ15) Data in (DQ0–DQ7); DQ8–DQ15 in High Z Data in (DQ8–DQ15); DQ0–DQ7 in High Z Mode Deselect / Power-down Output disabled Read Read Read Output disabled Output disabled Output disabled Write Write Write Standby Active Active Active Active Active Active Active Active Active Active Power Notes 44. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 45. BHE and BLE are applicable for × 16 configuration only. Document #: 001-53953 Rev. *H Page 17 of 22 [+] Feedback CY14V101LA CY14V101NA Ordering Information Speed (ns) 25 Ordering Code CY14V101LA-BA25XIT CY14V101LA-BA25XI CY14V101NA-BA25XIT CY14V101NA-BA25XI 45 CY14V101LA-BA45XIT CY14V101LA-BA45XI CY14V101NA-BA45XIT CY14V101NA-BA45XI All parts are Pb-free. The above table contains final information. Contact your local Cypress sales representative for availability of these parts. Package Diagram 51-85128 48-ball FBGA Package Type Operating Range Industrial Ordering Code Definitions CY 14 V 101 L A - BA 25 X I T Option: T - Tape and Reel Blank - Std. Pb-free Package: BA - 48-ball FBGA Data Bus: L - ×8 N - ×16 Voltage: V - 3.3 V VCC, 1.8 V VCCQ Temperature: I - Industrial (–40 to 85 °C) Speed: 25 - 25 ns 45 - 45 ns Die revision: Blank - No Rev A - 1st Rev Density: 101 - 1 Mb 14 - nvSRAM Cypress Document #: 001-53953 Rev. *H Page 18 of 22 [+] Feedback CY14V101LA CY14V101NA Package Diagrams Figure 14. 48-ball FBGA (6 × 10 × 1.2 mm) BA48B, 51-85128 51-85128 *F Document #: 001-53953 Rev. *H Page 19 of 22 [+] Feedback CY14V101LA CY14V101NA Acronyms Acronym BHE BLE CE CMOS EIA FBGA HSB I/O nvSRAM OE SRAM RoHS RWI WE byte high enable byte low enable chip enable complementary metal oxide semiconductor electronic industries alliance fine-pitch ball grid array hardware STORE busy input/output non-volatile static random access memory output enable static random access memory restriction of hazardous substances Read and write inhibited write enable Description Document Conventions Units of Measure Symbol °C k A mA mm F MHz s ms ns  % pF V W degree Celsius kilo ohms micro Amperes milli Amperes milli meter micro Farad Mega Hertz micro seconds milli seconds nano seconds ohms percent pico Farad Volts Watts Unit of Measure Document #: 001-53953 Rev. *H Page 20 of 22 [+] Feedback CY14V101LA CY14V101NA Document History Page Document Title: CY14V101LA/CY14V101NA, 1-Mbit (128 K × 8/64 K × 16) nvSRAM Document Number: 001-53953 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 2729117 GVCH/ 07/02/09 New Datasheet AESA *A 2765890 GVCH 09/18/09 Removed commercial temperature related specs Changed part number from CY14A101L/CY14A101N to CY14V101LA/CY14V101NA Removed 20 ns Access speed specs Figure 3: Updated Autostore Mode Page 4; Updated Hardware STORE (HSB) Operation description Page 5; Updated Software STORE Operation description Added ICCQ1 and ICCQ3 for VCCQ operation Updated VIH/VIL as 70%/30% of VCCQ Updated VOH test condition Updated footnote 24 and added footnote 25, 30 Updated VIODIS parameter value from 1.6 V to 1.5 V Updated Footnote 10 Added Contents on page 2 *B 2767333 GVCH/ 01/06/10 Removed 44-TSOP II package related specs PYRS Changed Latch Up Current from 200 mA to 140 mA Changed STORE cycles to QuantumTrap from 200 K to 1 Million Added Contents *C 2923525 GVCH 04/27/10 Pin Definitions: Added more clarity on HSB pin operation Hardware STORE Operation: Added more clarity on HSB pin operation Table 1: Added more clarity on status of BHE/BLE pin operation Updated HSB pin operation in Figure 9 Updated footnote 24 *D 2999981 GVCH 08/04/2010 Changed datasheet status from “Preliminary” to “Final” *E 3033088 GVCH 09/22/2010 Changed ISB and ICC4 value from 5 mA to 8 mA Added Acronyms and Units of Measure table Updated as per new template *F 3123639 GVCH 12/30/2010 Removed Note “Address expansion for 16 Mbit. NC pin not connected to die.” in page 3 as 16 Mb address expansion is not supported in 48-ball FBGA package. Added CY14V101LA-BA25XI and CY14V101NA-BA25XI parts in Ordering Information. *G 3150308 GVCH 01/21/2011 Updated input capacitance for BHE and BLE pin Updated input and output capacitance for HSB pin Updated Ordering Information *H 3301833 GVCH 07/04/2011 Updated DC Electrical Characteristics (Added Note 13 and referred the same note in VCAP parameter). Updated AC Switching Characteristics (Added Note 15 and referred the same note in Parameters). Updated Thermal Resistance (Values of JA and JC for 48-ball FBGA package). Updated Package Diagrams. Document #: 001-53953 Rev. *H Page 21 of 22 [+] Feedback CY14V101LA CY14V101NA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-53953 Rev. *H Revised July 4, 2011 Page 22 of 22 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback