CY14V104LA

CY14V104LA CY14V104NA 4-Mbit (512 K × 8 / 256 K × 16) nvSRAM 4-Mbit (512 K × 8 / 256 K × 16) nvSRAM Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The Cypress CY14V104LA/CY14V104NA is a fast static RAM, with a non-volatile element in each memory cell. The memory is organized as 512 K bytes of 8 bits each or 256 K words of 16 bits each. The embedded non-volatile elements incorporate QuantumTrap technology, producing the world’s most reliable non-volatile memory. The SRAM provides infinite read and write cycles, while independent non-volatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the non-volatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the non-volatile memory. Both the STORE and RECALL operations are also available under software control. 25 ns and 45 ns access times Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16 (CY14V104NA) Hands off automatic STORE on power-down with only a small capacitor STORE to QuantumTrap non-volatile elements initiated by software, device pin, or AutoStore on power-down RECALL to SRAM initiated by software or power-up Infinite read, write, and recall cycles 1-million STORE cycles to QuantumTrap 20 year data retention Core VCC = 3.0 V to 3.6 V; IO VCCQ = 1.65 V to 1.95 V Industrial temperature 48-ball fine-pitch ball grid array (FBGA) package Pb-free and restriction of hazardous substances (RoHS) compliance Logic Block Diagram [1, 2, 3] Quatrum Trap 2048 X 2048 A0 A1 A2 A3 A4 A5 A6 A7 A8 A17 A18 D Q0 DQ 1 DQ 2 DQ 3 D Q4 D Q5 DQ 6 DQ 7 D Q8 DQ 9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A9 A10 A11 A12 A13 A14 A15 A16 CE BLE I N P U T B U F F E R S R O W D E C O D E R STORE RECALL STATIC RAM ARRAY 2048 X 2048 STORE/RECALL CONTROL HSB VCC VCCQ VCAP POWER CONTROL SOFTWARE DETECT A14 - A2 COLUMN I/O COLUMN DEC OE WE BHE Notes 1. Address A0–A18 for × 8 configuration and Address A0–A17 for × 16 configuration. 2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 3. BHE and BLE are applicable for × 16 configuration only. Cypress Semiconductor Corporation Document #: 001-53954 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 6, 2011 [+] Feedback CY14V104LA CY14V104NA Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Device Operation .............................................................. 4 SRAM Read ....................................................................... 4 SRAM Write ....................................................................... 4 AutoStore Operation ........................................................ 4 Hardware STORE Operation ............................................ 4 Hardware RECALL (Power-Up) ....................................... 5 Software STORE ............................................................... 5 Software RECALL ............................................................. 5 Preventing AutoStore ....................................................... 6 Data Protection ................................................................. 6 Noise Considerations ....................................................... 6 Best Practices ................................................................... 7 Maximum Ratings ............................................................. 8 Operating Range ............................................................... 8 DC Electrical Characteristics .......................................... 8 Data Retention and Endurance ....................................... 9 Capacitance ...................................................................... 9 Thermal Resistance .......................................................... 9 AC Test Loads ................................................................ 10 AC Test Conditions ........................................................ 10 AC Switching Characteristics ....................................... 11 SRAM Read Cycle .................................................... 11 SRAM Write Cycle ..................................................... 11 Switching Waveforms .................................................... 11 AutoStore/Power-Up RECALL ....................................... 14 Switching Waveforms .................................................... 14 Software Controlled STORE/RECALL Cycle ................ 15 Switching Waveforms .................................................... 15 Hardware STORE Cycle ................................................. 16 Switching Waveforms .................................................... 16 Truth Table For SRAM Operations ................................ 17 Ordering Information ...................................................... 18 Ordering Code Definitions ......................................... 18 Package Diagrams .......................................................... 19 Acronyms ........................................................................ 20 Document Conventions ................................................. 20 Units of Measure ....................................................... 20 Document History Page ................................................. 21 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC Solutions ......................................................... 22 Document #: 001-53954 Rev. *F Page 2 of 22 [+] Feedback CY14V104LA CY14V104NA Pinouts Figure 1. Pin Diagram – 48-ball FBGA (× 8) Top View (not to scale) 1 NC NC DQ0 VSS 2 OE NC NC DQ1 3 A0 A3 A5 A17 VCAP A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE NC 6 VCC NC DQ4 A B C D E F G H (× 16) Top View (not to scale) 1 BLE DQ8 2 OE BHE 3 A0 A3 A5 A17 VCAP A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE DQ1 6 VCC DQ0 DQ2 A B C D E F G H DQ9 DQ10 VSS DQ11 DQ5 VCCQ DQ6 NC WE A11 VSS DQ7 NC NC [4] DQ3 VCCQ DQ4 DQ5 WE A11 VSS DQ6 DQ7 NC VCCQ DQ2 DQ3 NC A18 NC HSB A8 VCCQ DQ12 DQ14 DQ13 DQ15 HSB NC [4] A8 Pin Definitions Pin Name A0–A18 A0–A17 DQ0–DQ7 Input/output DQ0–DQ15 WE CE OE BHE BLE VSS VCC VCCQ HSB Input Input Input Input Input Ground I/O Type Input Description Address Inputs Used to Select One of the 524,288 bytes of the nvSRAM for × 8 Configuration. Address Inputs Used to Select One of the 262,144 words of the nvSRAM for × 16 Configuration. Bidirectional Data I/O Lines for × 8 Configuration. Used as input or output lines depending on operation. Bidirectional Data I/O Lines for × 16 Configuration. Used as input or output lines depending on operation. Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tri-stated on deasserting OE HIGH. Byte High Enable, Active LOW. Controls DQ15–DQ8. Byte Low Enable, Active LOW. Controls DQ7–DQ0. Ground for the Device. Must be connected to the ground of the system. Power supply Power Supply Inputs to the Core of the Device. Power supply Power Supply Inputs for the Inputs and Outputs of the Device. Input/output Hardware Store Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a non-volatile STORE operation. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional). VCAP NC Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to non-volatile elements. No Connect No Connect. This pin is not connected to the die. Note 4. Address expansion for 8-Mbit. NC pin not connected to die. Document #: 001-53954 Rev. *F Page 3 of 22 [+] Feedback CY14V104LA CY14V104NA Device Operation The CY14V104LA/CY14V104NA nvSRAM is made up of two functional components paired in the same physical cell. They are a SRAM memory cell and a non-volatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the non-volatile cell (the STORE operation), or from the non-volatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14V104LA/CY14V104NA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the non-volatile cells and up to 1 million STORE operations. See Truth Table For SRAM Operations on page 17 for a complete description of read and write modes. on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This may corrupt the data stored in nvSRAM. Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to DC Electrical Characteristics on page 8 for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull-up should be placed on WE to hold it inactive during power-up. This pull-up is effective only if the WE signal is tristate during power-up. Many MPUs tristate their controls on power-up. This should be verified when using the pull-up. When the nvSRAM comes out of power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary non-volatile stores, AutoStore and hardware store operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 2. AutoStore Mode VCCQ VCC SRAM Read The CY14V104LA/CY14V104NA performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0–18 or A0–17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. 0.1 uF 10 kOhm VCCQ VCC 0.1 uF WE VCAP VCAP VSS SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–15 are written into the memory if the data is valid tSD before the end of a WE controlled write or before the end of an CE controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. It is recommended that OE be kept HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. Hardware STORE Operation The CY14V104LA/CY14V104NA provides the HSB pin to control and acknowledge the STORE operations. Use the HSB pin to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14V104LA/CY14V104NA conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k pull-up resistor. SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14V104LA/CY14V104NA. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. AutoStore Operation The CY14V104LA/CY14V104NA stores data to the nvSRAM using one of the following three storage operations: Hardware Store activated by HSB; Software Store activated by an address sequence; AutoStore on device power-down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14V104LA/CY14V104NA. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Note If a capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing AutoStore on page 6. If AutoStore is enabled without a capacitor Document #: 001-53954 Rev. *F Page 4 of 22 [+] Feedback CY14V104LA CY14V104NA During any STORE operation, regardless of how it is initiated, the CY14V104LA/CY14V104NA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the CY14V104LA/CY14V104NA remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used. 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8FC0 Initiate STORE Cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Hardware RECALL (Power-Up) During power-up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB is driven LOW by the HSB driver. Software RECALL Data is transferred from non-volatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled read operations must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the non-volatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the non-volatile elements. Software STORE Data is transferred from SRAM to the non-volatile memory by a software address sequence. The CY14V104LA/CY14V104NA software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous non-volatile data is first performed, followed by a program of the non-volatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following read sequence must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ Table 1. Mode Selection CE H L L L WE X H L H OE X L X L BHE, BLE[5] X L L X A15–A0[6] X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable I/O Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Power Standby Active Active Active[7] Notes 5. BHE and BLE are applicable for × 16 configuration only. 6. While there are 19 address lines on the CY14V104LA (18 address lines on the CY14V104NA), only the 13 address lines (A14–A2) are used to control software modes. Rest of the address lines are don’t care. 7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle. Document #: 001-53954 Rev. *F Page 5 of 22 [+] Feedback CY14V104LA CY14V104NA Table 1. Mode Selection (continued) CE L WE H OE L BHE, BLE[5] X A15–A0[6] 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Non-volatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Non-volatile Recall I/O Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Active[8] L H L X Active ICC2[8] L H L X Active[8] Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled. Data Protection The CY14V104LA/CY14V104NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14V104LA/CY14V104NA is in a write mode (both CE and WE are LOW) at power-up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). When VCCQ < VIODIS, I/Os are disabled (no STORE takes place). This protects against inadvertent writes during brown out conditions on VCCQ supply. Noise Considerations Refer to Cypress application note, AN1064. Note 8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle. Document #: 001-53954 Rev. *F Page 6 of 22 [+] Feedback CY14V104LA CY14V104NA Best Practices nvSRAM products have been used effectively for over 26 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ ■ The non-volatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. Power-up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this max VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period. ■ Document #: 001-53954 Rev. *F Page 7 of 22 [+] Feedback CY14V104LA CY14V104NA Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................–65 C to +150 C Maximum accumulated storage time At 150 C ambient temperature ....................... 1000 h At 85 C ambient temperature ......................20 Years Ambient temperature with power applied ...........................................–55 C to +150 C Supply voltage on VCC relative to VSS .......... –0.5 V to 4.1 V Supply voltage on VCCQ relative to VSS ...... –0.5 V to 2.45 V Voltage applied to outputs in High Z state .................................. –0.5 V to VCCQ + 0.5 V Input voltage ..................................... –0.5 V to VCCQ + 0.5 V Transient voltage (< 20 ns) on any pin to ground potential ............... –2.0 V to VCCQ + 2.0 V Package power dissipation capability (TA = 25 °C) ..................................................1.0 W Surface mount Pb soldering temperature (3 seconds) ..........................................+260 C DC output current (1 output at a time, 1s duration) .....15 mA Static discharge voltage (per MIL-STD-883, Method 3015) ......................... > 2001 V Latch up current .................................................... > 140 mA Operating Range Range Ambient Temperature Industrial –40 C to +85 C VCC VCCQ 3.0 V – 3.6 V 1.65 V – 1.95 V DC Electrical Characteristics Over the Operating Range Parameter Description VCC VCCQ ICC1 ICCQ1 ICC2 ICC3 ICCQ3 ICC4 ISB Average VCC current Average VCCQ current Average VCC current during STORE Average VCC current at tRC= 200 ns, VCC(Typ), 25 °C Average VCCQ current at tRC= 200 ns, VCCQ(Typ), 25 °C Average VCAP current during AutoStore cycle VCC standby current tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) All inputs don’t care, VCC = Max Average current for duration tSTORE All inputs cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA). All inputs don’t care. Average current for duration tSTORE CE > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). Standby current level after non-volatile cycle is complete. Inputs are static. f = 0 MHz. VCCQ = Max, VSS < VIN < VCCQ VCCQ = Max, VSS < VIN < VCCQ Power supply voltage – Test Conditions Min 3.0 1.65 – – – – – – – – – Typ [9] 3.3 1.8 – – – – – 35 5 – – Max 3.6 1.95 70 52 15 10 10 – – 8 8 Unit V V mA mA mA mA mA mA mA mA mA IIX[10] Input leakage current (except HSB) Input leakage current (for HSB) –1 –100 –1 – – – +1 +1 +1 A A A IOZ VCAP[11] Off-state output leakage current VCCQ = Max, VSS < VOUT < VCCQ, CE or OE > VIH or BHE/BLE > VIH or WE < VIL Storage capacitor Between VCAP pin and VSS, 5 V rated 61 68 180 F Notes 9. Typical values are at 25 °C, VCC = VCC(Typ) and VCCQ = VCCQ(Typ). Not 100% tested. 10. The HSB pin has IOUT = -4 µA for VOH of 1.07 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. 11. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options. Document #: 001-53954 Rev. *F Page 8 of 22 [+] Feedback CY14V104LA CY14V104NA DC Electrical Characteristics (continued) Over the Operating Range Parameter Description VIH VIL VOH VOL Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage – – IOUT = –1 mA IOUT = 2 mA Test Conditions Min 0.7 × VCCQ – 0.3 VCCQ – 0.45 Typ [9] – – – – Max VCCQ + 0.3 0.3 × VCCQ – 0.45 Unit V V V V Data Retention and Endurance Over the Operating Range Parameter DATAR NVC Data retention Non-volatile STORE operation Description Min 20 1,000 Unit Years K Capacitance Parameter[12] CIN Description Input capacitance (except BLE, BHE and HSB) Input capacitance (for BLE, BHE and HSB) COUT Output capacitance (except HSB) Output capacitance (for HSB) Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC (Typ), VCCQ = VCCQ (Typ) Max 7 8 7 8 Unit pF pF pF pF Thermal Resistance In the following table, the thermal resistance parameters are listed. Parameter[12] Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 48-ball FBGA 46.09 7.84 Unit C/W C/W JA JC Note 12. These parameters are guaranteed by design but not tested. Document #: 001-53954 Rev. *F Page 9 of 22 [+] Feedback CY14V104LA CY14V104NA AC Test Loads Figure 3. AC Test Loads 1.8 V Output 30 pF 450  R1 R2 450  1.8 V Output 5 pF 450  R1 for tri-state specs R2 450  AC Test Conditions Input pulse levels ................................................0 V to 1.8 V Input rise and fall times (10%–90%) ......................... VIH during address transitions. Document #: 001-53954 Rev. *F Page 12 of 22 [+] Feedback CY14V104LA CY14V104NA Switching Waveforms (continued) Figure 7. SRAM Write Cycle #2 (CE Controlled) [26, 27, 28, 29] tWC Address tSA CE tBW BHE, BLE tPWE WE tSD Data Input Data Output Input Data Valid High Impedance tHD Address Valid tSCE tHA Figure 8. SRAM Write Cycle #3 (BHE and BLE Controlled) [26, 27, 28, 29] tWC Address tSCE CE tSA BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output tBW tHA Address Valid Notes 26. HSB must remain HIGH during read and write cycles. 27. BHE and BLE are applicable for × 16 configuration only. 28. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 29. CE or WE must be >VIH during address transitions. Document #: 001-53954 Rev. *F Page 13 of 22 [+] Feedback CY14V104LA CY14V104NA AutoStore/Power-Up RECALL Over the Operating Range Parameter tHRECALL [30] tSTORE [31] tDELAY [32] VSWITCH VIODIS[33] tVCCRISE[36] VHDIS[36] tLZHSB[36] tHHHD[36] Description Power-Up RECALL duration STORE cycle duration Time allowed to complete SRAM write cycle Low voltage trigger level for VCC I/O disable voltage on VCCQ VCC rise time HSB output disable voltage on VCC HSB to output active time HSB high active time Figure 9. AutoStore or Power-Up RECALL [34] VCC VSWITCH VHDIS CY14V104LA/CY14V104NA Min Max – 20 – 8 – 25 – 2.90 – 1.50 150 – – 1.9 – 5 – 500 Unit ms ms ns V V s V s ns Switching Waveforms VCCQ VIODIS 32 t VCCRISE tHHHD HSB OUT VCCQ Note 35 Note tSTORE t HHHD Note 32 tSTORE Note 35 tDELAY tLZHSB tDELAY POWERUP RECALL Read & Write Inhibited (RWI) POWER-UP RECALL Read & Write VCC BROWN OUT AutoStore Read POWER POWER-UP Read & DOWN & RECALL Write V Write AutoStore CCQ BROWN OUT I/O Disable t LZHSB AutoStore tHRECALL tHRECALL Notes 30. tHRECALL starts from the time VCC rises above VSWITCH. 31. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware Store takes place. 32. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 33. HSB will not be defined below VIODIS voltage. 34. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 35. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. 36. These parameters are guaranteed by design but not tested. Document #: 001-53954 Rev. *F Page 14 of 22 [+] Feedback CY14V104LA CY14V104NA Software Controlled STORE/RECALL Cycle Over the Operating Range Parameters [37, 38] tRC tSA tCW tHA tRECALL Description STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration 25 ns Min 25 0 20 0 – Max – – – – 200 Min 45 0 30 0 – 45 ns Max – – – – 200 Unit ns ns ns ns s Switching Waveforms Figure 10. CE and OE Controlled Software STORE/RECALL Cycle [38] tRC Address tSA CE tSA OE tHHHD HSB (STORE only) DQ (DATA) tLZCE tHZCE t DELAY Note 39 tRC Address #6 tCW Address #1 tCW tHA tHA tHA tHA tLZHSB High Impedance tSTORE/tRECALL RWI Figure 11. AutoStore Enable/Disable Cycle tRC Address tSA CE tSA Address #1 tCW tRC Address #6 tCW tHA tHA tHA tHA OE tHZCE tSS Note 39 tLZCE DQ (DATA) t DELAY Notes 37. The software sequence is clocked with CE controlled or OE controlled reads. 38. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles. 39. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time. Document #: 001-53954 Rev. *F Page 15 of 22 [+] Feedback CY14V104LA CY14V104NA Hardware STORE Cycle Over the Operating Range Parameters tDHSB tPHSB tSS [40, 41] Description HSB to output active time when write latch not set Hardware STORE pulse width Soft sequence processing time CY14V104LA/CY14V104NA Min – 15 – Max 25 – 100 Unit ns ns s Switching Waveforms Figure 12. Hardware STORE Cycle [42] Write latch set tPHSB HSB (IN) tSTORE tDELAY HSB (OUT) tLZHSB DQ (Data Out) RWI tHHHD Write latch not set tPHSB HSB (IN) HSB pin is driven HIGH to VCC only by Internal 100 kOhm resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low. tDELAY tDHSB tDHSB HSB (OUT) RWI Figure 13. Soft Sequence Processing [40, 41] Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 Address #6 tCW tSS CE VCC Notes 40. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 41. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 42. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware Store takes place. Document #: 001-53954 Rev. *F Page 16 of 22 [+] Feedback CY14V104LA CY14V104NA Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. Table 2. Truth Table for × 8 Configuration CE H L L L WE X H H L OE X L H X High Z Data out (DQ0–DQ7) High Z Data in (DQ0–DQ7) Inputs/Outputs[43] Read Output disabled Write Mode Deselect/Power-down Standby Active Active Active Power Table 3. Truth Table for × 16 Configuration CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE[44] X H L H L L H L L H L BLE[44] X H L L H L L H L L H Inputs/Outputs[43] High Z High Z Data out (DQ0–DQ15) Data out (DQ0–DQ7); DQ8–DQ15 in High Z Data out (DQ8–DQ15); DQ0–DQ7 in High Z High Z High Z High Z Data in (DQ0–DQ15) Data in (DQ0–DQ7); DQ8–DQ15 in High Z Data in (DQ8–DQ15); DQ0–DQ7 in High Z Mode Deselect/Power-down Output disabled Read Read Read Output disabled Output disabled Output disabled Write Write Write Standby Active Active Active Active Active Active Active Active Active Active Power Notes 43. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 44. BHE and BLE are applicable for × 16 configuration only. Document #: 001-53954 Rev. *F Page 17 of 22 [+] Feedback CY14V104LA CY14V104NA Ordering Information Speed (ns) 25 Ordering Code CY14V104LA-BA25XIT CY14V104LA-BA25XI CY14V104NA-BA25XIT CY14V104NA-BA25XI 45 CY14V104LA-BA45XIT CY14V104LA-BA45XI CY14V104NA-BA45XIT CY14V104NA-BA45XI Contact your local Cypress sales representative for availability of these parts. Package Diagram 51-85128 48-ball FBGA Package Type Operating Range Industrial Ordering Code Definitions CY 14 V 104 L A - BA 25 X I T Option: T - Tape and Reel Blank - Std. X - Pb-free Package: BA - 48-ball FBGA Die Revision: Blank - No Rev A - 1st Rev Temperature: I - Industrial (–40 to 85 °C) Speed: 25 - 25 ns 45 - 45 ns Data Bus: L-×8 N - × 16 Voltage: V - 3.3 V VCC, 1.8 V VCCQ Density: 104 - 4 Mb 14 - NVSRAM Cypress Document #: 001-53954 Rev. *F Page 18 of 22 [+] Feedback CY14V104LA CY14V104NA Package Diagrams Figure 14. 48-ball FBGA (6 × 10 × 1.2 mm) BA48B, 51-85128 51-85128 *F Document #: 001-53954 Rev. *F Page 19 of 22 [+] Feedback CY14V104LA CY14V104NA Acronyms Acronym BHE BLE CE CMOS EIA FBGA HSB I/O nvSRAM OE RoHS SRAM WE byte high enable byte low enable chip enable complementary metal oxide semiconductor electronic industries alliance fine-pitch ball grid array hardware store busy input/output non-volatile static random access memory output enable restriction of hazardous substances static random access memory write enable Description Document Conventions Units of Measure Symbol °C k MHz A mA F s ms ns  % pF V W degree Celsius kilo ohms Mega Hertz micro Amperes milli Amperes micro Farads micro seconds milli seconds nano seconds ohms percent pico Farads Volts Watts Unit of Measure Document #: 001-53954 Rev. *F Page 20 of 22 [+] Feedback CY14V104LA CY14V104NA Document History Page Document Title: CY14V104LA/CY14V104NA, 4-Mbit (512 K × 8 / 256 K × 16) nvSRAM Document Number: 001-53954 Rev. ** *A ECN No. 2729117 2826127 Orig. of Change GVCH / AESA GVCH / AESA Submission Date 07/02/2009 12/11/2009 New Data Sheet Removed commercial temperature related specs Changed part number from CY14A104L/CY14A104N to CY14V104LA/CY14V104NA Removed 20 ns Access speed specs Removed 44/54 TSOP II package related information Updated STORE cycles to QuantumTrap from 200K to 1 million Figure 3: Updated Autostore Mode Page 4: Updated Hardware STORE (HSB) Operation description Page 5: Updated Software STORE Operation description Maximum Ratings: Supply Voltage on VCCQ Relative to GND from –0.5V to 2.5V to –0.5V to 2.45V Added ICCQ1 and ICCQ3 for VCCQ operation Updated ICC4 test condition Updated footnote 8 Updated VIH/VIL as 70%/30% of VCCQ Updated VOH test condition. Updated Input Rise and Fall Times (10% - 90%) from 3ns to 1.8 ns Updated footnote 19, 22 and added footnote 20, 25 Updated VIODIS parameter value from 1.6V to 1.5V Updated Figure 10, 11 and 12 Changed latch up current from 200 mA to 140 mA. Changed status from Advance to Preliminary. Added Contents. Pin Definitions: Added more clarity on HSB pin operation Hardware STORE Operation: Added more clarity on HSB pin operation Table 1: Added more clarity on status of BHE/BLE pin operation Updated HSB pin operation in Figure 9 Updated footnote 22 Change datasheet status from “Preliminary” to “Final” 48 FBGA package: 16 Mb address expansion is not supported Changed ISB and ICC4 value from 5 mA to 8 mA Changed ICCQ1 value from 25 mA to 15 mA for 25 ns access speed and 15 mA to 10 mA for 45 ns access speed. Added Acronyms and Units of Measure table Updated input capacitance for BHE and BLE pin Updated DC Electrical Characteristics (Added Note 11 and referred the same note in VCAP parameter). Updated AC Switching Characteristics (Added Note 13 and referred the same note in Parameters). Updated Thermal Resistance (Values of JA for 48-ball FBGA package). Updated Package Diagrams. Description of Change *B 2858300 GVCH 01/19/2010 *C 2951754 GVCH / AESA 06/14/2010 *D 3115647 GVCH 12/20/2010 *E *F 3150253 3303659 GVCH GVCH 01/21/11 07/06/2011 Document #: 001-53954 Rev. *F Page 21 of 22 [+] Feedback CY14V104LA CY14V104NA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-53954 Rev. *F Revised July 6, 2011 Page 22 of 22 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback