Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY14V116F7
CY14V116G7
16-Mbit nvSRAM
with Asynchronous NAND Interface
16-Mbit nvSRAM with Asynchronous NAND Interface
Features
■
Functional Description
16-Mbit nonvolatile static random access memory (nvSRAM)
❐ Performance up to 33 MT/s per I/O
❐ Maximum data throughput using ×16 bus – 528 Mbps
❐ Industry-standard asynchronous NAND Flash interface with
reduced instruction set
❐ Shared address, data, and command bus
• Address and command bus is 8 bits
• Command is sent in one or two command cycles
• Address is sent in five address cycles
• Data bus width is ×8 or ×16 bits
■
Modes of operation:
❐ Asynchronous NAND Interface I/O with 30-ns access time
❐ Status Register with a software method for detecting the following:
• Nonvolatile STORE completion
• Pass/Fail condition of previous command
• Write protect status
■
Hands-off automatic STORE on power-down with only a small
capacitor
■
STORE to QuantumTrap nonvolatile elements is initiated by a
software command, a dedicated hardware pin, or AutoStore on
power-down
■
RECALL to SRAM initiated by software or power-up
■
High reliability
❐
❐
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
■
Operating voltage
❐ Core VCC = 2.7 V to 3.6 V; I/O VCCQ = 1.70 V to 1.95 V
■
165-ball fine-pitch ball grid array (FBGA) package
■
Industrial temperature: –40 C to +85 C
■
Restriction of hazardous substances (RoHS) compliant
•
The CY14V116F7/CY14V116G7 nvSRAM provides access
through a standard asynchronous NAND interface and supports
the ×8 and ×16 interface options. In the case of ×16 interface,
data bytes are transmitted over the DQ[15:0] lines and has
double the throughput compared to the DQ[7:0] bus. The
CY14V116F7/ CY14V116G7 uses a highly multiplexed DQ bus
to transfer data, addresses, and instructions. All addresses and
commands are always transmitted over the data bus DQ[7:0].
Therefore, in the case of the ×16 bus interface, the upper eight
data bits DQ[15:8] become don’t care bits during the address and
command cycles. The CY14V116F7/CY14V116G7 uses five
control pins (CLE, ALE, CE, RE, and WE) to transfer command,
address, and data during read and write operations. Additional
I/O pins, such as write protect (WP), ready/busy (R/B), and HSB
STORE, are used to support features in the device.
The asynchronous NAND interface nvSRAM is aligned to a
majority of the ONFI 1.0 specifications and supports data access
speed up to 33 MHz.
For a complete list of related documentation, click here.
■
Cypress Semiconductor Corporation
Document Number: 001-75528 Rev. *K
Cypress nvSRAM combines high-performance SRAM cells with
nonvolatile elements in a monolithic integrated circuit. The
embedded
nonvolatile
elements
incorporate
the
Silicon-Oxide-Nitride-Oxide-Silicon
(SONOS)
technology,
producing the world’s most reliable nonvolatile memory. The
SRAM can be read and written an infinite number of times. The
nonvolatile data resides in the nonvolatile elements and does not
change when data is written to the SRAM.
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 5, 2018
CY14V116F7
CY14V116G7
Block Diagram
Single-Channel Architecture
VCC
VCAP
VCCQ
Power Control
16 Mbit nvSRAM
Core
WP
STORE / RECALL /
Write Protect
Control
R/B
HSB
Data I/O
I/O Control
DQ[15:0]
DQ[7:0]
Address Register
DQ[7:0]
Command Register
Address
CE
CLE
ALE
NAND Interface
Control Logic
WE
RE
Document Number: 001-75528 Rev. *K
Page 2 of 32
CY14V116F7
CY14V116G7
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Discovery and Initialization ............................................. 5
nvSRAM Bus Operations ................................................. 5
Control Signals ................................................................. 5
nvSRAM Bus Modes ......................................................... 6
nvSRAM Enable/Standby ............................................ 6
nvSRAM Bus Idle ........................................................ 6
nvSRAM Commands ................................................... 6
nvSRAM Address Input ............................................... 7
nvSRAM Data Input ..................................................... 8
nvSRAM Data Output .................................................. 8
Command Definition .................................................... 9
Basic Operations ............................................................ 10
Read ID (90h) Definition ............................................ 10
Read Parameter Page (ECh) .................................... 12
Read Status (70h) Definition ..................................... 14
Status Field Definition ............................................... 15
nvSRAM Burst Mode Read (00h, 30h) ...................... 15
nvSRAM Burst Write (80h, 10h) ................................ 16
Reset (FFh) Definition ............................................... 16
nvSRAM Software RECALL (FCh) ............................ 17
Software STORE (84h, A5h) in nvSRAM .................. 17
nvSRAM AutoStore Disable (A3h) ............................ 17
nvSRAM AutoStore Enable (ACh) ............................. 17
Write Protect .............................................................. 18
nvSRAM Store Operations ............................................. 18
AutoStore Operation .................................................. 18
Hardware STORE (HSB) Operation .......................... 19
Software Store Operation .......................................... 19
Document Number: 001-75528 Rev. *K
nvSRAM RECALL Operations ....................................... 19
Hardware RECALL (Power-Up) ................................ 19
Software Recall ......................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
DC Electrical Characteristics ........................................ 20
Data Retention and Endurance ..................................... 21
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Conditions ........................................................ 22
AC Switching Characteristics ....................................... 23
Timing Modes ............................................................ 23
nvSRAM AutoStore/
Power-Up RECALL Characteristics .............................. 24
Hardware STORE Characteristics ................................. 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Page 3 of 32
CY14V116F7
CY14V116G7
Pin Configurations
Figure 1. Single-Channel (×8) Pin Diagram: 165-ball FBGA
1
2
3
4
5
6
7
8
9
10
11
A
R
R
R
NC
NC
NC
NC
NC
R
R
R
B
R
R
R
NC
NC
NC
NC
NC
R
R
R
C
R
VCCQ
VCCQ
NC
VSS
NC
VCC
NC
VCCQ
VCCQ
R
D
R
VSS
NC
VSS
NC
NC
NC
VSS
NC
VSS
R
E
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
F
NC
VSS
VCCQ
NC
NC
NC
NC
NC
VCCQ
VSS
NC
G
NC
NC
NC
NC
R
NC
NC
NC
NC
HSB
NC
H
NC
VSS
VCC
R/B
NC
NC
NC
NC
VCC
VSS
NC
J
NC
VCAP
NC
CE
NC
NC
NC
WP
R
NC
NC
K
NC
VSS
VCCQ
NC
NC
NC
CLE
ALE
VCCQ
VSS
NC
L
NC
DQ7
DQ6
NC
WE
NC
NC
NC
DQ1
DQ0
NC
M
R
VSS
DQ5
VSS
RE
NC
NC
VSS
DQ2
VSS
R
N
R
VCCQ
VCCQ
DQ4
VCC
NC
VSS
DQ3
VCCQ
VCCQ
R
P
R
R
R
NC
NC
NC
NC
NC
R
R
R
R
R
R
R
NC
NC
NC
NC
NC
R
R
R
Figure 2. Single-Channel (×16) Pin Diagram: 165-ball FBGA
1
2
3
4
5
6
7
8
9
10
11
A
R
R
R
NC
NC
NC
NC
NC
R
R
R
B
R
R
R
NC
NC
NC
NC
NC
R
R
R
C
R
VCCQ
VCCQ
DQ11
VSS
NC
VCC
DQ12
VCCQ
VCCQ
R
D
R
VSS
DQ10
VSS
NC
NC
NC
VSS
DQ13
VSS
R
E
NC
DQ8
DQ9
NC
NC
NC
NC
NC
DQ14
DQ15
NC
F
NC
VSS
VCCQ
NC
NC
NC
NC
NC
VCCQ
VSS
NC
G
NC
NC
NC
NC
R
NC
NC
NC
NC
HSB
NC
H
NC
VSS
VCC
R/B
NC
NC
NC
NC
VCC
VSS
NC
J
NC
VCAP
NC
CE
NC
NC
NC
WP
R
NC
NC
K
NC
VSS
VCCQ
NC
NC
NC
CLE
ALE
VCCQ
VSS
NC
L
NC
DQ7
DQ6
NC
WE
NC
NC
NC
DQ1
DQ0
NC
M
R
VSS
DQ5
VSS
RE
NC
NC
VSS
DQ2
VSS
R
N
R
VCCQ
VCCQ
DQ4
VCC
NC
VSS
DQ3
VCCQ
VCCQ
R
P
R
R
R
NC
NC
NC
NC
NC
R
R
R
R
R
R
R
NC
NC
NC
NC
NC
R
R
R
Document Number: 001-75528 Rev. *K
Page 4 of 32
CY14V116F7
CY14V116G7
Pin Definitions
Pin Name
I/O Type
Description
R/B
Output
Ready/Busy. The ready/busy signal indicates the device status. When it is pulled LOW, the signal
indicates that nvSRAM is busy doing either a STORE or a power-up RECALL or a Software
RECALL/Software STORE/AutoStore Disable/AutoStore Enable operation. This signal is an open drain
output and requires an external pull-up resistor.
RE
Input
Read Enable. The read enable signal enables the data output during read operation.
CE
Input
Chip Enable. The chip enable signal selects the device when pulled LOW. When chip enable is HIGH
and the device is not busy doing a STORE operation, the device goes into a low-power standby state.
CLE
Input
Command Latch Enable. The command latch enable signal is used to latch the command byte. This
is one of the signals used by the host to indicate the type of bus cycle (command, address, and data).
ALE
Input
Address Latch Enable. The address latch enable signal is used to latch the address byte. This is one
of the signals used by the host to indicate the type of bus cycle (command, address, and data).
WE
Input
Write Enable. The write enable signal controls the latching of the input data on every rising edge.
WP
Input
Write Protect. The WP disables the SRAM write operation in nvSRAM if pulled LOW.
DQ[7:0][1]
I/O Port, 8 bits for the ×8 configuration. The I/O port is an 8-bit wide bidirectional port for transferring
Input/Output
address, command, and data to and from the device.
I/O Port, 16 bits for the ×16 configuration. The I/O port is a 16-bit wide bidirectional bus to transfer
DQ[15:0][1] Input/Output data words to and from the device during write and read operations. Address and commands are always
transmitted over the lower 8 bits DQ[7:0].
HSB
Input
Hardware STORE. When pulled LOW external to the chip, it will initiate a nonvolatile STORE operation.
VCAP
Power supply
AutoStore capacitor: Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
VCC
Power supply Power. Power supply inputs to the core of the device.
VCCQ
VSS
Power supply I/O Power. Power supply inputs for the inputs and outputs of the device.
Power supply Ground for the device. Must be connected to ground of the system.
R
R
NC
NC
Reserved. These pins are reserved, should be left unconnected by the host.
No Connect. Die pads are not connected to the package pin.
Discovery and Initialization
When the power-up cycle starts and VCC crosses the VSWITCH
threshold, the device initializes an internal Power-up RECALL
operation and pulls the R/B pin LOW for tRECALL duration. When
the power-up cycle is completed, the device releases the R/B
pin, which is then pulled HIGH by an external pull-up resistor
connected to it. The R/B HIGH indicates the device’s ready
status and allows the host controller to communicate with the
device by executing opcodes. All supported opcodes are
described in Table 3 on page 9.
nvSRAM Bus Operations
The nvSRAM device I/Os are multiplexed. Data I/O, addresses,
and commands all share the same I/O pins. DQ[15:8] are used
only for data in the ×16 configuration. Addresses and commands
are always transmitted through DQ[7:0] and data through
DQ[15:0] in the ×16 configuration.
The command sequence normally consists of a Command Latch
cycle, Address Input cycles, and one or more Data cycles, either
Read or Write.
Control Signals
The nvSRAM control signals, such as CE, WE, RE, CLE, ALE,
and WP, control the nvSRAM device read and write operations.
The CE is used to enable the device when pulled LOW and the
device is not in the busy state. When the nvSRAM is selected, it
accepts command, address, and data bytes. The nvSRAM will
enter the standby mode if CE goes HIGH while data is being
transferred and the device is not busy.
A HIGH CLE signal, along with CE and WE LOW, indicates a
command input cycle. Similarly, a HIGH ALE signal, along with
CE and WE LOW, indicates an Address Input cycle.
Note
1. Data DQ[7:0] for the ×8 configuration and data DQ[15:0] for the ×16 configuration.
Document Number: 001-75528 Rev. *K
Page 5 of 32
CY14V116F7
CY14V116G7
nvSRAM Bus Modes
nvSRAM Enable/Standby
Depending upon the input control signals status, the nvSRAM
takes any of the following bus states as defined in Table 1.
Table 1. Asynchronous NAND Interface Bus Modes
CE
ALE
CLE
WE
RE
WP
Bus State
1
X
X
X
X
X
Standby
0
0
0
1
1
X
Bus Idle
0
0
1
0
1
X
Command cycle
0
1
0
0
1
X
Address cycle
0
0
0
0
1
H
Write Cycle
0
0
0
1
0
X
Read Cycle
0
1
1
X
X
X
Undefined
0
0
0
0
1
L
Write protect to
SRAM
A chip enable (CE) signal is used to enable or disable the device.
When CE is driven LOW, all nvSRAM input signals are enabled.
With CE LOW, the nvSRAM can accept commands, addresses,
and data on its DQ lines. The nvSRAM is disabled when CE is
driven HIGH, even when the device is busy. The nvSRAM enters
the low-power standby mode when the device status is ready
and R/B is pulled HIGH by the external pull-up resistor. When CE
is disabled, all nvSRAM I/Os are disabled except WP, R/B, and
HSB.
nvSRAM Bus Idle
The nvSRAM goes to the bus idle state when CE, ALE, CLE are
LOW, and WE, RE are HIGH. During bus idle, all the input signals
are enabled but the commands, addresses, and data are not
latched in the device and there is also no data output from the
device.
nvSRAM Commands
A command is written from DQ[7:0] to the command register on
the rising edge of WE when CE is LOW, ALE is LOW, CLE is
HIGH, and RE is HIGH. All commands except the status register
read (70h) and reset (FFh) are ignored when the nvSRAM is
busy (RDY bit is set to ‘0’ in the status register).
Note Signal with state ‘X’ can be either > VIH or < VIL.
Figure 3. Command Latch Cycle
CLE
t CLH
t CLS
t CS
t CH
CE
t WP
WE
t ALH
t ALS
ALE
t DH
t DS
DQ[7:0]
COMMAND
Don’t Care
Document Number: 001-75528 Rev. *K
Page 6 of 32
CY14V116F7
CY14V116G7
nvSRAM Address Input
During the nvSRAM address cycle, the host transmits the five
consecutive address bytes through DQ[7:0] to the address
register on every rising edge of WE toggle when CE is LOW, ALE
is HIGH, CLE is LOW, and RE is HIGH. In five-byte addressing,
the least significant address byte is sent in the first address cycle
and the most significant address byte is sent in the fifth address
cycle. nvSRAM requires only the first three address bytes to
address its entire 16-Mbit memory. Therefore, the two extra
address bytes in the five-byte address are don't care bytes. All
unused address bits, including the don't care bits, should be set
to ‘0’ by the host controller. The address cycle is ignored by the
nvSRAM during the busy (RDY bit is set to ‘0’ in the status
register) period. Refer to Table 2 on page 9 for nvSRAM
addressing.
Figure 4. Address Latch Cycle
CLE
t CLS
t CS
CE
t WC
t WP
t WH
WE
t ALS
t ALH
ALE
t DH
t DS
Address
Byte 1
DQ[7:0]
Address
Byte 2
Address
Byte 3
Address
Byte 4
Address
Byte 5
Don’t Care
Document Number: 001-75528 Rev. *K
Page 7 of 32
CY14V116F7
CY14V116G7
nvSRAM Data Input
Data is written from DQ (DQ[7:0] or DQ[15:0]) to the data register of the nvSRAM on the rising edge of WE when CE is LOW, ALE is
LOW, CLE is LOW, and RE is HIGH. Data inputs are ignored by the nvSRAM during device busy (RDY bit is set to ‘0’ in the status
register) state.
Figure 5. Data Input Cycle
CLE
t CLH
CE
t ALS
t CH
ALE
t WC
t WP
t WP
WE
t WP
t WH
t DH
t DS
DQ
D0
t DH
t DH
t DS
t DS
D1
DN
Don’t Care
nvSRAM Data Output
Data is sent out (during read) on the DQ bus (DQ[7:0] or DQ[15:0]) by the nvSRAM if it is in the ready status. Data is output from the
data register on every falling edge of RE when CE is LOW, ALE is LOW, CLE is LOW, and WE is HIGH. nvSRAM ignores the read
request if it is busy (RDY bit is set to ‘0’ in the status register) during a STORE cycle.
Figure 6. Data Output Cycles
t CEA
CE
tREA
t REA
t REA
t REH
t RP
t CHZ
t COH
RE
t RHZ
t RHZ
t RHOH
DQ
D1
D2
DN
t RC
Don’t Care
Document Number: 001-75528 Rev. *K
Page 8 of 32
CY14V116F7
CY14V116G7
Table 2. nvSRAM Addressing
Address Cycle
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
First
A7
A6
A5
A4
A3
A2
A1
A0
Second
A15
A14
A13
A12
A11
A10
A9
A8
A20/LOW [2]
A19
A18
A17
A16
Third
Don’t care[3]
Fourth
Don’t care[3]
Fifth
Don’t care[3]
Command Definition
The nvSRAM has address, command, and data multiplexed on
its I/Os. All commands and addresses are written through the DQ
bus DQ[7:0] by toggling WE to LOW while CE and CLE are LOW
and ALE is HIGH for the address cycle and CE and ALE are LOW
and CLE is HIGH for the command cycle. The status of all the
input pins are latched on the rising edge of WE after which the
device determines whether the bus cycle is a command cycle,
address cycle, data input cycle, or data output cycle. All the
asynchronous NAND interface nvSRAM commands are listed in
Table 3.
Table 3. nvSRAM Commands Table
nvSRAM Function
First Cycle
Second Cycle
Description
Read ID
90h
Identifies that the target supports the ONFI specification. If the target
supports the ONFI specification, then the ONFI signature is returned.
Read Parameter
Page
ECh
The read parameter page function retrieves the data structure that
describes the target’s organization, features, timings and other behavioral
parameters.
Read Status
70h
Read
00h
30h
The read function reads from the nvSRAM array location specified by the
address bytes.
Write
80h
10h[4]
Data is written to the SRAM array of nvSRAM. 10h is an optional
command cycle for the nvSRAM write operation and a successful write
will execute even without the host issuing this command.
Reset
FFh
Aborts the current operation (all writes and reads) and puts the nvSRAM
in its power-up state. If an NV operation is in progress, it will be completed
first and then the reset request will be serviced.
Software RECALL
FCh
Software RECALL
Retrieves a status value for the last operation issued.
Software STORE
84h
AutoStore Disable
A3h
A5h
Software STORE
Disables the AutoStore
AutoStore Enable
ACh
Enables the AutoStore
Reserved
EEh
Reserved
Reserved
EFh
Reserved
Notes
2. A20 address bit should be set to LOW for the ×16 configuration.
3. Although these address bits are ‘don’t care’, Cypress recommends that these bits are treated as 0s.
4. The 10h command at the end of the write cycle is optional and used only for flash compatibility.
Document Number: 001-75528 Rev. *K
Page 9 of 32
CY14V116F7
CY14V116G7
Basic Operations
For the read ID command, only the addresses of 00h and 20h
are valid. Any other addresses, except 00h and 20h, following
the read ID command (90h) will return invalid data to the host. To
retrieve the ONFI signature, an address of 20h shall be entered.
The following sections describe the nvSRAM commands.
Read ID (90h) Definition
The read ID function identifies that the device supports the ONFI
specification. If the nvSRAM supports the ONFI specification, the
ONFI signature shall be returned. The ONFI signature is the
ASCII encoding of 'ONFI' where 'O' = 4Fh, 'N' = 4Eh, 'F' = 46h,
and 'I' = 49h. Reading beyond four bytes will yield indeterminate
values. Figure 7 and Figure 8 define the read ID behavior and
timings.
For a device that supports 16-bit data access, the upper 8 bits
DQ[15:8] are not used and are “Don’t Care” bits.
Figure 7. Read ID Operation Diagram for ONFI Signature
Cycle Type
CMD
ADDR
DOUT
DOUT
DOUT
DOUT
4Fh
4Eh
46h
49h
t WHR
DQ[7:0]
90h
20h
Figure 8. Read ID Timing Diagram for ONFI Signature
CE
t CH
t CS
CLE
t CLS
t CLH
WE
t WHR
ALE
t COH
t RC
t CHZ
RE
t RHOH
t RP
t RHZ
DQ[7:0]
90h
20h
4Fh
4Eh
46h
49h
Don’t Care
Document Number: 001-75528 Rev. *K
Page 10 of 32
CY14V116F7
CY14V116G7
The read ID function can also be used to determine the JEDEC manufacturer ID and the device ID for the particular NAND part by
specifying an address of 00h. Figure 9 defines the read ID behavior and timings for retrieving the device ID. Reading beyond the first
two bytes yields undetermined value.
Figure 9. Read ID Operation Diagram for Manufacturer ID
Cycle Type
CMD
ADDR
DOUT
DOUT
MID
DID
t WHR
DQ[7:0]
90 h
00 h
Figure 10. Read ID Timing Diagram for Manufacturer ID
CE
t CH
t CS
CLE
t CLS
t CLH
WE
t WHR
ALE
t COH
t RC
t CHZ
RE
t RHOH
t RP
t RHZ
DQ[7:0]
90h
00h
MID
MID
DID
DID
Don’t Care
MID is a 2-byte code consisting of the assigned manufacturer ID.
MID registers are set in factory and are read-only registers for
the user. This is the JEDEC-assigned manufacturer ID for
Cypress. JEDEC assigns the manufacturer ID in different banks.
The first eight bits represents the bank in which the ID is
assigned. The next eight bits represent the manufacturer ID. The
Cypress manufacturer ID is 34h in bank 0. Therefore, the
manufacturer ID for all Cypress NAND interface nvSRAM
products is:
DID is a 2-byte code consisting of the device ID for the part,
assigned by Cypress. The device ID is 22h, 00h for the ×8 part
and 22h, 40h for the ×16 part.
DID (×8): 0010_0010_0000_0000
DID (×16): 0010_0010_0100_0000
MID: 0000_0000_0011_0100
Document Number: 001-75528 Rev. *K
Page 11 of 32
CY14V116F7
CY14V116G7
Read Parameter Page (ECh)
The read parameter page command (ECh) retrieves the data
structure that describes the target's organization, features,
timings, and other behavioral parameters. Figure 11 defines the
read parameter page command. This command is accepted by
the target only when the nvSRAM is idle. Writing ECh to the
command register puts the target in the Read Parameter Page
mode. The device stays in this mode until another valid
command is issued.
the parameter page byte. The nvSRAM starts sending parameter
bytes for every RE toggle.
The read parameter page (ECh) output data can be used by the
host to configure its internal settings for properly using the
nvSRAM device. The parameter page data is static for every
part. However, the value can be changed through the product
cycle of the device. The host should interpret the data and
configure itself accordingly.
When the ECh command is sent, followed by the 00h address
cycle, the host should wait for at least tWHR time before reading
Figure 11. Read Parameter Page command timing
CLE
WE
t WHR
ALE
t RC
RE
t RP
DQ[7:0]
ECh
00h
P0
Parameter Page Data Structure Definition
Table 4 defines the parameter page data structure of nvSRAM.
The parameter page spans into multiple bytes and the least
significant byte of the parameter corresponds to the first byte in
P1
the parameter page data structure. Values are reported in the
parameter page in units of bytes. For a device that supports
16-bit data access, the upper 8 bits DQ[15:8] are not used and
are “Don’t Care” bits.
Table 4. Parameter Page Data Structure Definition
Byte
0–3
4–5
Parameter Description[5]
Value: (For SDR Timing Mode - 3) Value: (For SDR Timing Mode - 2)
×8
×16
×8
×16
Parameter page signature
Byte 0: 4Fh, “O”
4Fh
4Fh
4Fh
4Fh
Byte 1: 4Eh, “N”
4Eh
4Eh
4Eh
4Eh
Byte 2: 46h, “F”
46h
46h
46h
46h
Byte 3: 49h, “I”
49h
49h
49h
49h
00h, 02h
00h, 02h
00h, 02h
00h, 02h
Revision number
Bits 15–2: Reserved (0)
Bit 1: Supports ONFI version 1.0
Bit 0: Reserved (0)
Note
5. ( ) designates values shipped from the factory.
Document Number: 001-75528 Rev. *K
Page 12 of 32
CY14V116F7
CY14V116G7
Table 4. Parameter Page Data Structure Definition (continued)
Byte
6–7
Parameter Description[5]
Feature Supported
Value: (For SDR Timing Mode - 3) Value: (For SDR Timing Mode - 2)
×8
×16
×8
×16
00h, 00h
00h, 01h
00h, 00h
00h, 01h
00h, 00h
00h, 00h
00h, 00h
00h, 00h
Bits 15–1: Reserved (0)
Bit 0: When set to ‘1’, supports 16-bit data bus
width
8–9
Optional Command supported
Bits 15–3: Reserved (0)
Bit 2: Supports Get Feature and Set Feature
Bit 1–0: Reserved (0)
10–31
Reserved (0)
All bytes 00h
32–43
Device manufacturer (12 ASCII characters)
All bytes 00h
44–63
Device model (20 ASCII characters)
All bytes 00h
64
JEDEC manufacturer ID
65–66
Date Code (Optional)
All bytes 00h
67–79
Reserved (0)
All bytes 00h
80–100
Unused (0)
All bytes 00h
101
Number of address cycles
Bits 7–4: Column address cycles
Bits 3–0: Row address cycles
34h
32h
34h
32h
102–127 Unused (0)
128
I/O pin capacitance
129–130 Timing mode support
34h
34h
32h
32h
All bytes 00h
08h
08h
08h
08h
00h, 08h
00h, 08h
00h, 04h
00h, 04h
Bits 15–4: Reserved (0)
Bit 3: When set to ‘1’, supports timing mode 3
Bit 2: When set to ‘1’, supports timing mode 2
Bits 1–0: Reserved(0)
131–140 Unused (0)
All bytes 00h
141–163 Reserved (0)
All bytes 00h
164–253 Unused (0)
All bytes 00h
254–255 Integrity CRC
All bytes 00h
256–768 Reserved (0)
All bytes 00h
Document Number: 001-75528 Rev. *K
Page 13 of 32
CY14V116F7
CY14V116G7
Read Status (70h) Definition
The read status command retrieves a status value for the last operation issued. See Table 5 on page 15 (Status field definition) for
status register bit definitions. Figure 12 and Figure 13 define the read status behavior and timings.
SR: Status register bits are defined in Table 6 on page 15.
Figure 12. Read Status Operation
Cycle Type
CMD
DOUT
t WHR
DQ[7:0]
70h
SR
Figure 13. Read Status Timing
t CLR
CLE
t CLH
t CLS
t CS
CE
t CH
t WP
WE
t CEA
t WHR
t RP
RE
t CHZ
t COH
t RHZ
t RHOH
t DS
t DH
DQ[7:0]
70h
t IR
t REA
Status output
Don’t Care
Document Number: 001-75528 Rev. *K
Page 14 of 32
CY14V116F7
CY14V116G7
Status Field Definition
The read status register command returns the status register byte value (SR). If the RDY bit is cleared to zero, all other bits in the
status byte (except WP) are invalid and shall be ignored by the host. The RDY bit can be polled to check the ready or busy status
while a nvSRAM STORE or Software RECALL cycle is in progress.
Table 5. Status Field Definition
SR bit
7
6
5
4
3
2
1
0
Status Register
WP
RDY
X (0)
X (0)
X (0)
R (0)
X (0)
FAIL
Table 6. Status Register Bit Definition
SR Bit
SR Bit Definition
SR Bit Description
Bit 0
FAIL
This shows the status of the last executed command by the nvSRAM. The FAIL bit is set to
‘1’ if the last command did not execute successfully. The nvSRAM sets the FAIL bit when the
last command sent by the host did not get registered properly, or the command did not receive
the associated address bytes, or an invalid command was sent by the host.
Bit 1
Don’t care
Reading this bit always returns a ‘0’.
Bit 2
Reserved
Reading this bit always returns a ‘0’.
Bit 3
Don’t care
Reading this bit always returns a ‘0’.
Bit 4
Don’t care
Reading this bit always returns a ‘0’.
Bit 5
Don’t care
Reading this bit always returns a ‘0’.
Bit 6
RDY
If set to ‘1’, the nvSRAM is ready for another command and all other bits in the status value
are valid. If cleared to ‘0’, the last command issued is not yet complete and the SR bits 5:0
are invalid and shall be ignored by the host. This bit impacts the value of R/B accordingly.
This bit is set to ‘0’ by the device while a STORE or Software RECALL is in progress.
Bit 7
WP
If set to ‘1’, the device is not write protected. If cleared to ‘0’, the device is protected from
writing. This bit shall always be valid regardless of the state of the RDY bit.
nvSRAM Burst Mode Read (00h, 30h)
The nvSRAM enters the Read mode when the host controller
sends a 00h command, followed by five Address bytes, and the
30h second command cycle. After the read command is
registered, the nvSRAM starts sending data out on its DQ bus
after tREA time from the falling edge of the RE control signal on
every RE toggling. The nvSRAM allows reading in the Burst
mode, where the host can continue reading the data from the
device by repeatedly pulsing RE at the maximum tRC rate. The
host controller can read the entire memory by initiating a single
read request. In the burst mode read, the internal address
counter of the nvSRAM automatically increments to the next
addressable location and the device continues sending data on
its DQ bus. After the internal address counter reaches the last
addressable memory location, the counter rolls over to the start
address and continues sending data bytes. The device stays in
the Read mode until the read is interrupted by another valid
command. Refer to Figure 14 for the data output cycle timing.
Figure 14. Read Timing
Cycle Type
CMD
ADDR
ADDR
ADDR
ADDR
ADDR
CMD
DOUT
DOUT
DOUT
DQ
00h
ADD1
ADD2
ADD3
ADD4
ADD5
30h
D0
D1
D2
t WHR
Document Number: 001-75528 Rev. *K
Page 15 of 32
CY14V116F7
CY14V116G7
nvSRAM Burst Write (80h, 10h)
The nvSRAM enters the Write mode when the host controller
sends an 80h command, followed by five Address bytes, and
data bytes to be written. After the write command is initiated,
subsequent data bytes are written to the nvSRAM on every WE
toggle. The Write mode terminates when the host sends a 10h
command at the end of a write data cycle. The nvSRAM supports
the burst mode write operation, in which the host initiates the
Write command, once at the beginning of the write cycle, and
continues sending data bytes to be written by pulsing the WE.
The host should maintain the minimum write pulse width (tWP) of
WE, and setup (tCS) and hold (tCH) criteria for the CE signal.
When the burst mode write is in progress, the internal address
counter of the nvSRAM advances automatically after every data
word write. After the internal address counter reaches the last
addressable memory location, the address counter rolls over to
the starting address and continues writing data from the starting
address location by overwriting the previously written data.
Note Command 10h is an optional command for the nvSRAM
write operation and a successful write executes without the host
issuing this command. If the host executes the 10h command
when the write operation is in progress, the ongoing Write mode
is terminated.
Refer to Figure 15 for the data input cycle timing.
Figure 15. Write Timing
Cycle Type
CMD
ADDR
ADDR
ADDR
ADDR
ADDR
DIN
DIN
DIN
DIN
CMD
DQ
80h
ADD1
ADD2
ADD3
ADD4
ADD5
D0
D1
D2
DN
10h
t ADL
Reset (FFh) Definition
The Reset function puts the nvSRAM in its power-up state. The
reset command can be executed when the device is in any state,
except when a power-up RECALL operation is in progress.
When the power-up RECALL operation is in progress, the reset
command is not issued and the host must wait for R/B to become
HIGH after the device is ready. Figure 16 defines the Reset
behavior and timings.
For a device that supports 16-bit data access, the upper 8 bits
DQ[15:8] are not used and are “Don’t Care” bits.
Note If the Reset (FFh) command is issued when any NV
operation is in progress, then the reset request is executed only
after the ongoing NV operation is completed. Depending upon
the present state of the device, the tRST timing varies based on
the following:
■
If the reset command is executed when the device is ready, it
takes tSS time to process the reset request.
■
If the reset command is issued when the software RECALL
cycle is in progress, it takes tRECALL time to process the reset
request.
■
If the reset command is issued when a software or HSB STORE
cycle is in progress, it takes tSTORE time to process the reset
request.
Figure 16. Reset Timing Diagram
CLE
ALE
WE
RE
DQ[7:0]
FFh
t WB
t RST
R/B
Document Number: 001-75528 Rev. *K
Page 16 of 32
CY14V116F7
CY14V116G7
nvSRAM Software RECALL (FCh)
The software RECALL initiates a software RECALL operation in
the nvSRAM. The command may be executed any time when the
device is in the ready status. Figure 17 defines the nvSRAM
Software RECALL behavior and timings. After the software
RECALL command is registered by the nvSRAM, it takes tSS
time to process the software command before initiating the
Software RECALL operation internally. All accesses to the
nvSRAM, except reset (FFh) and read status (70h), are inhibited
during tRECALL time. During the RECALL operation, the nvSRAM
sets the RDY bit of the status register to '0' and pulls the R/B pin
to LOW for tRECALL duration. After the RECALL completes, the
RDY bit is set to ‘1’ and R/B is pulled to HIGH by an external
pull-up resistor indicating the ready status.
For a device that supports 16-bit data access, the upper 8 bits
DQ[15:8] are not used and are “Don’t Care” bits.
Figure 17. nvSRAM Software RECALL
Cycle type
CMD
DQ[7:0]
FCh
t WB
t RECALL
R/B
Software STORE (84h, A5h) in nvSRAM
Sending a software STORE command initiates a software
STORE operation within the nvSRAM, regardless of whether
there was an SRAM write or not. After the software STORE
command is registered, the device takes tSTORE time to complete
the STORE operation. All accesses to the nvSRAM, except
Reset (FFh) and read status (70h), are inhibited during the
STORE operation. After you initiate the STORE cycle, the
nvSRAM pulls the R/B pin LOW for tSTORE duration. The RDY bit
of the status register SR[6] transitions from ‘1’ to ‘0’ and remains
at '0' until the STORE cycle is completed. Figure 18 defines the
Software STORE behavior and timing. After the software STORE
command is initiated, it pulls the R/B signal LOW for tSTORE time
and all accesses, including FFh reset to the nvSRAM, are
disabled.
For a device that supports 16-bit data access, the upper 8 bits
DQ[15:8] are not used and are “Don’t Care” bits.
Cycle type
DQ[7:0]
CMD
84h
A5h
t WB
t STORE
R/B
nvSRAM AutoStore Disable (A3h)
The AutoStore disable command (A3h) disables the nvSRAM
AutoStore. All accesses to the nvSRAM, except Reset (FFh) and
read status (70h), are inhibited during tSS time. When the
AutoStore Enable command is executing, the device pulls R/B
Document Number: 001-75528 Rev. *K
For a device that supports 16-bit data access, the upper 8 bits
DQ[15:8] are not used and are “Don’t Care” bits.
Figure 19. nvSRAM AutoStore Disable
Cycle type
CMD
DQ[7:0]
A3h
t WB
t SS
R/B
nvSRAM AutoStore Enable (ACh)
Figure 18. Software STORE Timing
CMD
LOW for tSS time. Because this setting is volatile, you must
perform a manual software STORE operation if this is desired to
survive subsequent power cycles. The command may be
executed any time when the device is in the ready status.
Figure 19 defines the nvSRAM AutoStore disable timing.
The AutoStore enable command (ACh) enables the nvSRAM
AutoStore. All accesses to the nvSRAM, except reset (FFh) and
read status (70h), are inhibited during tSS time. When the
AutoStore Enable command is executing, the device pulls R/B
LOW for tSS time. Because this setting is volatile, you must
perform a manual software STORE operation if this is desired to
survive subsequent power cycles. The command may be
executed any time when the device is in the ready status.
Figure 20 defines the nvSRAM AutoStore enable timing.
For a device that supports 16-bit data access, the upper 8 bits
DQ[15:8] are not used and are “Don’t Care” bits.
Page 17 of 32
CY14V116F7
CY14V116G7
nvSRAM Store Operations
Figure 20. nvSRAM AutoStore Enable
Cycle type
CMD
DQ[7:0]
ACh
t WB
The nvSRAM stores data in the nonvolatile memory cell using
one of the three store operations. These three operations are:
AutoStore, automatically triggered on device power-down;
Hardware STORE, activated by the HSB; and Software STORE
activated by issuing a software command.
t SS
AutoStore Operation
R/B
Write Protect
Figure 21. Write Protect Disable Timing
Cycle Type
CMD
ADDR
ADDR
Note If the capacitor is not connected to the VCAP pin, disable
AutoStore using the AutoStore disable command (A3h). If
AutoStore is enabled without a capacitor on the VCAP pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This corrupts the nvSRAM data.
Figure 23. AutoStore Mode
VCCQ
ADDR
VCC
0.1uF
0.1uF
10 k:
The write protect feature disables the write operation in the
nvSRAM. When the WP pin is pulled LOW externally by the host
before initiating the write command (80h), the nvSRAM clears
the WP (SR[7]) status in the status register and disables the write
into the SRAM memory. However, writing into the status register
is not protected. The status of the write protect pin is latched by
the device along with the write command (80h) on the rising edge
of the WE signal. After the write protect status is latched, it is
locked for the current write cycle. After modifying the value of the
WP, the host shall not issue a new command to the device for at
least tWW time. The host must not toggle the WP pin during a
command cycle. Figure 21 describes the tWW timing
requirement, which shows the start of an nvSRAM write
command after toggling the WP. The transition of the WP signal
is asynchronous. The bus shall be idle for tWW time after every
WP transition from LOW to HIGH or HIGH to LOW before a new
command is issued by the host.
The AutoStore operation is a unique feature of the SONOS
technology and is enabled by default on the device. During
normal operation, the device draws current from VCC to charge
a capacitor connected to the VCAP pin. This stored charge is
used by the chip to perform a STORE operation during
power-down. If the voltage on the VCC pin drops below VSWITCH,
the part automatically disconnects the VCAP pin from VCC and a
STORE operation is initiated with power provided by the VCAP
capacitor.
VCCQ
VCC
ADDR
R/B
DQ
80h
t WPS
ADD1
ADD2
ADD3
VCAP
ADD4
t WPH
VCAP
VSS
WP
Don’t Care
Figure 22. Write Protect Enable Timing
Cycle Type
CMD
ADDR
ADDR
ADDR
ADDR
80h
ADD1
ADD2
ADD3
ADD4
DQ
t WPS
t WPH
WP
Don’t Care
Document Number: 001-75528 Rev. *K
Figure 23 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 20 for the size of the VCAP. The voltage
on the VCAP pin is driven to VVCAP by a regulator on the chip. A
pull-up resistor should be placed on R/B to hold it inactive during
power-up. This pull-up resistor is only effective if the R/B signal
is tristate during power-up. When the nvSRAM comes out of
power-up RECALL, the host microcontroller must be active or
the R/B held inactive until the host microcontroller comes out of
reset. To reduce unnecessary nonvolatile STOREs, AutoStore
and Hardware STORE operations are ignored unless at least
one write operation has taken place since the most recent
STORE or RECALL cycle.
Page 18 of 32
CY14V116F7
CY14V116G7
Hardware STORE (HSB) Operation
The device provides the HSB pin to control the Hardware
STORE operation. The HSB pin is used to request a Hardware
STORE cycle. When the HSB pin is driven LOW, the device
conditionally initiates a STORE operation after tDELAY. An actual
STORE cycle begins only if a write to the SRAM has taken place
since the last STORE or RECALL cycle. SRAM write operations
that are in progress when HSB is driven LOW by any means are
given time (tDELAY) to complete before the STORE operation is
initiated. However, any SRAM write cycles requested after HSB
goes LOW are inhibited until R/B returns HIGH. R/B remains
LOW by the device as long as HSB is LOW. Any SRAM read and
write cycles are inhibited until HSB is returned HIGH by host
microcontroller or any other external source. The HSB pin must
be set to HIGH during the normal device operation. If HSB is not
used in application, this pin should be pulled HIGH using an
external pull-up resistor of value between 4.7 k and 10 k.
Software Store Operation
The software store operation is initiated by sending a Software
STORE command (84h, A5h). The nvSRAM initiates a STORE
cycle irrespective of whether the write latch is set or not. Refer
to Software STORE (84h, A5h) in nvSRAM on page 17 for further
details.
Document Number: 001-75528 Rev. *K
nvSRAM RECALL Operations
The nvSRAM recalls data from the nonvolatile memory cell using
one of the two recall operations. These two recall operations are:
Hardware Recall, activated automatically by the device during a
power cycle or brown out, and a software initiated RECALL
cycle.
Hardware RECALL (Power-Up)
During power-up or after any low-power condition
(VCC < VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on power-up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the R/B pin is driven LOW by the nvSRAM and all reads
and writes to nvSRAM inhibited.
Software Recall
The software recall operation is initiated by sending a Software
RECALL command (FCh). The nvSRAM initiates a RECALL
cycle and overwrites the SRAM data with the recalled data from
the nonvolatile cell. Refer to the nvSRAM Software RECALL
(FCh) on page 17 for further details.
Page 19 of 32
CY14V116F7
CY14V116G7
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
At 150 C ambient temperature .................................. 1000h
At 85 C ambient temperature ............................... 20 Years
Transient voltage (< 20 ns)
on any pin to ground potential ..........–2.0 V to VCCQ + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Package Pb soldering temperature
(3 seconds) .............................................................. +260 C
DC output current (1 output at a time, 1s duration). .... 20 mA
Maximum Junction temperature ................................ 150 C
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Supply voltage on VCC relative to VSS .........–0.5 V to +4.1 V
Latch up current .................................................... > 140 mA
Supply voltage on VCCQ relative to VSS .......–0.5 V to +2.4 V
Operating Range
DC voltage applied to outputs
in HIGH Z State ................................–0.5 V to VCCQ + 0.5 V
Range
Input voltage .....................................–0.5 V to VCCQ + 0.5 V
Industrial
Ambient
Temperature (TA)
VCC
VCCQ
–40 C to +85 C 2.7 V to 3.6 V 1.70 V to 1.95 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ [6]
Max
Unit
2.7
3.0
3.6
V
VCC
Core power supply
VCCQ
I/O power supply
1.70
1.80
1.95
V
ICC1
Average VCC current
tRC > 30 ns
–
–
100
mA
ICCQ1
Average VCCQ current
CY14V116F7
tRC > 30 ns
Values obtained without
CY14V116G7
output loads (IOUT = 0 mA)
–
–
30
mA
–
–
60
mA
–
–
10
mA
ICC2
Average VCC current during All inputs don’t care, VCC = VCC (Max)
Average current for duration tSTORE
STORE
ICC3
Average VCC current
tRC > 200 ns;
VCC = VCC(Typ), 25 °C
All inputs cycling at CMOS levels.
–
–
50
mA
ICCQ3
Average VCCQ current
tRC > 200 ns;
VCCQ = VCCQ(Typ), 25 °C
All inputs cycling at CMOS CY14V116F7
levels. Values obtained
CY14V116G7
without output loads
(IOUT = 0 mA)
–
–
15
mA
–
–
30
mA
ICC4[7]
Average VCAP current during All inputs don't care. Average current for
duration tSTORE
AutoStore cycle
–
–
6
mA
ISB
VCC standby current
5
mA
ISB1
VCCQ standby current
CE > (VCCQ – 0.2 V).
VIN < 0.2 V or > (VCCQ – 0.2 V)
–
–
2
mA
IIX
Input leakage current
VCCQ = VCCQ (Max), VSS < VIN < VCCQ
–1
–
+1
A
IOZ
Output leakage current
VCCQ = VCCQ (Max), VSS < VIN < VCCQ;
output disabled
–1
–
+1
A
VIH
Input HIGH voltage
0.8 × VCCQ
–
VCCQ + 0.3
V
VIL
Input LOW voltage
VSS – 0.3
–
0.2 × VCCQ
V
VOH
Output HIGH voltage
VCCQ – 0.1
–
VCCQ
V
IOH = -100 A
–
–
Notes
6. Typical values are at 25 °C, VCC = VCC(Typ) and VCCQ = VCCQ(Typ). Not 100% tested.
7. This parameter is only guaranteed by design and is not tested.
Document Number: 001-75528 Rev. *K
Page 20 of 32
CY14V116F7
CY14V116G7
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
VOL
Description
Test Conditions
Output LOW voltage (except IOL = 100 A
R/B)
Output LOW voltage (for
R/B)
IOL = 3 mA
VCAP[8]
Storage capacitor
Between VCAP pin and VSS
VVCAP[9, 10]
Maximum voltage driven on VCC = VCC(Max)
VCAP pin by the device
Min
Typ [6]
Max
Unit
–
–
0.1
V
–
–
0.2
V
19.8
22.0
82.0
F
–
–
5.0
V
Data Retention and Endurance
Over the Operating Range
Parameter
Description
DATAR
Data retention
NVC
Nonvolatile STORE operations
Min
Unit
20
Years
1,000,000
Cycles
Capacitance
Parameter [10]
Description
Max
Unit
10
pF
Input capacitance on data and I/O
pins
10
pF
Capacitance on all other control
pins
10
pF
Test Conditions
165-ball FBGA
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
according to EIA / JESD51.
15.6
C/W
2.9
C/W
CIN
Input capacitance on clock and
input pins
CIO
COTHER
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC (Typ), VCCQ = VCCQ (Typ)
Thermal Resistance
Parameter [10]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Notes
8. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on
VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore, it
is always recommended to use a capacitor within the specified min and max limits.
9. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating
temperature range should be higher than the VVCAP voltage.
10. These parameters are guaranteed by design and are not tested.
Document Number: 001-75528 Rev. *K
Page 21 of 32
CY14V116F7
CY14V116G7
AC Test Conditions
Input pulse levels ............................................... 0 V to VCCQ
Input rise and fall times (10%–90%) .............................. 5 ns
Input and output timing reference levels ....................VCCQ/2
Figure 24. Driver Output Reference
NAND
Package
Rtt = 5 0 Ohm
Vtt = 0. 5 x VCCQ
Output
CL = 30 pF
Document Number: 001-75528 Rev. *K
Page 22 of 32
CY14V116F7
CY14V116G7
AC Switching Characteristics
Timing Modes
Over the Operating Range
Mode 2
[11]
Parameter
Description
Mode 3
35 ns
30 ns
Unit
Min
Max
Min
Max
100
–
ns
tADL
Address cycle to data loading time
100
–
tALH
ALE hold time
10
–
5
–
ns
tALS
ALE setup time
15
–
10
–
ns
tAR
ALE to RE delay
10
–
10
–
ns
tCEA
CE access time
–
30
–
25
ns
tCH
CE hold time
10
–
5
–
ns
tCHZ[12]
CE HIGH to output HIGH Z
–
50
–
50
ns
tCLH
CLE hold time
10
–
5
–
ns
tCLR
CLE to RE delay
10
–
10
–
ns
tCLS
CLE setup time
15
–
10
–
ns
tCOH
CE HIGH to output hold
15
–
15
–
ns
tIR
Output HIGH Z to RE LOW
0
–
0
–
ns
tCS
CE setup time
25
–
25
–
ns
tDH
Data hold time
5
–
5
–
ns
tDS
Data setup time
15
–
10
–
ns
tRC
RE cycle time
35
–
30
–
ns
tREA
RE access time
–
25
–
20
ns
tREH
RE HIGH hold time
15
–
10
–
ns
tRHOH
RE HIGH to output hold
15
–
15
–
ns
tRHW
RE HIGH to WE LOW
100
–
100
–
ns
tRHZ[12]
RE HIGH to output HIGH Z
–
100
–
100
ns
tRP
RE pulse width
17
–
15
–
ns
tRST[13]
Device reset time
–
500/600/
8000
–
500/600/
8000
µs
tWC
WE cycle time
35
–
30
–
ns
tWB
WE HIGH or clock rising edge to SR[6] LOW
–
100
–
100
ns
tWH
WE HIGH hold time
15
–
10
–
ns
tWHR
WE command, address or data input cycle to data output cycle
80
–
80
–
ns
tWP
WE pulse width
17
–
15
–
ns
tWW
WP transition to command cycle
100
–
100
–
ns
tWPS
WP set up time
25
–
25
–
ns
tWPH
WP hold time
10
–
10
–
ns
Notes
11. Test conditions assume a signal transition time of 5 ns or less, timing reference levels of VCCQ/2, input pulse levels of 0 to VCCQ(Typ), and output loading of the specified
IOL/IOH and 30-pF load capacitance shown in Figure 24.
12. These parameters are guaranteed by design and are not tested.
13. There are three maximums listed for tRST: Device is not performing any STORE or RECALL operation/Device is performing RECALL operation/Device is performing
STORE operation.
Document Number: 001-75528 Rev. *K
Page 23 of 32
CY14V116F7
CY14V116G7
nvSRAM AutoStore/Power-Up RECALL Characteristics
Parameter
tHRECALL
[14]
Description
Min
Max
Unit
Power-Up RECALL duration
–
30
ms
tSTORE [15]
STORE cycle duration
–
8
ms
tDELAY[16]
tVCCRISE[17]
Time allowed to complete SRAM write cycle
–
45
ns
150
–
µs
VSWITCH
LOW voltage trigger level for VCC
–
2.65
V
VIODIS
I/O disable voltage on VCCQ
–
1.6
V
tLZRB[17]
VRBDIS[17]
R/B to output active time
–
5
µs
R/B output disable voltage on VCC
–
1.9
V
VCC rise time
Figure 25. AutoStore or Power-Up RECALL [18, 19]
VCC
VSWITCH
VRBDIS
VCCQ
VIODIS
[15]
t VCCRISE
Note
tSTORE
Note
[15]
tSTORE
R/B
VCCQ
tDELAY
tLZRB
AutoStore
t LZRB
tDELAY
Power-Up
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI )
Power-Up
RECALL
Read & Write
Power-Up
RECALL
VCC
BROWN
OUT
AutoStore
Read
Read Power-down
AutoStore
&
&
Write V
Write
CCQ
BROWN
OUT
I/O Disable
Notes
14. tHRECALL starts from the time VCC rises above VSWITCH.
15. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
16. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
17. These parameters are guaranteed by design and are not tested.
18. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
19. Pin is driven HIGH to VCCQ only when an external pull-up is connected on the R/B pin. R/B driver is disabled.
Document Number: 001-75528 Rev. *K
Page 24 of 32
CY14V116F7
CY14V116G7
Hardware STORE Characteristics
Over the Operating Range
Parameter
Description
Min
Max
Unit
tPHSB
Hardware STORE pulse width
15
–
ns
tDRB
R/B to output active time when write latch not set
–
100
ns
tRECALL
RECALL duration
–
600
s
tSS[20]
Soft sequence processing time
–
500
s
Figure 26. Hardware STORE Cycle [21]
Write latch set
tPHSB
HSB
tSTORE
tHHHD
tWB
R/B
tLZRB
DQ (Data Out)
RWI
Write latch not set
tPHSB
R/B pin is driven HIGH to VCCQ only by external
pull-up resistor on R/B.
SRAM is disabled as long as HSB is driven low.
HSB
R/B
tWB
tDRB
tDRB
RWI
Notes
20. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
21. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated.
Document Number: 001-75528 Rev. *K
Page 25 of 32
CY14V116F7
CY14V116G7
Ordering Information
Ordering Code
CY14V116G7-BZ30XI
Package
Diagram
Package Type
51-85195 165-ball FBGA
Operating
Range
Industrial
CY14V116G7-BZ30XIT
Ordering Code Definitions
CY 14 V 116 F 7 - BZ 30 X I T
Option:
T - Tape and Reel
Blank - Std.
ES - Engineering Sample
Pb-free
Speed:
30 - 30 ns
Temperature:
I - Industrial (–40 °C to 85 °C)
Package:
BZ - 165-ball FBGA
7 - ONFI 1.0
F - ×8 NAND
G - ×16 NAND
Voltage:
V - 3.0 VCC, 1.8 V VCCQ
Density:
116 - 16-Mbit
14 - nvSRAM
Cypress
Document Number: 001-75528 Rev. *K
Page 26 of 32
CY14V116F7
CY14V116G7
Package Diagram
Figure 27. 165-ball FBGA (15 mm × 17 mm × 1.40 mm) Package Outline, 51-85195
51-85195 *D
Document Number: 001-75528 Rev. *K
Page 27 of 32
CY14V116F7
CY14V116G7
Acronyms
Acronym
Document Conventions
Description
ALE
address latch enable
CE
chip enable
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
Hz
hertz
kHz
kilohertz
k
kiloohm
CLE
command latch enable
CMOS
complementary metal oxide semiconductor
CRC
cyclic redundancy check
MHz
megahertz
EIA
electronic industries alliance
MT/s
million transfers for second
I/O
input/output
A
microampere
JEDEC
joint electron devices engineering council
F
microfarad
JESD
JEDEC Standards
s
microsecond
mA
milliampere
ms
millisecond
ns
nanosecond
nvSRAM
nonvolatile static random access memory
ONFI
open NAND flash interface
NV
nonvolatile
ohm
RE
read enable
pF
picofarad
RoHS
restriction of hazardous substances
V
volt
R/W
read/write
W
watt
RWI
read and write inhibited
SR
status register
WE
write enable
Document Number: 001-75528 Rev. *K
Page 28 of 32
CY14V116F7
CY14V116G7
Document History Page
Document Title: CY14V116F7/CY14V116G7, 16-Mbit nvSRAM with Asynchronous NAND Interface
Document Number: 001-75528
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
3508602
GVCH
02/02/2012
New data sheet.
*A
3746140
GVCH
09/17/2012
Replaced CY14V116FX and CY14V116GX with CY14V116F7 and
CY14V116G7.
Updated Basic Operations (Updated Table 4, updated nvSRAM Burst Write
(80h, 10h) (description), updated Reset (FFh) Definition (no change in
description, updated Figure 16 only), updated nvSRAM Software RECALL
(FCh) (no change in description, updated Figure 17 only), updated Software
STORE (84h, A5h) in nvSRAM (no change in description, updated Figure 18
only), updated nvSRAM AutoStore Disable (A3h) (no change in description,
updated Figure 19 only), updated nvSRAM AutoStore Enable (ACh) (no
change in description, updated Figure 20 only, updated Write Protect (no
change in description, added Figure 21 and Figure 22 only)).
Updated Maximum Ratings (Removed “Ambient temperature with power
applied” and added “Maximum junction temperature”).
Updated DC Electrical Characteristics (Splitted the Test Conditions of ICCQ1,
ICCQ3 parameters into two rows (one for CY14V116F7 and another for
CY14V116G7), retained the original values for CY14V116F7 row and added
new values for CY14V116G7 row).
Updated Capacitance (Changed maximum value of CIN and CIO parameters
from 7 pF to 11.5 pF).
Updated AC Switching Characteristics (Updated Timing Modes (Added tWPS,
tWPH parameters and their details)).
Added nvSRAM AutoStore/Power-Up RECALL Characteristics table and
Switching Waveforms (corresponding to it (Figure 25)).
Added Hardware STORE Characteristics and Switching Waveforms
(corresponding to it (Figure 26)).
*B
3944873
GVCH
03/26/2013
Updated Basic Operations:
Updated Read Parameter Page (ECh):
Updated Parameter Page Data Structure Definition:
Updated Table 4 (almost entire table).
Removed “Get Features (EEh) Definition”.
Removed “Set Features (EFh) Definition”.
Updated DC Electrical Characteristics:
Changed maximum value of VCCQ parameter from 1.9 V to 1.95 V.
Changed maximum value of ISB parameter from 15 mA to 5 mA.
Changed maximum value of ISB1 parameter from 5 mA to 2 mA.
Updated Capacitance:
Changed maximum value of CIN and CIO parameters from 11.5 pF to 8 pF.
Changed maximum value of COTHER parameter from 20 pF to 8 pF.
Updated AC Switching Characteristics:
Updated Timing Modes:
Removed tCEH parameter and its details.
Completing Sunset Review.
Document Number: 001-75528 Rev. *K
Description of Change
Page 29 of 32
CY14V116F7
CY14V116G7
Document History Page (continued)
Document Title: CY14V116F7/CY14V116G7, 16-Mbit nvSRAM with Asynchronous NAND Interface
Document Number: 001-75528
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*C
4260504
GVCH
01/24/2014
Updated Pin Definitions:
Added Note 1 and referred the same note in “DQ[7:0]” and “DQ[15:0]” pins.
Updated nvSRAM Bus Modes:
Updated nvSRAM Address Input:
Updated Table 2:
Added Note 2 and referred the same note in “A20/LOW” in “DQ4” column.
Updated Command Definition:
Updated Table 3 (Updated Note 4 (for more clarity)).
Updated Basic Operations:
Updated Read ID (90h) Definition:
Updated description (Added DID values for ×8 and ×16 part).
Updated nvSRAM Store Operations:
Updated AutoStore Operation:
Updated description (Removed “The HSB signal is monitored by the system
to detect if an AutoStore cycle is in progress”).
Updated DC Electrical Characteristics:
Changed minimum value of VCAP parameter from 20 F to 19.8 F.
Updated nvSRAM AutoStore/Power-Up RECALL Characteristics:
Updated Figure 25 (for more clarity).
Completing Sunset Review.
*D
4286722
GVCH
02/20/2014
Updated Ordering Information:
No change in part numbers.
Updated Ordering Code Definitions:
Minor formatting correction.
*E
4417851
GVCH
06/24/2014
Updated nvSRAM Bus Modes:
Updated Command Definition:
Updated Table 3 (Added Reserved commands and its details).
Updated DC Electrical Characteristics:
Added Note 7 and referred the same note in ICC4 parameter.
Changed maximum value of VVCAP parameter from 4.5 V to 5.0 V.
Updated Capacitance:
Changed values of CIN, CIO and COTHER from 8 pF to 10 pF.
Updated Thermal Resistance:
Updated all values of JA and JC parameters.
Updated nvSRAM AutoStore/Power-Up RECALL Characteristics:
Removed tRBHD parameter and its details.
Updated Figure 25.
Completing Sunset Review.
*F
4432183
GVCH
07/07/2014
Updated DC Electrical Characteristics:
Changed maximum value of VCAP parameter from 120.0 F to 82.0 F.
*G
4456803
ZSK
07/31/2014
No technical updates.
Completing Sunset Review.
*H
4541059
GVCH
10/16/2014
Updated DC Electrical Characteristics:
Updated details in “Test Conditions” columns corresponding to ICC1, ICCQ1,
ICC3, ICCQ3 parameters.
*I
4568158
GVCH
11/13/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
4616093
GVCH
01/07/2015
Changed status from Preliminary to Final.
Updated Ordering Information:
Updated part numbers.
Completing Sunset Review.
Document Number: 001-75528 Rev. *K
Page 30 of 32
CY14V116F7
CY14V116G7
Document History Page (continued)
Document Title: CY14V116F7/CY14V116G7, 16-Mbit nvSRAM with Asynchronous NAND Interface
Document Number: 001-75528
Rev.
ECN No.
Orig. of
Change
Submission
Date
*K
6015693
GVCH
01/05/2018
Document Number: 001-75528 Rev. *K
Description of Change
Updated Package Diagram:
spec 51-85195 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
Page 31 of 32
CY14V116F7
CY14V116G7
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2012-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-75528 Rev. *K
Revised January 5, 2018
Page 32 of 32
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