CY2037B-11WAF-

CY2037 High-Accuracy EPROM Programmable PLL Die for Crystal Oscillators Features ■ ■ ■ ■ ■ ■ ■ ■ Benefits ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ EPROM-programmable die for in-package programming of crystal oscillators High resolution PLL with 12-bit multiplier and 10-bit divider EPROM-programmable capacitor tuning array with shadow register Twice programmable die (CY2037A, CY2037B[1], and CY2037-2) Simple 2-wire programming interface On-chip oscillator runs from 10 - 30 MHz fundamental tuned crystal EPROM-selectable TTL or CMOS duty cycle levels Operating frequency: ❐ 1 - 133 MHz at 5V ❐ 1 - 100 MHz at 3.3V ❐ 1 - 66.6 MHz at 2.7V Sixteen selectable post divide options, using PLL or reference oscillator output Programmable power down (PD#) or OE pin (CY2037A, CY2037B, and CY2037-2) Frequency select (CY2037-3) Programmable asynchronous or synchronous OE and power down (PD#) modes (CY2037A, CY2037B, and CY2037-2) Low jitter outputs typically: ❐ < ± 100 ps (pk-pk) at 5V and f>33 MHz ❐ < ± 125 ps (pk-pk) at 3.3V and f>33 MHz 3.3V or 5V operation Small die Controlled rise and fall times and output slew rate Enables quick turnaround of custom oscillators Lowers inventory costs through stocking of blank parts Enables synthesis of highly accurate and stable output clock frequencies with zero or low PPM Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal Enables reprogramming of programmed part to correct errors, and control excess inventory Enables programming of output frequency after packaging Lowers cost of oscillator because PLL may be programmed to a high frequency using a low frequency, low cost crystal Duty cycle centered at 1.4V or VDD/2 Provides flexibility to service most TTL or CMOS applications Provides flexibility in output configurations and testing Enables low power operations or output enable functions Enables two frequency options for meeting different industry standards, that is, PAL/NTSC Provides flexibility for system applications through selectable instantaneous or synchronous change in outputs Suitable for most PC, consumer, and networking applications Lowers inventory costs because the same die services both applications Enables encapsulation in small size, surface mount packages Has lower EMI than oscillators ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Device Functionality: Output Frequencies Parameter Fo Description Output frequency Condition VDD = 4.5V–5.5V VDD = 3.0V–3.6V VDD = 2.7V–3.0V Min 1 1 1 Max 133 100 66 Unit MHz MHz MHz Note 1. CY2037A and CY2037B are identical. However, CY2037B is recommended for all new designs. Cypress Semiconductor Corporation Document Number: 38-07354 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 06, 2008 [+] Feedback CY2037 Logic Block Diagram PD#/OE or FS XG XD CRYSTAL OSCILLATOR HIGH ACCURACY PLL CONFIGURATION EPROM MUX / 1, 2, 4, 8, 16, 32, 64, 128 CLKOUT Document Number: 38-07354 Rev. *E Page 2 of 11 [+] Feedback CY2037 Die Pad Description Horizontal scribe VDD VDD XX CLKOUT N/C Note Active die size: X = 55.9 mils / 1420.1 μm Vertical scribe Scribe: X (horizontal) = 2.6 mils / 65.6 μm Y (vertical) = 3.0 mils / 76.9 μm Bond pad opening: 85 μm x 85 μm Pad pitch: 125 μm x 125 μm (pad center to pad center) XD N/C XR XG PD#/OE or FS Y Device Name VSS VSS X Die Pad Summary Name VDD VSS XD XX XG PD#/OE or FS Die Pad 1, 2 8, 9 4 3 6 7 X Coordinate (μm) 124.7 1291.35 124.7 124.7 124.7 124.7 Y Coordinate (μm) 855.6, 731 99.6, 225.2 481.8 606.4 232.6 108 Voltage supply Ground Crystal connection No connect [2] Crystal connection CY2037A, CY2037B, and CY2037-2: EPROM-programmable power down or output enable pad CY2037-3: Frequency select. Serves as VPP in programming mode for all devices Clock output. Also serves as three-state input during programming. No connect (so do not bond to these pads) Description CLKOUT N/C 11 5, 10 1282.45 124.7,1282.45 901.8 357.2, 769.4 Note 2. For customers not bonding the XD or XG pad to external pins, an alternative bonding option would be shorting the Xx pad to the XD pad. Document Number: 38-07354 Rev. *E Page 3 of 11 [+] Feedback CY2037 Functional Description CY2037 is an EPROM-programmable, high accuracy, PLL-based die designed for the crystal oscillator market. The die attaches directly to a low cost 10 - 30 MHz crystal and can be packaged into a 4-pin through-hole or surface mount packages. The oscillator devices may be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. This enables fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals. CY2037 contains an on-chip oscillator and a unique oscillator tuning circuit for fine-tuning of the output frequency. The crystal Cload may be selectively adjusted by programming a set of seven EPROM bits. This feature is used to compensate for crystal variations or to obtain a more accurate synthesized frequency. CY2037 uses EPROM programming with a simple 2-wire, 4-pin interface that includes VSS and VDD. Clock outputs may be generated up to 133 MHz at 5V or up to 100 MHz at 3.3V. The entire configuration can be reprogrammed once, which allows the programmed inventory to be altered or reused. CY2037 PLL die is designed for very high resolution. It has a 12-bit feedback counter multiplier and a 10-bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with zero or low PPM error. The clock is further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64, and 128. The divider input can be selected as the PLL or crystal oscillator output, providing a total of 16 separate output options. For further flexibility, the ouput is selectable between TTL and CMOS duty cycle levels. CY2037, CY2037B, and CY2037-2 also contain flexible power management controls. These parts include both power down (PD#) and OE features with integrated pull up resistors. The PD# and OE modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. When PD# or OE modes are enabled, CLKOUT is pulled low by a weak pull down. The weak pull down is easily overdriven by another active CLKOUT for applications that require multiple CLKOUTs on a single signal path. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable CY2037 to have low jitter and accurate outputs, making it suitable for most PC, networking, and consumer applications. On the other hand, CY2037-3 contains a frequency select function in place of the power down and output enable modes. For example, consumer products often require frequency compatibility with different electrical standards around the world. With this frequency select feature, a product that incorporates CY2037-3 could be compatible with both NTSC for North American, and PAL for Europe by simply changing the FS line. The twice programmable feature is also absent in CY2037-3, because the second EPROM row is now being used for the alternate frequency. EPROM Configuration Block Table 2 summarizes the features that are configurable by EPROM. Refer “7C8038x/7C8034X Programming Specification” for further details. This specification can be obtained from your Cypress factory representative. . Table 2. EPROM Adjustable Features Adjustable Features Adjust Frequency Feedback Counter Value (P) Reference Counter Value (Q) Output Divider Selection Oscillator Tuning (Load Capacitance Values) Duty Cycle Levels (TTL or CMOS) Power Management Mode (OE or PD#) Power Management Timing (Synchronous or Asynchronous) PLL Output Frequency CY2037 contains a high resolution PLL with 12-bit multiplier and 10-bit divider. The output frequency of the PLL is determined by the following formula: 2 • (P + 5) F PLL = --------------------------- • F REF (Q + 2) In this formula, P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values. Power Management Features (except CY2037-3) CY2037 contains EPROM-programmable PD# and OE functions. If power down is selected, all active circuitry on the chip is shut down when the control pin goes LOW. The oscillator and PLL circuits must relock when the part leaves the power down mode. If output enable mode is selected, the output is tri-stated and weakly pulled low when the control pin goes low. In this mode the oscillator and PLL circuits continue to operate, allowing a rapid return to normal operation when the control input is deasserted. In addition, the PD# and OE modes can be programmed to occur synchronously or asynchronously with respect to the output signal. When the asynchronous setting is used, the power down or output disable occurs immediately (allowing for logic delays), regardless of the position in the clock cycle. However, when the synchronous setting is used, the part waits for a falling edge at the output before the power down or output enable signal is initiated, thus preventing output glitches. In asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of the output. Document Number: 38-07354 Rev. *E Page 4 of 11 [+] Feedback CY2037 Crystal Oscillator Tuning Circuit CY2037 contains a unique tuning circuit to fine-tune the output frequency of the device. The tuning circuit consists of an array of eleven load capacitors on both sides of the oscillator drive inverter. The capacitor load values are EPROM-programmable and may be increased in small increments. As the capacitor load is increased the circuit is fine-tuned to a lower frequency. The capacitor load values vary from 0.17 pF to 8 pF for a 100:1 total control ratio. The tuning increments are shown in Table 3. Refer to “7C8038x/7C8034x Programming Specification” for further details. Figure 1. Crystal Oscillator Tuning Circuit Rf External Crystal C6 C5 C4 C3 C2 C1 C0 Cgo Cdo C7 C8 C9 C10 CD6 CD5 CD4 CD3 CD2 CD1 CD0 CD3 CD4 CD5 CD6 CD = EPROM BIT T = TRANSISTOR C = LOAD CAPACITOR Table 3. Crystal Oscillator Parameter Parameter Rf Description Feedback resistor, VDD = 4.5–5.5V Feedback resistor, VDD = 2.7–3.6V Gate capacitor Drain capacitor Series cap Series cap Series cap Series cap Series cap Series cap Series cap Series cap Series cap Series cap Series cap Min 0.5 1.0 Typ. 2 4 13 9 0.27 0.52 1.00 0.7 1.4 2.6 5.0 0.45 0.85 1.7 3.3 Max 3.5 9.0 Unit MΩ MΩ pF pF pF pF pF pF pF pF pF pF pF pF pF Capacitors have ± 20% tolerance Cg Cd C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 Document Number: 38-07354 Rev. *E Page 5 of 11 [+] Feedback CY2037 CY2037A/CY2037B Versus CY2037-2 CY2037A and CY2037B contain a shadow register in addition to the EPROM register. The shadow register is an exact copy of the EPROM register and is the default register when the Valid bit is not set. It is useful when the prototype or production environment calls for measuring and adjusting the CLKOUT frequency several times. Multiple adjustments can be performed with the shadow register. After the required frequency is achieved the EPROM register is permanently programmed. Some production flows do not require the use of the shadow register. If this is the case, then CY2037-2 is the chosen device and CY2037-2 has a disabled shadow register. CY2037-3 contains the shadow register. Inkless Die Pick Map (DPM) Format Cypress ships inkless wafers to customers with an accompanying die pick map, which is used to determine the good die for assembly and programming. Customers can also access individual DPM files at their convenience through ftp.cypress.com with a valid user account login and password. Contact your local Cypress Field Application Engineer (FAE) or sales representative for a customer FTP account. The DPM files are named with the fab lot number and wafer number scribed on the wafer. The DPM files are transferred to the customer’s FTP account when the factory ships out the wafers against their purchase order (PO). Frequency Select Feature of CY2037-3 CY2037-3 contains a frequency select function in place of the powerdown and the output enable functions. With the frequency select feature, customers can switch two different frequencies that are configured in the two EPROM rows. Table 4 lists the definition of the frequency select pin (FS). Table 4. Frequency Select Pin Decoding for CY2037-3 FS Pin 0 1 Output Frequency From EPROM row 0 configuration From EPROM row 1 configuration Document Number: 38-07354 Rev. *E Page 6 of 11 [+] Feedback CY2037 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.[3] Supply voltage .................................................. –0.5 to +7.0V Input voltage .............................................. –0.5V to VDD+0.5 Storage temperature (non-condensing)........ 55°C to +150°C Junction temperature.................................. –40°C to +100°C Static discharge voltage............................................... 2000V (per MIL-STD-883, Method 3015) Operating Conditions Parameter VDD TAJ [4] CTTL Supply voltage (3.3V) Supply voltage (5.0V) Operating temperature, Junction Max. capacitive load on outputs for TTL levels VDD = 4.5–5.5V, output frequency = 1 - 40 MHz VDD = 4.5–5.5V, output frequency = 40 - 133 MHz CCMOS Max. capacitive load on outputs for CMOS levels VDD = 4.5–5.5V, output frequency = 1 - 66.6 MHz VDD = 4.5–5.5V, output frequency = 66.6 - 133 MHz VDD = 3.0–3.6V, output frequency = 1 - 40 MHz VDD = 3.0–3.6V, output frequency = 40 - 100 MHz VDD = 2.7–3.0V, output frequency = 1 - 66 MHz XREF tPU Reference frequency, input crystal. Fundamental tuned crystals only Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 10 0.05 30 50 MHz ms Description Min 2.7 4.5 –10 Max 3.6 5.5 +100 50 25 50 25 30 15 15 Unit V V °C pF pF pF pF pF pF pF Electrical Characteristics Over the Operating Range[5] Parameter VIL VIH VOL VOHCMOS VOHTTL IIL IIH IDD IDDS[6] RUP Description Low level input voltage High level input voltage Low level output voltage High level output voltage, CMOS levels High level output voltage, TTL levels Input low current Input high current Power supply current, Unloaded Standby current Input pull up resistor VIN = 0V VIN = VDD VDD = 4.5V - 5.5V, output frequency