CY2040

CY2040-2/3 32 kHz and 24 MHz Clock Generator with Precision 32 kHz Input Features • • • • Precision RTC 32 kHz and 24 MHz output Power-down mode (32 kHz on) is < 50 uA Suspend mode (V24M = off) is typically 5 uA Low RMS period Jitter (< 40 ps) • 16-pin TSSOP package • 3.3V + 5% Voltage Supply • CY2040-2 multiplier 32.000 kHz × 750 = 24.0 MHz (requires a single 32.000 kHz crystal) • CY2040-3 enables the 32 kHz and 24.0 MHz oscillators (requires a 32.768 kHz and 24.000 MHz crystal) Logic Block Diagram XIN32K XOUT32K 32kHz OSC Pin Configuration OUT32K NC 32K P LLE N P D24M # V32K 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VSS O UT24M O UT32KPLL O UT32K XO UT24M X IN 2 4 M VSS NC Q=INPUT DIVIDER PLL V24M POST DIVIDER X IN 3 2 K XO UT32K NC P=FEEDBACK DIVIDER OUT24M XIN24M XOUT24M 24MHz OSC OUT32KPLL PD24M# 32KPLLEN CONTROL LOGIC Cypress Semiconductor Corporation Document #: 38-07122 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 14, 2002 CY2040-2/3 Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol NC 32KPLLEN PD24M# V32K[1] V24M[1] XIN32K XOUT32K NC NC VSS Xin24M OUT24M OUT32K OUT32KPLL OUT24M VSS Type NC I, PU I, PU P P I O NC NC P I O O O O P Description No connection (leave it floating). OUT32KPLL (pin 14) output enable (OE). 1 = running, 0 = 3-state. Weak pull-up. Power down pin to turn off OUT32M, OUT32KPLL, PLL, post divider and 24-MHz crystal oscillator. Active Low. 1 = running, 0 = power down. Weak pull-up. 3.3V supply for the 32 kHz oscillator circuit (Vbatt). 3.3V supply for the 24 MHz oscillator and PLL circuits (VDD). Crystal connection input for OSC1. Recommend using CLoad = 6 pF crystal with ESR