CY2048WAF

CY2048WAF Flash Programmable Capacitor Tuning Array Die for Crystal Oscillator(XO) Features • Flash-programmable capacitor tuning array for low ppm initial frequency clock output • Low clock output jitter — 4 ps typ. RMS period jitter — ±30 ps typ. peak-to-peak period jitter • Flash-programmable dividers • Two-pin programming interface • On-chip oscillator runs from 10–48-MHz crystal • Five selectable post-divide options, using reference oscillator output • Programmable asynchronous or synchronous OE and PWR_DWN modes • 2.7V to 3.6V operation • Controlled rise and fall times and output slew rate Benefits • Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal • Allows multiple programming opportunities to correct errors, and control excess inventory • Enables programming of output frequency after packaging • PPM clock output error can be adjusted in package • Provides flexibility in output configurations and testing • Enables low-power operation or output enable function • Provides flexibility for system applications through selectable instantaneous or synchronous change in outputs • Enables encapsulation in small-size, surface-mount packages Block Diagram PD#/OE (SDATA/VPP) CONFIGURATION XIN XOUT OSCILLATOR CRYSTAL / 1, 2, 4, 8, 16 OUT (SCL) VDD VSS Die Pad Description H o riz o n ta l S c rib e 1 VDD Notes: OUT 6 X(max): 980 µm, Y(max): 988 µm V e rtic a l S c rib e Y (m a x ) 2 XOUT X IN P D # /O E Scribe: X = 70 µm, Y = 86 µm Bond pad opening: 85 µm x 85 µm Pad pitch: 175 µm (min.) Wafer thickness: 11 mils (Typ.) 3 7C80330A VSS 5 4 d ie # /re v X (m a x ) Cypress Semiconductor Corporation Document #: 38-07738 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 12, 2005 CY2048WAF Die Pad Summary (Pad coordinates are referenced from the center of the die (X = 0, Y = 0)) Name VDD XOUT XIN PD#/OE VPP SDATA OUT SCL VSS 5 6 Pad Number 1 2 3 4 Voltage Supply Oscillator Drain Oscillator Gate Programmable power-down or output enable pin High voltage for programming NV memory Serial data pin used for programming in test mode Clock output Serial clock for programming in test mode Ground 360.0 –354.5 360.0 353.7 Description X coordinate (µm) –360.8 –360.8 –360.8 –360.8 Y coordinate (µm) 353.7 134.1 –42.6 –275.9 Document #: 38-07738 Rev. *A Page 2 of 7 CY2048WAF Absolute Maximum Conditions (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage (VDD) ........................................–0.5 to +7.0V DC Input Voltage...................................... –0.5V to VDD + 0.5 Output Short Circuit Current ..................................... ± 50 mA Storage Temperature (Non-condensing) .... –55°C to +125°C Junction Temperature ................................ –40°C to +125°C Data Retention @ Tj = 125°C................................> 10 years ESD (Human Body Model) MIL-STD-883................. > 2000V Crystal Specifications[1] Parameter FNOM R1 R3/R1 C0 C1 Description Nominal crystal frequency Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal shunt capacitance Crystal motional capacitance Comments Fundamental mode, AT cut Fundamental mode Ratio used because typical R1 values are much less than the maximum spec Min. Typ. 10 – 4.5 – 2 – – – – – Max. 48 40 – 5 – Unit MHz Ω – pF fF Operating Conditions Parameter VDD TJ CXIN CXOUT CL COUT tRAMP TS Operating Voltage Junction Temperature Capacitance XIN, all tuning caps OFF Capacitance XOUT, all tuning caps OFF All tuning Caps OFF All tuning Caps ON Output Load Capacitance Power-up time for VDD to reach minimum specified voltage (power ramps must be monotonic) Start up time, 90% VDD to valid frequency on output Description Min. 2.7 –40 – – 4 9.2 – 0.05 – Typ. – – 10 10 5 10 – – – Max. 3.6 125 – – 6 11.4 15 500 10 Unit V °C pF pF pF pF pF ms ms DC Electrical Specifications TJ = –40 to 125°C over the operating range Parameter VIL VIH VOL VOH IIL IIH IOZL IOZH IDD IPD RUP RDN CIN RF Description Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Leakage Current Output Leakage Current Power Supply Current Power Down Current Input Pull-up resistor Output Pull-down resistor Input Pin Capacitance Crystal Feedback R Condition CMOS Levels CMOS Levels VDD = 2.7V–3.6V, IOL = 8 mA VDD = 2.7V–3.6V, IOL = –8 mA Input = VSS Input = VDD Output = VSS Output = VDD No Load, VDD = 3.3V, 48 MHz PD# = 0V VIN = VSS VIN> = 0.8VDD VIN = 0.5VDD PD#/OE pin XIN = 0 Min. – 80 – VDD–0.4 – – – – – – 1 80 500 – 300 Typ. – – – – 1 1 1 – – – 3 120 900 – – Max. 20 – 0.4 – 10 10 10 50 20 25 6 150 1500 7 800 Unit %VDD %VDD V V µA µA µA µA mA µA MΩ kΩ kΩ pF kΩ Note: 1. Not 100% tested. Document #: 38-07738 Rev. *A Page 3 of 7 CY2048WAF AC Electrical Specifications[1] over the operating range, except as noted Parameter[1] FOUT DC TR TF tPJ1 tPJ2[2] DL –R FDRIFT Description Output Frequency Output Duty Cycle Rise Time Fall Time RMS Period Jitter Peak-to-peak Period Jitter Crystal drive level Negative Resistance Output Frequency Drift XTAL Buffered or Divided Output Clock Rise Time, Measured from 20% to 80% of VDD, COUT = 15 pF. Output Clock Fall Time, Measured from 80% to 20% of VDD, COUT = 15 pF. XIN = 10–48 MHz. Measured at VDD/2 XIN = 10–48 MHz. Measured at VDD/2 48-MHz crystal, CL = 7 pF, C0 = 2 pF, R1 = 10 Ohms, Temp. = 25°C, VDD = 3.6V Measured at 48 MHz, CL = 10 pF, C0 = 5 pF 3.0V ± 10%, 3.3V ± 10% for Temp. = 25°C – –2 – – 4 30 350–400 – – –150 2 Condition Min. 0.625 45 Typ. – 50 Max. 48 55 2.5 2.5 15 80 Unit MHz % ns ns ps ps µW Ω ppm Phase Noise, Temp = 25°C, VDD = 3.3V, FNOM = 10MHz, XCAP = 7F (Hex) Offset 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz dBc/Hz (Typ) –90 –115 –130 –140 –140 –140 Crystal Oscillator Tuning Capacitor Values Capacitor Bit C7 C6 C5 C4 C3 C2 C1 C0 Capacitance (pF) per Side 5.000 2.500 1.250 0.625 0.313 0.156 0.078 0.039 XIN XOUT CXIN CXOUT C7 C6 C5 C4 C3 C2 C1 C0 C0 C1 C2 C3 C4 C5 C6 C7 Figure 1. Programmable Load Capacitance Notes: 2. TPJ2 measured using DTS-2075, # of events set to 10, 000. Document #: 38-07738 Rev. *A Page 4 of 7 CY2048WAF Timing Parameters over the operating range Parameter TSTP,SYNC TSTP,ASYNC TPU,SYNC TPU,ASYNC TPZX,SYNC TPZX,ASYNC TPXZ,SYNC TPXZ,ASYNC Description Time from falling edge on PD# to stopped output, synchronous mode, T=1/Fout Time from falling edge on PD# to stopped output, asynchronous mode Time from rising edge on PD# to output at valid frequency, synchronous mode, T = 1/Fout Time from rising edge on PD# to output at valid frequency, asynchronous mode Time from rising edge on OE to running output, synchronous mode, T=1/Fout Time from rising edge on OE to running output, asynchronous mode Time from falling edge on OE to high impedance output, synchronous mode, T = 1/Fout Time from falling edge on OE to high impedance output, asynchronous mode Min. Max. 1.5T + 350 350 3 3 1.5T + 350 350 1.5T + 350 350 Unit ns ns ms ms ns ns ns ns PD TPU CLOCK SYNC TSTP CLOCK ASYNC T TSTP Weakly pulled LOW Weakly pulled LOW Figure 2. Power-down Timing OE CLOCK SYNC T PZX CLOCK ASYNC T T PZX Weakly pulled LOW TPXZ Weakly pulled LOW T XZ P Figure 3. Output Enable Timing VDD - 10% POWER 0V tRAMP OUT TS Figure 4. VDD Power-up Timing Document #: 38-07738 Rev. *A Page 5 of 7 CY2048WAF Test and Measurement Set-up VDD 0.1 µF DUT Output CLOAD GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 5. Duty Cycle Definition tR tF V DD 80% of V DD 20% of VDD 0V Clock Output Figure 6. Ordering Information Ordering Code CY2048WAF[3] Package Type Wafer Operating Range (TJ) Industrial,–40 °C to 125°C Note: 3. The product is offered as tested die-on-wafer form. Contact Cypress Sales for additional programming information and support. All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07738 Rev. *A Page 6 of 7 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2048WAF Document History Page Document Title: CY2048WAF Flash Programmable Capacitor Tuning Array Die for Crystal Oscillator(XO) Document Number: 38-07738 REV. ECN NO. Issue Date ** *A 319840 413511 See ECN See ECN Orig. of Change RGL RGL New data sheet Minor Change: Pls. post in the web Description of Change Document #: 38-07738 Rev. *A Page 7 of 7