CY2071ASL

CY2071A Single-PLL General-Purpose EPROM Programmable Clock Generator Features Single phase-locked loop architecture EPROM programmability Benefits Generates a custom frequency from an external source Easy customization and fast turnaround Factory-programmable (CY2071A, CY2071AI) or field- Programming support available for all opportunities programmable (CY2071AF, CY2071AFI) device options Up to three configurable outputs Low-skew, low-jitter, high-accuracy outputs Internal loop filter Power management (OE) Frequency select options Configurable 5V or 3.3V operation 8-pin 150-mil SOIC package i Generates three related frequencies from a single device Meets critical industry standard timing requirements Alleviates the need for external components Supports low-power applications 3 outputs with 2 user selectable frequencies Supports industry standard design platforms Industry-standard packaging saves on board space Selector Guide Part Number CY2071A CY2071AI CY2071AF CY2071AFI Outputs 3 3 3 3 Input Frequency Range 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) Output Frequency Range 500 kHz–130 MHz (5V) 500 kHz–100 MHz (3.3V) 500 kHz–100 MHz (5V) 500 kHz–80 MHz (3.3V) 500 kHz–100 MHz (5V) 500 kHz–80 MHz (3.3V) 500 kHz–90 MHz (5V) 500 kHz–66.6 MHz (3.3V) Specifics Factory Programmable Commercial Temperature Factory Programmable Industrial Temperature Field Programmable Commercial Temperature Field Programmable Industrial Temperature Logic Block Diagram for CY2071A XTALIN XTALOUT PLL Block REFERENCE OSCILLATOR CLKA EPROMConfigurable Multiplexer and Divide Logic CLKB CLKC OE / FS Pin Configuration 8-pin SOIC Top View CLKA GND XTALIN XTALOUT 1 2 3 4 8 7 6 5 OE/FS VDD CLKC CLKB Cypress Semiconductor Corporation Document #: 38-07139 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY2071A Pin Summary Name CLKA GND XTALIN[1] XTALOUT[1, 2] CLKB CLKC VDD OE / FS Number 1 2 3 4 5 6 7 8 Description Configurable Clock Output Ground Reference Crystal Input or External Reference Clock Input Reference Crystal Feedback Configurable Clock Output Configurable Clock Output Voltage Supply Output Control Pin, either Output Enable or Frequency Select Input (Active-HIGH, internal pull-up resistor to VDD) Notes: 1. For best accuracy, use a parallel-resonant crystal, CL = 17 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal). Functional Description The CY2071A is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives, CD-ROM drives, video CD players, games, set-top boxes, and data/telecommunications. The device offers up to three configurable clock outputs in an 8-pin, 150-mil SOIC package and can operate off either a 3.3V or 5V power supply. The on-chip reference oscillator is designed for 10-MHz to 25-MHz crystals. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. The CY2071A has one PLL and outputs three factory-EPROM configurable clocks: CLKA, CLKB, and CLKC. The output clocks can originate either from the PLL or the reference, or selected dividers thereof. Additionally, pin 8 can be configured to be an Output Enable or a Select input. The CY2071A can replace multiple Metal Can Oscillators (MCO) in a synchronous system, providing cost and board space savings to the manufacturer. Hence, these devices are ideally suited for applications that require multiple, accurate, and stable clocks synthesized from low-cost generators in small packages. A hard-disk drive is an example of such an application. In this case, CLKA drives the PLL in the Read Controller, while CLKB and CLKC drive the MCU and associated sequencers. sheet when specifying them in CyClocks to ensure that you stay within the limits. You can download a copy of CyClocks free on the Cypress Semiconductor website at www.cypress.com. Consider using the CY2081 for applications that require unrelated output frequencies. Consider using the CY2291, CY2292, or CY2907 for applications that require more than three output clocks. Cypress FTG Programmer The Cypress Frequency Timing Generator (FTG) Programmer is a portable programmer designed to custom program our family of EPROM Field Programmable Clock Devices. The FTG programmers connect to a PC serial port and allow users of CyClocks software to quickly and easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ............................................... –0.5V to +7.0V DC Input Voltage ..................................... –0.5V to VDD+0.5V Storage Temperature ................................. –65°C to +150°C Max. Soldering Temperature (10 sec) ..........................260°C Junction Temperature...................................................150°C Static Discharge Voltage............................................ >2000V (per MIL-STD-883, Method 3015) CyClocks™ Software CyClocks is an easy-to-use software application that allows you to configure any one of the EPROM-Programmable Clocks offered by Cypress. You may specify the input frequency, PLL and output frequencies, and different functional options. Please note the output frequency ranges in this data Document #: 38-07139 Rev. *A Page 2 of 8 CY2071A Operating Conditions[3] Parameter VDD VDD TA CL fREF tPU Description Supply Voltage, 5.0V Operation Supply Voltage, 3.3V Operation Commercial Operating Temperature, Ambient Industrial Operating Temperature, Ambient Max. Load Capacitance per Output (5V Operation) Max. Load Capacitance per Output (3.3V Operation) External Reference Crystal External Reference Clock[4, 5] Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 10.0 1.0 0.05 Min. 4.5 3.0 0 –40 Max. 5.5 3.6 70 85 25 15 25.0 30.0 50 Unit V V °C °C pF pF MHz MHz ms Electrical Characteristics, Commercial 5.0V VDD = 5V ±10%, TA = 0°C to +70°C Parameter VOH VOL VIH VIL IIH IIL IOZ IDD Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[6] Voltage[6] LOW-Level Output Input LOW Current Output Leakage Current VDD Supply Current[7] IOH = –4.0 mA IOL = 4.0 mA Except Crystal Pins Except Crystal Pins VIN = VDD – 0.5V VIN = 0.5V Three State Outputs VDD = VDD max. 5V operation, CL = 25 pF 40 2.0 0.8 10 150 250 60 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V µA µA µA mA Input HIGH Current Electrical Characteristics, Commercial 3.3V VDD = 3.3V ±10%, TA = 0°C to +70°C Parameter VOH VOL VIH VIL IIH IIL IOZ IDD Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[6] LOW-Level Output Input LOW Current Output Leakage Current VDD Supply Current[7] Voltage[6] Input HIGH Current IOH = –4.0 mA IOL = 4.0 mA Except Crystal Pins Except Crystal Pins VIN = VDD – 0.5V VIN = 0.5V Three State Outputs VDD = VDD max. 3.3V operation, CL = 15 pF 24 2.0 0.8 10 150 250 40 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V µA µA µA mA Notes: 3. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses. 4. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 5. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock. 6. Xtal inputs have CMOS thresholds. 7. Load = max, typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula: IDD(mA) = VDD*(6.25+(0.055*FREF) + (0.0017*CLOAD*(FCLKA+FCLKB+FCLKC))). CLOAD is specified in pF and F is specified in MHz. Document #: 38-07139 Rev. *A Page 3 of 8 CY2071A Electrical Characteristics, Industrial 5.0V VDD =5.0V ±10%, TA = –40°C to +85°C Parameter VOH VOL VIH VIL IIH IIL IOZ IDD Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[7] [6] Conditions IOH = –4.0 mA IOL = 4.0 mA Except Crystal Pins Except Crystal Pins VIN = VDD – 0.5V VIN = 0.5V Three State Outputs VDD = VDD max. 5V operation, CL = 25 pF Min. 2.4 Typ. Max. 0.4 Unit V V V V µA µA µA mA 2.0 0.8 10 150 250 40 75 LOW-Level Output Voltage[6] Electrical Characteristics, Industrial 3.3V VDD =3.3V ±10%, TA = –40°C to +85°C Parameter VOH VOL VIH VIL IIH IIL IOZ IDD Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[6] Voltage[6] LOW-Level Output Input LOW Current Output Leakage Current VDD Supply Current[7] IOH = –4.0 mA IOL = 4.0 mA Except Crystal Pins Except Crystal Pins VIN = VDD – 0.5V VIN = 0.5V Three State Outputs VDD = VDD max. 3.3V operation, CL = 15 pF 24 2.0 0.8 10 150 250 50 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V µA µA µA mA Input HIGH Current Switching Characteristics, Commercial 5.0V[8] Parameter t1 Name Output Period Description Clock output range 5V operation 25-pF load CY2071A CY2071AF Min. 7.692 [130 MHz] 10 [100 MHz] 0.8 350 250 45% 40% 50% 50% 1.5 1.5 Typ. Max. 2000 [500 kHz] 2000 [500 kHz] 1 500 350 55% 60% 2.5 2.5 0.5 ns ns ns Unit ns ns % ps ps t1A t1B t1C Clock Jitter Clock Jitter Clock Jitter[9] Output Duty Cycle Peak-to-peak period jitter (t1 max. – t1 min.), % of clock period, fOUT ≤ 16 MHz Peak-to-peak period jitter (16 MHz ≤ fOUT ≤ 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Duty fOUT ≤ 60 MHz cycle[10, 11] for outputs, (t2 ÷ t1) Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1), fOUT > 60 MHz t3 t4 t5 Rise Time[9] Fall Time[9] Skew Output clock rise time Output clock fall time Skew delay between any two outputs with identical frequencies (generated by the PLL) Notes: 8. Guaranteed by design, not 100% tested. 9. When the output clock frequency is between 100 MHz and 130 MHz at 5V, the maximum capacitive load for these measurements is 15 pF. 10. Reference Output duty cycle depends on XTALIN duty cycle. 11. Measured at 1.4V. Document #: 38-07139 Rev. *A Page 4 of 8 CY2071A Switching Characteristics, Commercial 3.3V[8] Parameter t1 Name Output Period Description Clock output range 3.3V operation 15-pF load CY2071AS CY2071AF Min. 10 [100 MHz] 12.50 [80 MHz] 0.8 350 250 45% 40% 50% 50% 1.5 1.5 Typ. Max. 2000 [500 kHz] 2000 [500 kHz] 1 500 350 55% 60% 2.5 2.5 0.5 ns ns ns Unit ns ns % ps ps t1A t1B t1C Clock Jitter Clock Jitter Clock Jitter[9] Output Duty Cycle Peak-to-peak period jitter (t1 max. – t1 min.), % of clock period, fOUT ≤ 16 MHz Peak-to-peak period jitter (16 MHz ≤ fOUT ≤ 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Duty cycle fOUT ≤ 60 MHz [10, 11] for outputs, (t2 ÷ t1) Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1), fOUT > 60 MHz t3 t4 t5 Rise Time[9] Fall Time Skew [9] Output clock rise time Output clock fall time Skew delay between any two outputs with identical frequencies (generated by the PLL) Switching Characteristics, Industrial 5.0V[8] Parameter t1 Name Output Period Description Clock output range 5.0V operation 25-pF load CY2071AI CY2071AFI Min. 10 [100 MHz] 11.1 [90 MHz] 0.8 350 250 45% 40% 50% 50% 1.5 1.5 Typ. Max. 2000 [500 kHz] 2000 [500 kHz] 1 500 350 55% 60% 2.5 2.5 0.5 ns ns ns Unit ns ns % ps ps t1A t1B t1C Clock Jitter Clock Jitter Clock Jitter[9] Output Duty Cycle Peak-to-peak period jitter (t1 max. – t1 min.), % of clock period, fOUT ≤ 16 MHz Peak-to-peak period jitter (16 MHz ≤ fOUT ≤ 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Duty cycle[10, 11] for outputs, (t2 ÷ t1) fOUT ≤ 60 MHz Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1), fOUT > 60 MHz t3 t4 t5 Rise time[9] Fall time[9] Skew Output clock rise time Output clock fall time Skew delay between any two outputs with identical frequencies (generated by the PLL) Document #: 38-07139 Rev. *A Page 5 of 8 CY2071A Switching Characteristics, Industrial 3.3V[8] Parameter t1 Name Output Period Description Clock output range 3.3V operation 15-pF load CY2071AI CY2071AFI Min. 12.50 [80 MHz] 15.0 [66.6 MHz] 0.8 350 250 45% 40% 50% 50% 1.5 1.5 Typ. Max. 2000 [500 kHz] 2000 [500 kHz] 1 500 350 55% 60% 2.5 2.5 0.5 ns ns ns Unit ns ns % ps ps t1A t1B t1C Clock Jitter Clock Jitter Clock Jitter[9] Output Duty Cycle Peak-to-peak period jitter (t1 max. – t1 min.), % of clock period, fOUT ≤ 16 MHz Peak-to-peak period jitter (16 MHz ≤ fOUT ≤ 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Duty cycle[10, 11] for outputs, (t2 ÷ t1) fOUT ≤ 60 MHz Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1), fOUT > 60 MHz t3 t4 t5 Rise time[9] Fall time[9] Skew Output clock rise time Output clock fall time Skew delay between any two outputs with identical frequencies (generated by the PLL) Switching Waveforms All Outputs Duty Cycle and Rise/Fall Time t1 t2 OUTPUT 2.4V 0.4V t3 2.4V 0.4V t4 2071A–3 VDD 0V Output-Output Clock Skew OUTPUT OUTPUT t5 2071A–4 Document #: 38-07139 Rev. *A Page 6 of 8 CY2071A Test Circuit VDD 0.1 µF 7 OUTPUTS 2 CLK output CLOAD GND 2071A–5 Ordering Information Ordering Code CY2071ASC-XXX CY2071ASL-XXX CY2071ASI-XXX CY2071AF CY2071AFI CY3670 Package Name S8 S8 S8 S8 S8 Package Type 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC FTG Programmer Operating Range 5.0V, Commercial, Factory Programmable 3.3V, Commercial, Factory Programmable 5V/3.3V, Industrial, Factory Programmable 5V/3.3V, Commercial, Field Programmable 5V/3.3V, Industrial, Field Programmable Custom programming for Field Programmable Clocks Package Characteristics Package 8 Pin SOIC θJA (C/W) 170 θJC (C/W) 35 Transistor Count 5436 Package Diagram 8-Lead (150-Mil) SOIC S8 51-85066-A Document #: 38-07139 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2071A Document Title: CY2071A Single-PLL General-Purpose EPROM Programmable Clock Generator Document Number: 38-07139 REV. ** *A ECN NO. 110248 121827 Issue Date 12/17/01 12/14/02 Orig. of Change SZV RBI Description of Change Change from Spec number: 38-00521 to 38-07139 Power up requirements added to Operating Conditions Information Document #: 38-07139 Rev. *A Page 8 of 8