CY2077
High-Accuracy One-Time Programmable
Single-PLL Clock Generator
High-Accuracy One-Time Programmable Single-PLL Clock Generator
Features
■
Sixteen selectable post-divide options, using either PLL or
reference oscillator/external clock
■
Programmable PWR_DWN or OE pin, with asynchronous or
synchronous modes
■
High-accuracy PLL with 12-bit multiplier and 10-bit divider
■
One-time programmability
■
3.3 V or 5 V operation
■
■
Operating frequency
❐ 390 kHz–133 MHz at 5 V
❐ 390 kHz–100 MHz at 3.3 V
Low jitter outputs typically
❐ 80 ps at 3.3 V/5 V
■
Controlled rise and fall times and output slew rate
■
Available in both commercial and industrial temperature ranges
■
Reference input from either a 10 MHz–30 MHz fundamental
toned crystal or a 1 MHz–75 MHz external clock
■
Factory programmable device options
■
PROM selectable TTL or CMOS duty cycle levels
Functional Description
For a complete list of related documentation, click here.
Logic Block Diagram
XTALIN
or
external clock
Q
10 bits
Phase Detector
XTALOUT[1]
Crystal
Oscillator
PWR_DWN
or OE
Charge
Pump
Configuration
PROM
VCO
P
12 bits
HIGH
ACCURACY
PLL
MUX
/ 1, 2, 4, 8, 16, 32, 64, 128
CLKOUT
Note
1. When using an external clock source, leave XTALOUT floating.
Cypress Semiconductor Corporation
Document Number: 38-07210 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 7, 2017
CY2077
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
PROM Configuration Block ......................................... 4
PLL Output Frequency ................................................ 4
Power Management Features ..................................... 4
Absolute Maximum Ratings ............................................ 5
Operating Conditions ....................................................... 5
Electrical Characteristics ................................................. 6
Output Clock Switching Characteristics
- Commercial ..................................................................... 7
Operating Conditions ....................................................... 8
Electrical Characteristics ................................................. 9
Output Clock Switching Characteristics
- Industrial ....................................................................... 10
Document Number: 38-07210 Rev. *J
Switching Waveforms .................................................... 12
Typical Rise/Fall Time Trends ....................................... 13
Typical Duty Cycle Trends ............................................. 14
Typical Jitter Trends ...................................................... 15
Programming Procedures ............................................. 16
Ordering Information ...................................................... 16
Package Diagrams .......................................................... 17
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 2 of 20
CY2077
Pinouts
Figure 1. 8-pin SOIC pinout (Top View)
VDD
XTALOUT
XTALIN
PD/OE
1
2
3
4
8
7
6
5
CLKOUT
VSS
VSS
VSS
Pin Definitions
8-pin SOIC
Pin Name
Pin
Pin Description
VDD
1
VSS
5, 6, 7
Voltage supply
XD
2
Crystal output (leave this pin floating when external reference is used)
XG
3
Crystal input or external input reference
PWR_DWN / OE
4
One-time programmable power-down or output enable pin. PWR_DWN is active low. OE is active
high. Weak pull-up.
CLKOUT
8
Clock output. Weak pull-down
Ground (all the pins must be grounded)
Document Number: 38-07210 Rev. *J
Page 3 of 20
CY2077
Functional Overview
PLL Output Frequency
CY2077 is an one-time programmable, high-accuracy,
general-purpose, PLL-based design for use in applications such
as modems, disk drives, CD-ROM drives, video CD players,
DVD
players,
games,
set-top
boxes,
and
data/telecommunications.
CY2077 can generate a clock output up to 133 MHz at 5 V or
100 MHz at 3.3 V. It has been designed to give the customer a
very accurate and stable clock frequency with little to zero PPM
error. CY2077 contains a 12-bit feedback counter divider and
10-bit reference counter divider to obtain a very high resolution
to meet the needs of stringent design specifications.
Furthermore, there are eight output divide options of /1, /2, /4, /8,
/16, /32, /64, and /128. The output divider can select between the
PLL and crystal oscillator output/external clock, providing a total
of 16 different options to add more flexibility in designs. TTL or
CMOS duty cycles can be selected.
Power management with the CY2077 is also very flexible. The
user can choose either a PWR_DWN, or an OE feature with
which both have integrated pull up resistors. PWR_DWN and OE
signals can be programmed to have asynchronous and
synchronous timing with respect to the output signal. There is a
weak pull down on the output that pulls CLKOUT LOW when
either the PWR_DWN or OE signal is LOW. This weak pull down
can easily be overridden by another clock signal in designs
where multiple clock signals share a signal path.
Multiple options for output selection, better power distribution
layout, and controlled rise and fall times enable the CY2077 to
be used in applications that require low jitter and accurate
reference frequencies.
PROM Configuration Block
CY2077 contains a high-resolution PLL with 12-bit multiplier and
10-bit divider[2]. The output frequency of the PLL is determined
by the following formula:
2 • (P + 5)
F PLL = --------------------------- • F REF
(Q + 2)
where P is the feedback counter value and Q is the reference
counter value. P and Q are One-Time programmable values.
The calculation of P and Q values for a given PLL output
frequency is handled by the CyberClocks software. Refer to
Programming Procedures on page 16 for details.
Power Management Features
PWR_DWN and OE options are configurable by PROM
programming for the CY2077. In PWR_DWN mode, all active
circuits are powered down when the control pin is set LOW.
When the control pin is set back HIGH, both the PLL and
oscillator circuit must relock. In the case of OE, the output is
three-stated and weakly pulled down when the control pin is set
LOW. The oscillator and PLL are still active in this state, which
leads to a quick clock output return when the control pin is set
back HIGH.
Additionally, PWR_DWN and OE can be configured to occur
asynchronously or synchronously with respect to CLKOUT. In
asynchronous mode, PWR_DWN or OE disables CLKOUT
immediately (allowing for logic delays), without respect to the
current state of CLKOUT. Synchronous mode prevents output
glitches by waiting for the next falling edge of CLKOUT after
PWR_DWN, or OE becomes asserted. In either asynchronous
or synchronous setting, the output is always enabled
synchronously by waiting for the next falling edge of CLKOUT.
Table 1. PROM Adjustable Features
PROM Adjustable Features
Adjust
Freq.
Feedback counter value (P)
Reference counter value (Q)
Output divider selection
Duty cycle levels (TTL or CMOS)
Power management mode (OE or PWR_DWN)
Power management timing (synchronous or asynchronous)
Table 2. Device Functionality: Output Frequencies
Symbol
Fo
Description
Output frequency
Min
Max
Unit
VDD = 4.5 V–5.5 V
Condition
0.39
133
MHz
VDD = 3.0 V–3.6 V
0.39
100
MHz
Note
2. When using CyClocks, note that the PLL frequency range is from 50 MHz to 250 MHz for 5 V VDD supply, and 50 MHz to 180 MHz for 3 V VDD supply. The output
frequency is determined by the selected output divider.
Document Number: 38-07210 Rev. *J
Page 4 of 20
CY2077
Absolute Maximum Ratings
Input voltage ........................................ –0.5 V to VDD +0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage ................................................ –0.5 to +7.0 V
Storage temperature (non-condensing) ..... –55°C to +150°C
Junction temperature ................................................. 150°C
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2000 V
Operating Conditions
For Commercial Temperature Device
Parameter
VDD
Description
Supply voltage
TA
Operating temperature, ambient
CTTL
Max. capacitive load on outputs for TTL levels
VDD = 4.5 V–5.5 V, output frequency = 1 MHz–40 MHz
CCMOS
Min
Max
Unit
3.0
5.5
V
0
+70
°C
–
50
pF
VDD = 4.5 V–5.5 V, output frequency = 40 MHz–125 MHz
–
25
pF
VDD = 4.5 V–5.5 V, output frequency = 125 MHz–133 MHz
–
15
pF
Max. capacitive load on outputs for CMOS levels
VDD = 4.5 V–5.5 V, output frequency = 1 MHz–40 MHz
–
50
pF
VDD = 4.5 V–5.5 V, output frequency = 40 MHz–125 MHz
–
25
pF
VDD = 4.5 V–5.5 V, output frequency = 125 MHz–133 MHz
–
15
pF
VDD = 3.0 V–3.6 V, output frequency = 1 MHz–40 MHz
–
30
pF
VDD = 3.0 V–3.6 V, output frequency = 40 MHz–100 MHz
–
15
pF
XREF
Reference frequency, input crystal with Cload = 10 pF
10
30
MHz
Reference frequency, external clock source
1
75
MHz
tPU
Power-up time for all VDD’s to reach minimum specified voltage (power ramps must
be monotonic)
0.05
50
ms
Document Number: 38-07210 Rev. *J
Page 5 of 20
CY2077
Electrical Characteristics
TA = 0 °C to +70 °C
Parameter
VIL
Description
Low-level input voltage
VIH
High-level input voltage
VOL
Low-level output voltage
Min
Typ
Max
Unit
VDD = 4.5 V–5.5 V
Test Conditions
–
–
0.8
V
VDD = 3.0 V–3.6 V
–
–
0.2 × VDD
V
VDD = 4.5 V–5.5 V
2.0
–
–
V
VDD = 3.0 V–3.6 V
0.7 × VDD
–
–
V
VDD = 4.5 V–5.5 V, IOL= 16 mA
–
–
0.4
V
VDD = 3.0 V–3.6 V, IOL= 8 mA
–
–
0.4
V
VDD – 0.4
–
–
V
VOHCMOS
High-level output voltage CMOS VDD = 4.5 V–5.5 V, IOH= –16 mA
levels
VDD = 3.0 V–3.6 V, IOH= –8 mA
VOHTTL
High-level output voltage TTL
levels
VDD = 4.5 V–5.5 V, IOH= –8 mA
VDD – 0.4
–
–
V
2.4
–
–
V
IIL
Input low current
VIN = 0 V
–
–
10
μA
IIH
Input high current
VIN = VDD
–
–
5
μA
IDD
Power supply current Unloaded
VDD = 4.5 V–5.5 V,
output frequency < 133 MHz
–
–
45
mA
VDD = 3.0 V–3.6 V,
output frequency < 100 MHz
–
–
25
mA
VDD = 4.5 V–5.5 V
–
25
100
μA
VDD = 3.0 V–3.6 V
–
10
50
μA
VDD = 4.5 V–5.5 V, VIN = 0 V
1.1
3.0
8.0
MΩ
VDD = 4.5 V–5.5 V, VIN = 0.7 × VDD
50
100
200
kΩ
VDD = 5.0 V
–
20
–
μA
IDDS[3]
RUP
Stand-by current (PD = 0)
Input pull-up resistor
IOE_CLKOUT CLKOUT pull-down current
Note
3. If external reference is used, it is required to stop the reference (set reference to LOW) during power-down.
Document Number: 38-07210 Rev. *J
Page 6 of 20
CY2077
Output Clock Switching Characteristics - Commercial
Over the Operating Range [4]
Parameter
t1w
t1x
t1y
t2
t3
Description
Test Conditions
Min
Typ
Max
Unit
Output duty cycle at 1.4 V,
VDD = 4.5 V–5.5 V,
t1w = t1A ÷ t1B
1 MHz–40 MHz, CL < 50 pF
45
–
55
%
40 MHz–125 MHz, CL < 25 pF
45
–
55
%
125 MHz–133 MHz, CL < 15 pF
45
–
55
%
Output duty cycle at VDD/2,
VDD = 4.5 V–5.5 V,
t1x = t1A ÷ t1B
1 MHz–40 MHz, CL < 50 pF
45
–
55
%
40 MHz–125 MHz, CL < 25 pF
45
–
55
%
125 MHz–133 MHz, CL < 15 pF
45
–
55
%
Output duty cycle at VDD/2,
VDD = 3.0 V–3.6 V,
t1y = t1A ÷ t1B
1 MHz–40 MHz, CL < 30 pF
45
–
55
%
40 MHz–100 MHz, CL < 15 pF
40
–
60
%
Output clock rise time
Between 0.8 V–2.0 V,
VDD = 4.5 V–5.5 V, CL = 50 pF
–
–
1.8
ns
Between 0.8 V–2.0 V,
VDD = 4.5 V–5.5 V, CL = 25 pF
–
–
1.2
ns
Between 0.8 V–2.0 V,
VDD = 4.5 V–5.5 V, CL = 15 pF
–
–
0.9
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD= 4.5 V–5.5 V, CL = 50 pF
–
–
3.4
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD= 3.0 V–3.6 V, CL = 30 pF
–
–
4.0
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD= 3.0 V–3.6 V, CL = 15 pF
–
–
2.4
ns
Between 0.8 V –2.0 V,
VDD = 4.5 V–5.5 V, CL = 50 pF
–
–
1.8
ns
Between 0.8 V – 2.0 V,
VDD = 4.5 V–5.5 V, CL = 25 pF
–
–
1.2
ns
Between 0.8 V–2.0 V,
VDD = 4.5 V–5.5 V, CL = 15 pF
–
–
0.9
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD = 4.5 V–5.5 V, CL = 50 pF
–
–
3.4
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD = 3.0 V–3.6 V, CL = 30 pF
–
–
4.0
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD = 3.0 V–3.6 V, CL = 15 pF
–
–
2.4
ns
Output clock fall time
t4
Startup time out of power-down
PWR_DWN pin LOW to HIGH[5]
–
1
2
ms
t5a
Power-down delay time
(synchronous setting)
PWR_DWN pin LOW to output LOW
(T = period of output CLK)
–
T/2
T + 10
ns
t5b
Power-down delay time
(asynchronous setting)
PWR_DWN pin LOW to output LOW
–
10
15
ns
t6
Power-up time
From power-on [5]
–
1
2
ms
Notes
4. Not all parameters measured in production testing.
5. Oscillator start time can not be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 Ω.
Document Number: 38-07210 Rev. *J
Page 7 of 20
CY2077
Output Clock Switching Characteristics - Commercial (continued)
Over the Operating Range [4]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
t7a
Output disable time
(synchronous setting)
OE pin LOW to output high-Z
(T = period of output CLK)
–
T/2
T + 10
ns
t7b
Output disable time
(asynchronous setting)
OE pin LOW to output high-Z
–
10
15
ns
t8
Output enable time
(always synchronous enable)
OE pin LOW to HIGH
(T = period of output CLK)
–
T
(1.5 × T) +
25
ns
t9
Peak-to-peak period jitter
VDD = 3.0 V–3.6 V, 4.5 V–5.5 V,
Fo > 33 MHz, VCO > 100 MHz
–
80
150
ps
VDD = 3.0 V–5.5 V, Fo < 33 MHz
–
0.3%
1%
% of FO
Operating Conditions
For Industrial Temperature Device
Parameter
Description
Min
Max
Unit
VDD
Supply voltage
3.0
5.5
V
TA
Operating temperature, ambient
–40
+85
°C
CTTL
Max. capacitive load on outputs for TTL levels
VDD = 4.5 V–5.5 V, output frequency = 1 MHz–40 MHz
–
35
pF
VDD = 4.5 V–5.5 V, output frequency = 40 MHz–125 MHz
–
15
pF
VDD = 4.5 V–5.5 V, output frequency = 125 MHz–133 MHz
–
10
pF
–
35
pF
VDD = 4.5 V–5.5 V, output frequency = 40 MHz–125 MHz
–
15
pF
VDD = 4.5 V–5.5 V, output frequency = 125 MHz–133 MHz
–
10
pF
CCMOS
XREF
tPU
Max. capacitive load on outputs for CMOS levels
VDD = 4.5 V–5.5 V, output frequency = 1 MHz–40 MHz
VDD = 3.0 V–3.6 V, output frequency = 1 MHz–40 MHz
–
20
pF
VDD = 3.0 V–3.6 V, output frequency = 40 MHz–100 MHz
–
10
pF
Reference frequency, input crystal with Cload = 10 pF
10
30
MHz
Reference frequency, external clock source
1
75
MHz
0.05
50
ms
Power-up time for all VDD’s to reach minimum specified voltage
(power ramps must be monotonic)
Document Number: 38-07210 Rev. *J
Page 8 of 20
CY2077
Electrical Characteristics
TA = –40 °C to +85 °C
Parameter
VIL
Description
Low-level input voltage
VIH
High-level input voltage
VOL
Low-level output voltage
Min
Typ
Max
Unit
VDD = 4.5 V–5.5 V
Test Conditions
–
–
0.8
V
VDD = 3.0 V–3.6 V
–
–
0.2 × VDD
V
VDD = 4.5 V–5.5 V
2.0
–
–
V
VDD = 3.0 V–3.6 V
0.7 × VDD
–
–
V
VDD = 4.5 V–5.5 V, IOL= 16 mA
–
–
0.4
V
VDD = 3.0 V–3.6 V, IOL= 8 mA
–
–
0.4
V
–
–
V
VOHCMOS
High-level output voltage,
CMOS levels
VDD = 4.5 V–5.5 V, IOH= –16 mA
VDD – 0.4
VDD = 3.0 V–3.6 V, IOH= –8 mA
VDD – 0.4
–
–
V
VOHTTL
High-level output voltage,
TTL levels
VDD = 4.5 V–5.5 V, IOH= –8 mA
2.4
–
–
V
IIL
Input low current
VIN = 0 V
–
–
10
μA
IIH
Input high current
VIN = VDD
–
–
5
μA
IDD
Power supply current, Unloaded VDD = 4.5 V–5.5 V,
output frequency < 133 MHz
–
–
45
mA
VDD = 3.0 V–3.6 V,
output frequency < 100 MHz
–
–
25
mA
VDD = 4.5 V–5.5 V
–
25
100
μA
VDD = 3.0 V–3.6 V
–
10
50
VDD = 4.5 V–5.5 V, VIN = 0 V
1.1
3.0
8.0
MΩ
VDD = 4.5 V–5.5 V, VIN = 0.7 × VDD
50
100
200
kΩ
VDD = 5.0 V
–
20
–
μA
IDDS[6]
RUP
Stand-by current (PD = 0)
Input pull-up resistor
IOE_CLKOUT CLKOUT pull-down current
Note
6. If external reference is used, it is required to stop the reference (set reference to LOW) during power-down.
Document Number: 38-07210 Rev. *J
Page 9 of 20
CY2077
Output Clock Switching Characteristics - Industrial
Over the Operating Range [7]
Parameter
t1w
t1x
t1y
t2
t3
Description
Test Conditions
Min
Typ
Max
Unit
Output duty cycle at 1.4 V,
VDD = 4.5 V–5.5 V,
t1w = t1A ÷ t1B
1 MHz–40 MHz, CL < 35 pF
45
–
55
%
40 MHz–125 MHz, CL < 15 pF
45
–
55
%
125 MHz–133 MHz, CL < 10 pF
45
–
55
%
Output duty cycle at VDD/2,
VDD = 4.5 V–5.5 V,
t1x = t1A ÷ t1B
1 MHz–40 MHz, CL < 35 pF
45
–
55
%
40 MHz–125 MHz, CL < 15 pF
45
–
55
%
125 MHz–133 MHz, CL < 10 pF
45
–
55
%
Output duty cycle at VDD/2,
VDD = 3.0 V–3.6 V,
t1y = t1A ÷ t1B
1 MHz–40 MHz, CL < 20 pF
45
–
55
%
40 MHz–100 MHz, CL < 10 pF
40
–
60
%
Output clock rise time
Between 0.8 V–2.0 V,
VDD = 4.5 V–5.5 V, CL = 35 pF
–
–
1.8
ns
Between 0.8 V– 2.0 V,
VDD = 4.5 V–5.5 V, CL = 15 pF
–
–
1.2
ns
Between 0.8 V–2.0 V,
VDD = 4.5 V–5.5 V, CL = 10 pF
–
–
0.9
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD = 4.5 V–5.5 V, CL = 35 pF
–
–
3.4
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD = 3.0 V–3.6 V, CL = 20 pF
–
–
4.0
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD = 3.0 V–3.6 V, CL = 10 pF
–
–
2.4
ns
Between 0.8 V–2.0 V,
VDD = 4.5 V–5.5 V, CL = 35 pF
–
–
1.8
ns
Between 0.8 V–2.0 V,
VDD = 4.5 V–5.5 V, CL = 15 pF
–
–
1.2
ns
Between 0.8 V–2.0 V,
VDD = 4.5 V–5.5 V, CL = 10 pF
–
–
0.9
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD= 4.5 V–5.5 V, CL = 35 pF
–
–
3.4
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD = 3.0 V–3.6 V, CL = 20 pF
–
–
4.0
ns
Between 0.2 × VDD to 0.8 × VDD,
VDD = 3.0 V–3.6 V, CL = 10 pF
–
–
2.4
ns
Output clock fall time
t4
Startup time out of Power-down
PWR_DWN pin LOW to HIGH[8]
–
1
2
ms
t5a
Power-down delay time
(synchronous setting)
PWR_DWN pin LOW to output LOW
(T = period of output clk)
–
T/2
T + 10
ns
t5b
Power-down delay time
(asynchronous setting)
PWR_DWN pin LOW to output LOW
–
10
15
ns
t6
Power-up time
From power on[8]
–
1
2
ms
Notes
7. Not all parameters measured in production testing.
8. Oscillator start time can not be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70Ω.
Document Number: 38-07210 Rev. *J
Page 10 of 20
CY2077
Output Clock Switching Characteristics - Industrial (continued)
Over the Operating Range [7]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
t7a
Output Disable time
(synchronous setting)
OE pin LOW to output high-Z
(T = period of output clk)
–
T/2
T + 10
ns
t7b
Output Disable time
(asynchronous setting)
OE pin LOW to output high-Z
–
10
15
ns
t8
Output Enable time
(always synchronous enable)
OE pin LOW to HIGH
(T = period of output clk)
–
T
(1.5 × T) +
25
ns
t9
Peak-to-peak period jitter
VDD = 3.0 V–3.6 V, 4.5 V–5.5 V,
Fo > 33 MHz, VCO > 100 MHz
–
80
150
ps
VDD = 3.0 V – 5.5 V, Fo < 33 MHz
–
0.3%
1%
% of FO
Document Number: 38-07210 Rev. *J
Page 11 of 20
CY2077
Switching Waveforms
Figure 2. Duty Cycle Timing (t1w, t1x, t1y)
t1B
t1A
OUTPUT
Figure 3. Output Rise/Fall Time
VDD
OUTPUT
0V
t2
t3
Figure 4. Power-down Timing (synchronous and asynchronous modes)
POWER
DOWN
VDD
VIH
VIL
t4
0V
CLKOUT
(synchronous[9])
T
t5a
1/f
CLKOUT
(asynchronous[10])
1/f
t5b
Figure 5. Power-up Timing
VDD
POWER
UP
VDD – 10%
t6
0V
min 30 μs
max 30 ms
CLKOUT
1/f
Figure 6. Output Enable Timing (synchronous and asynchronous modes)
OUTPUT
ENABLE
VDD
VIH
VIL
0V
T
CLKOUT
High Impedance
(synchronous[9])
t7a
CLKOUT
t8
High Impedance
(asynchronous[10])
t7b
t8
Notes
9. In synchronous mode, the power-down or output three-state is not initiated until the next falling edge of the output clock.
10. In asynchronous mode, the power-down or output three-state occurs within 25 ns regardless of position in the output clock cycle.
Document Number: 38-07210 Rev. *J
Page 12 of 20
CY2077
Typical Rise/Fall Time Trends
For CY2077 [11]
Figure 7. Rise/Fall Time vs. VDD over Temperatures
Rise Time vs. VDD -- CMOS duty Cycle
Cload = 15pF
Rise Time (ns)
2.00
1.80
-40C
25C
85C
1.60
1.40
1.20
Fall Time (ns)
Fall Time vs. VDD -- CMOS duty Cycle
Cload = 15pF
1.00
2.7
3.0
3.3
3.6
2.00
1.80
1.60
1.40
1.20
1.00
-40C
25C
85C
2.7
3.9
3.0
0.70
0.60
0.50
0.40
0.30
0.20
-40C
25C
85C
5.0
3.9
Fall Time vs. VDD -- TTL duty Cycle
Cload = 15pF
5.5
Fall Time (ns)
Rise Time (ns)
Rise Time vs. VDD -- TTL duty Cycle
Cload = 15pF
4.5
3.6
VDD (V)
VDD (V)
4.0
3.3
0.70
0.60
0.50
0.40
0.30
0.20
6.0
-40C
25C
85C
4.0
4.5
VDD (V)
5.0
5.5
6.0
VDD (V)
Figure 8. Rise/Fall Time vs. Output Loads over Temperatures
Fall Time vs. CLoad over Temperature
VDD = 3.3v, CMOS output
2.50
-40C
25C
85C
2.00
1.50
1.00
10
15
20
25
Cload (pF)
30
35
Fall Time (ns)
Rise Time (ns)
Rise Time vs. CLoad over Temperature
VDD = 3.3v, CMOS output
2.00
-40C
25C
85C
1.50
1.00
10
15
20
25
30
35
Cload (pF)
Note
11. Rise/Fall time for CMOS output is measured between 1.2 VDD and 0.8 × VDD. Rise/Fall time for TTL output is measured between 0.8 V and 2.0 V.
Document Number: 38-07210 Rev. *J
Page 13 of 20
CY2077
Typical Duty Cycle Trends
For CY2077 [12]
Figure 9. Duty Cycle vs. VDD over Temperatures
55.00
53.00
51.00
49.00
47.00
45.00
Duty Cycle vs. VDD over Temperature
(CMOS Duty Cycle Ouput, Fout=50MHz,
Cload=50pF)
-40C
25C
85C
4.0
4.5
5.0
5.5
Duty Cycle (%)
Duty Cycle (%)
Duty Cycle vs. VDD over Temperature
(TTL Duty Cycle Output, Fout=50MHz, Cload =
50pF)
55.00
53.00
51.00
49.00
47.00
45.00
6.0
-40C
25C
85C
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (v)
Figure 10. Duty Cycle vs. Output Load
Duty Cycle (%)
Duty Cycle vs. CLoad with Various VDD
(Fout = 50MHz, Temp = 25C)
55.00
53.00
51.00
49.00
47.00
45.00
VDD=4.5V
VDD=5.0V
VDD=5.5V
10 15 20 25 30 35 40 45 50 55
Cload (pF)
Output DC (%)
Figure 11. Duty Cycle vs. Output Frequency over Temperatures
Output Duty Cycle vs. Fout over Temperature
(Vdd = 5V, Cload = 15pF)
55.00%
54.00%
53.00%
25C
52.00%
85C
51.00%
-40C
50.00%
20 30 40 50 60 70 80
Output Frequency (MHz)
Note
12. Duty cycle is measured at 1.4 V for TTL output and 0.5 × VDD for CMOS output.
Document Number: 38-07210 Rev. *J
Page 14 of 20
CY2077
Typical Jitter Trends
For CY2077
Figure 12. Period Jitter (pk-pk) vs. VDD over Temperatures
Period Jitter (pk-pk) vs. VDD over Temperatures
(Fout=40MHz, Cload = 30pF)
Period JItter (ps)
100
80
60
-40C
40
25C
20
85C
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
Figure 13. Period Jitter (pk-pk) vs. Output Frequency over Temperatures
Output Jitter (pk-pk) vs. Output Frequency
(VDD=3.3V, Cload=15pf, CMOS output)
100
Jitter (ps)
80
25C
60
-40C
40
85C
20
0
0
20
40
60
80
100
120
140
Output frequency (MHz)
Output Jitter(pk-pk) vs. Output Frequency
(VDD=5.0V, Cload=15pf, CMOS output)
100
Jitter (ps)
80
25C
60
-40C
40
85C
20
0
0
20
40
60
80
100
120
140
Output frequency (MHz)
Document Number: 38-07210 Rev. *J
Page 15 of 20
CY2077
Programming Procedures
Currently the CY2077 is available only as a field-programmable
device, as indicated by an “F” in the ordering code.
Devices may be programmed using the CY3672-USB
programmer, or through programmers available from third party
programmer manufacturers such as Hi-Lo Systems and BP
Micro. Programming services are also available from third
parties, including some Cypress distribution partners.
To generate a JEDEC format programming file, customers must
use CyClocks software. This software automatically calculates
the output frequencies that can be generated by CY2077
devices. The CyClocks software is a subset of the larger
software tool CyberClocks, which is available free of charge from
the Cypress web site (http://www.cypress.com). CyberClocks is
installed on a PC and must not be confused with the web-based
application CyberClocks Online.
For high volume designs, factory programming of
customer-specific configurations is available on other 8-pin
devices such as the CY22180, CY22801 and CY22381. Factory
programming is no longer offered for new designs using the
CY2077.
Ordering Information
Ordering Code [14]
Package Name
Package Type
Operating Temperature Range Operating Voltage
Pb-Free
CY2077FSXC
S8
8-pin SOIC
Commercial (T = 0 °C to 70 °C)
3.3 V or 5 V
CY2077FSXCT
S8
8-pin SOIC –Tape and Reel
Commercial (T = 0 °C to 70 °C)
3.3 V or 5 V
CY2077FZZ
Z8
8-pin TSSOP
Commercial (T = 0 °C to 70 °C)
3.3 V or 5 V
CY2077FZXI
Z8
8-pin TSSOP
Industrial (T = –40 °C to 85 °C)
3.3 V or 5 V
CY2077FZXIT
Z8
8-pin TSSOP –Tape and Reel Industrial (T = –40 °C to 85 °C)
3.3 V or 5 V
Programmer
CY3672-USB
Programming Kit
CY3696
Socket adapter board, for programming CY2077FS (SOIC Package)
CY3697
Socket adapter board, for programming CY2077FZ (TSSOP Package)
Table 3. Obsolete or Not For New Designs
Original Device
Ordering Code
[13, 14]
Description
Replacement Device
Ordering Code
CY2077SC-xxx
none
CY2077SC-xxxT
none
CY2077SI-xxx
none
CY2077SI-xxxT
none
CY2077SXC-xxx
none
CY2077SXC-xxxT
none
CY2077ZC-xxx
none
CY2077ZC-xxxT
none
CY2077ZI-xxx
none
CY2077ZI-xxxT
none
CY2077ZXC-xxx
none
CY2077ZXC-xxxT
Description
none
CY2077FSI
SOIC, Industrial (T = –40 °C to 85 °C)
CY2077FSXC
Pb-free SOIC, Commercial
CY2077FZ
TSSOP, Commercial (T = 0 °C to 70 °C)
CY2077FZZ
Pb-free TSSOP, Commercial
CY2077FZI
TSSOP, Industrial (T = –40 °C to 85 °C)
CY2077FZXI
Pb-free TSSOP, Industrial
Notes
13. The CY2077SC-xxx(T), CY2077SI-xxx(T), CY2077SXC-xxx(T), CY2077ZC-xxx(T), CY2077ZI-xxx(T) andCY2077ZXC-xxx(T), are factory programmed configurations.
Factory programming is available for high-volume design opportunities. For more details, contact your local Cypress FAE or Cypress Sales Representative.
14. The CY2077F are field programmable. For more details, contact your local Cypress FAE or Cypress Sales Representative.
Document Number: 38-07210 Rev. *J
Page 16 of 20
CY2077
Package Diagrams
Figure 14. 8-pin SOIC (150 Mils) Package Outline, 51-85066
51-85066 *H
Document Number: 38-07210 Rev. *J
Page 17 of 20
CY2077
Package Diagrams (continued)
Figure 15. 8-pin TSSOP (4.40 mm Body) Package Outline, 51-85093
51-85093 *E
Document Number: 38-07210 Rev. *J
Page 18 of 20
CY2077
Document History Page
Document Title: CY2077, High-Accuracy One-Time Programmable Single-PLL Clock Generator
Document Number: 38-07210
Revision
ECN
Orig. of
Change
Sumbission
Date
**
111727
DSG
02/07/02
Convert from Spec number: 38-01009 to 38-07210
*A
114938
CKN
07/24/02
Added table and notes to page 11
*B
121843
RBI
12/14/02
Power up requirements added to Operating Conditions Information
*C
2104546
PYG / KVM
/ AESA
See ECN
Updated Ordering Information table
Replaced the “Custom Configuration Request Procedure” section with
“Programming Procedures”
Updated package diagrams
*D
2631183
KVM /
AESA
01/06/09
CY2077FS removed from the active part number table.
Added CY2077FZXI and CY2077FZXIT to the Ordering Information table.
Corrected wording on p. 2 about when the weak output pull-down is active.
Added to Table 1 to indicate that PWR_DWN is active low and OE is active
high.
Updated to new template.
*E
2905892
CXQ
04/07/10
Updated Ordering Information:
Updated Table 3:
Removed inactive part CY2077FS.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *C to *D.
spec 51-85093 – Changed revision from *A to *B.
*F
3388539
MNSB /
PURU
09/29/11
Updated Programming Procedures:
Replaced “CY3670” with “CY3672-USB”.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *D to *E.
spec 51-85093 – Changed revision from *B to *C.
*G
3514611
PURU
02/01/2012
Removed Benefits.
Updated Package Diagrams:
spec 51-85093 – Changed revision from *C to *D.
*H
4575273
PURU
11/20/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *E to *F.
spec 51-85093 – Changed revision from *D to *E.
*I
4694396
TAVA
03/20/2015
Updated Package Diagrams:
spec 51-85066 – Changed revision from *F to *G.
Updated to new template.
*J
5766130
PSR
06/07/2017
Updated Document Title to read as “CY2077, High-Accuracy One-Time
Programmable Single-PLL Clock Generator”.
Replaced “EPROM Programmable” with “One-time Programmable” in all
instances across the document.
Replaced “EPROM” with “PROM” in all instances across the document.
Updated Logic Block Diagram.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *G to *H.
Updated to new template.
Document Number: 38-07210 Rev. *J
Description of Change
Page 19 of 20
CY2077
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2002–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-07210 Rev. *J
Revised June 7, 2017
Page 20 of 20
PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
工商网监
湘ICP备2023018690号
