CY2077ZXC-XXXT

CY2077 High-accuracy EPROM Programmable Single-PLL Clock Generator Features ■ ■ ■ ■ Benefits ■ ■ ■ ■ ■ High-accuracy PLL with 12-bit multiplier and 10-bit divider EPROM programmability 3.3V or 5V operation Operating frequency ❐ 390 kHz–133 MHz at 5V ❐ 390 kHz–100 MHz at 3.3V Reference input from either a 10–30 MHz fundamental toned crystal or a 1–75 MHz external clock EPROM selectable TTL or CMOS duty cycle levels Sixteen selectable post-divide options, using either PLL or reference oscillator/external clock Programmable PWR_DWN or OE pin, with asynchronous or synchronous modes Low jitter outputs typically ❐ 80 ps at 3.3V/5V Controlled rise and fall times and output slew rate Available in both commercial and industrial temperature ranges Factory programmable device options Enables synthesis of highly accurate and stable output clock frequencies with zero PPM Enables quick turnaround of custom frequencies Supports industry standard design platforms Services most PC, networking, and consumer applications Lowers cost of oscillator as PLL can be programmed to a high frequency using either a low-frequency, low-cost crystal, or an existing system clock Duty cycle centered at 1.5V or VDD/2 Provides flexibility to service most TTL or CMOS applications Provides flexibility in output configurations and testing Enables low-power operation or output enable function and flexibility for system applications, through selectable instantaneous or synchronous change in outputs Suitable for most PC, consumer, and networking applications Has lower EMI than oscillators Suitable to fit most applications Easy customization and fast turnaround ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram PWR_DWN or OE Phase Detector Crystal Oscillator Charge Pump Configuration EPROM XTALOUT[1] XTALIN or external clock Q 10 bits VCO P 12 bits HIGH ACCURACY PLL MUX / 1, 2, 4, 8, 16, 32, 64, 128 Note 1. When using an external clock source, leave XTALOUT floating. CLKOUT Cypress Semiconductor Corporation Document Number: 38-07210 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 15, 2008 [+] Feedback CY2077 Pin Configuration Figure 1. Pin Diagram - 8 Pin Top View VDD XTALOUT XTALIN PD/OE Table 1. Pin Definition - 8 Pin Pin Name VDD VSS XD XG PWR_DWN / OE CLKOUT Pin # 1 5,6,7 2 3 4 8 Pin Description Voltage supply Ground (all the pins must be grounded) Crystal output (leave this pin floating when external reference is used) Crystal input or external input reference EPROM programmable power down or output enable pin. Weak pull up Clock output. Weak pull down 1 2 3 4 8 7 6 5 CLKOUT VSS VSS VSS Functional Description CY2077 is an EPROM-programmable, high-accuracy, general-purpose, PLL-based design for use in applications such as modems, disk drives, CD-ROM drives, video CD players, DVD players, games, set-top boxes, and data/telecommunications. CY2077 can generate a clock output up to 133 MHz at 5V or 100 MHz at 3.3V. It has been designed to give the customer a very accurate and stable clock frequency with little to zero PPM error. CY2077 contains a 12-bit feedback counter divider and 10-bit reference counter divider to obtain a very high resolution to meet the needs of stringent design specifications. Furthermore, there are eight output divide options of /1, /2, /4, /8, /16, /32, /64, and /128. The output divider can select between the PLL and crystal oscillator output/external clock, providing a total of 16 different options to add more flexibility in designs. TTL or CMOS duty cycles can be selected. Power management with the CY2077 is also very flexible. The user can choose either a PWR_DWN, or an OE feature with which both have integrated pull up resistors. PWR_DWN and OE signals can be programmed to have asynchronous and synchronous timing with respect to the output signal. There is a weak pull down on the output that pulls CLKOUT LOW when either the PWR_DWN or OE signal is active. This weak pull down can easily be overridden by another clock signal in designs where multiple clock signals share a signal path. Multiple options for output selection, better power distribution layout, and controlled rise and fall times enable the CY2077 to be used in applications that require low jitter and accurate reference frequencies. EPROM Configuration Block Table 2. EPROM Adjustable Features EPROM Adjustable Features Feedback counter value (P) Reference counter value (Q) Output divider selection Duty cycle levels (TTL or CMOS) Power management mode (OE or PWR_DWN) Power management timing (synchronous or asynchronous) Adjust Freq. PLL Output Frequency CY2077 contains a high-resolution PLL with 12-bit multiplier and 10-bit divider.[2] The output frequency of the PLL is determined by the following formula: 2 • (P + 5) F PLL = --------------------------- • F REF (Q + 2) where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values. The calculation of P and Q values for a given PLL output frequency is handled by the CyberClocks™ software. Refer to ““Programming Procedures” on page 12” for details. Note 2. When using CyClocks, note that the PLL frequency range is from 50 MHz to 250 MHz for 5V VDD supply, and 50 MHz to 180 MHz for 3V VDD supply. The output frequency is determined by the selected output divider. Document Number: 38-07210 Rev. *C Page 2 of 14 [+] Feedback CY2077 Power Management Features PWR_DWN and OE options are configurable by EPROM programming for the CY2077. In PWR_DWN mode, all active circuits are powered down when the control pin is set LOW. When the control pin is set back HIGH, both the PLL and oscillator circuit must relock. In the case of OE, the output is three-stated and weakly pulled down when the control pin is set LOW. The oscillator and PLL are still active in this state, which leads to a quick clock output return when the control pin is set back HIGH. Table 3. Device Functionality: Output Frequencies Symbol Fo Description Output frequency Condition VDD = 4.5–5.5V VDD = 3.0–3.6V Min 0.39 0.39 Max 133 100 Unit MHz MHz Additionally, PWR_DWN and OE can be configured to occur asynchronously or synchronously with respect to CLKOUT. In asynchronous mode, PWR_DWN or OE disables CLKOUT immediately (allowing for logic delays), without respect to the current state of CLKOUT. Synchronous mode prevents output glitches by waiting for the next falling edge of CLKOUT after PWR_DWN, or OE becomes asserted. In either asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of CLKOUT. Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply voltage .................................................. –0.5 to +7.0V Input voltage ........................................... –0.5V to VDD +0.5V Storage temperature (non-condensing)...... –55°C to +150°C Junction temperature.................................................. 150°C Static discharge voltage........................................... > 2000V (per MIL-STD-883, method 3015) Operating Conditions for Commercial Temperature Device Parameter Description VDD Supply voltage Operating temperature, ambient TA Max. capacitive load on outputs for TTL levels CTTL VDD = 4.5 – 5.5V, output frequency = 1 – 40 MHz VDD = 4.5 – 5.5V, output frequency = 40 – 125 MHz VDD = 4.5 – 5.5V, output frequency = 125 – 133 MHz CCMOS Max. capacitive load on outputs for CMOS levels VDD = 4.5 – 5.5V, output frequency = 1 – 40 MHz VDD = 4.5 – 5.5V, output frequency = 40 – 125 MHz VDD = 4.5 – 5.5V, output frequency = 125 – 133 MHz VDD = 3.0 – 3.6V, output frequency = 1 – 40 MHz VDD = 3.0 – 3.6V, output frequency = 40 – 100 MHz Reference frequency, input crystal with Cload = 10 pF Reference frequency, external clock source Power up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Min 3.0 0 Max 5.5 +70 50 25 15 Unit V °C pF pF pF XREF tPU 10 1 0.05 50 25 15 30 15 30 75 50 pF pF pF pF pF MHz MHz ms Document Number: 38-07210 Rev. *C Page 3 of 14 [+] Feedback CY2077 Electrical Characteristics TA = 0°C to +70°C Parameter Description VIL VIH VOL VOHCMOS VOHTTL IIL IIH IDD IDDS[3] RUP Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage CMOS levels High-level output voltage TTL levels Input low current Input high current Power supply current Unloaded Stand-by current (PD = 0) Input pull up resistor Test Conditions VDD = 4.5 – 5.5V VDD = 3.0 – 3.6V VDD = 4.5 – 5.5V VDD = 3.0 – 3.6V VDD = 4.5 – 5.5V, IOL= 16 mA VDD = 3.0 – 3.6V, IOL= 8 mA VDD = 4.5 – 5.5V, IOH= –16 mA VDD = 3.0 – 3.6V, IOH= –8 mA VDD = 4.5 – 5.5V, IOH= –8 mA VIN = 0V VIN = VDD VDD = 4.5 – 5.5V, output frequency