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CY2081
Three-PLL General-Purpose EPROM-Programmable Clock Generator
Features
• Factory-EPROM configurable for quick availability and prototyping • General purpose clock synthesizer for all applications – such as modems, disk drives, CD-ROM drives, Video CD players, games, set-top boxes, data/telecommunications, etc. • Three independent configurable clock outputs • Outputs ranging from 500 kHz to 100 MHz (5V) and up to 80 MHz for 3.3V operation • Configurable output control pin (pin 8) can be used as an output enable, power-down, suspend or select line. • Phase-locked loop oscillator input derived from external crystal (10 MHz to 25 MHz) or external reference clock (1 MHz to 30 MHz) • 3.3V or 5V operation (factory configured) • 8-pin 150-mil packaging achieves minimum footprint for space-critical applications • Sophisticated internal loop filter requires no external components or manufacturing tweaks as commonly required with external filters ured to operate off either a 3.3V or 5V power supply. The on-chip reference oscillator is designed for 10 MHz to 25 MHz crystals. Alternatively, a reference clock between 1 MHz and 30 MHz can be used. The CY2081 also features an output control pin (pin 8), which can be configured as an output enable, power down, frequency select, or suspend input. This gives the user the ability to three-state the output, power down the device, change the CLKA output frequency during operation, or suspend any of the outputs. Asserting the PD input will result in all the PLLs and the outputs being shut down. The PLLs will have to re-lock when the PD input is deasserted. The CY2081 outputs three clocks: CLKA, CLKB, and CLKC, whose frequencies can possess any value within the specified range. Additionally, the reference frequency can be obtained on any output. Custom configurations with user-defined features and frequencies can be obtained by filling out the custom configuration form located at the back of this data sheet and contacting your local Cypress representative. The CY2081 can replace multiple Metal Can Oscillators (MCO) in a synchronous system, providing cost and board space savings to manufacturers. Hence, this device is ideally suited for applications that require multiple, accurate, and stable clocks synthesized from low-cost generators in small packages. A hard disk drive is an example of such an application. In this case, CLKA drives the PLL in the Read Controller, while CLKB and CLKC drive the MCU and associated sequencers. Consider using the CY2291, CY2292, or CY2907 for applications that require more than three output clocks.
Functional Description
The CY2081 is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives, CD-ROM drives, Video CD players, games, set-top boxes and data/telecommunications. This devices offers three configurable clock outputs in an 8-pin 150-mil SOIC package and can be config-
Logic Block Diagram
Pin Configuration
SOIC Top View
CLKA GND XTALIN XTALOUT
1 2 3 4 8 7 6 5
OE/PD/FS/SUSPEND V DD CLKC CLKB
XTALIN XTALOUT
Reference Oscillator
PLL 1 EPROMConfigurable Multiplexer and Divide Logic
CLKA
PLL 2
CLKB
PLL 3
CLKC
OE/PD/FS/SUSPEND
Cypress Semiconductor Corporation Document #: 38-07136 Rev. **
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3901 North First Street
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San Jose
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CA 95134 • 408-943-2600 Revised September 26, 2001
CY2081
Pin Summary
Name CLKA GND XTALIN[1] XTALOUT CLKB CLKC VDD
[1,2]
Number 1 2 3 4 5 6 7
Description Configurable Clock Output Ground Reference Crystal Input or External Reference Clock Input Reference Crystal Feedback Configurable Clock Output Configurable Clock Output Voltage Supply Output control pin; either active-HIGH Output Enable, active-LOW power down, CLKA Frequency Select, or active-LOW Suspend input
OE / PD / FS / SUSPEND 8
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ............................................... –0.5V to +7.0V DC Input Voltage...................................... –0.5V to VDD+0.5V Storage Temperature ................................. –65°C to +150°C Junction Temperature...................................................150°C Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015)
Operating Conditions[3]
Parameter VDD TA CL fREF fREF Supply Voltage Operating Temperature, Ambient Max. Load Capacitance per output External Reference Crystal External Reference Clock
[4, 5]
Description
Min. 4.5 (3.0) 0 10.0 1.0
Max. 5.5 (3.6) 70 25 (15) 25.0 30.0
Unit V °C pF MHz MHz
Electrical Characteristics VDD = 5V (3.3V) ±10%, TA = 0°C to +70°C
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD IDDS Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[6] LOW-Level Output Voltage Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current
[7] [6]
Conditions IOH = –4.0 mA IOL = 4.0 mA Except Crystal Pins Except Crystal Pins VIN = VDD – 0.5V VIN = 0.5V Three State Outputs VDD = VDD max. 5V (3.3V) operation, CL = 25 pF (15 pF) Power-down Active, 5V Operation
Min. 2.4
Typ.
Max. 0.4
Unit V V V V µA µA µA mA µA
2.0 0.8 66.67 MHz Duty cycle for outputs, defined as t2 ÷ t1[11] fOUT ≤ 66.67 MHz t3 t4 t5 t6 Rise time Fall time Output clock rise time[12] at CL=25 pF (15 pF at 3.3V operation) Output clock fall time[12] at CL=25 pF (15 pF at 3.3V operation) 1 40% 45% Min. 10 [100 MHz] 12.5 [80 MHz]
