CY22050KFZXI

CY22050 One-PLL General-Purpose Flash-Programmable Clock Generator One-PLL General-Purpose Flash-Programmable Clock Generator Features Functional Description ■ Integrated phase-locked loop (PLL) The CY22050 is programmable clock generator for use in networking, telecommunication, datacom, and other general-purpose applications. The CY22050 offers up to six configurable outputs in a 16-pin TSSOP, running off a 3.3 V power supply. The on-chip reference oscillator is designed to run off an 8–30-MHz crystal, or a 1–133-MHz external clock signal. ■ Commercial and Industrial operation ■ Flash-programmable ■ Field-programmable ■ Low-skew, low-jitter, high-accuracy outputs ■ 3.3 V operation with 2.5 V output option ■ 16-pin TSSOP package (CY22050) ■ Input frequency range: ❐ 8 MHz–30 MHz (external crystal) ❐ 1 MHz–133 MHz (driven clock) ■ Output frequency range: ❐ Commercial temperature • 8 kHz–200 MHz (3.3 V) • 8 kHz–166.6 MHz (2.5 V) ❐ Industrial temperature • 8 kHz–166.6 MHz (3.3 V) • 8 kHz–150 MHz (2.5 V) The CY22050 has a single PLL driving 6 programmable output clocks. The output clocks are derived from the PLL or the reference frequency (REF). Output post dividers are available for either. Four of the outputs can be set as 3.3 V or 2.5 V, for use in a wide variety of portable and low-power applications. For a complete list of related documentation, click here. Logic Block Diagram LCLK1 Divider Bank 1 XIN XOUT OSC. Q LCLK2 Output Select Matrix  VCO P LCLK3 LCLK4 Divider Bank 2 PLL CLK5 CLK6 OE VDD Cypress Semiconductor Corporation Document Number: 38-07006 Rev. *O • AVDD AVSS VSS VDDL 198 Champion Court VSSL • PWRDWN San Jose, CA 95134-1709 • 408-943-2600 Revised January 28, 2015 CY22050 Contents Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 3 Programming Description ............................................... 4 Field Programming the CY22050F .............................. 4 CyberClocks Software .............................................. 4 CY3672 Development Kit ............................................ 4 Applications ...................................................................... 4 Controlling Jitter .......................................................... 4 CY22050 Frequency Calculation ..................................... 5 Clock Output Settings: Crosspoint Switch Matrix ........ 5 Reference Crystal Input ................................................... 6 Crystal Drive Level and Power .................................... 6 Absolute Maximum Conditions ....................................... 6 Recommended Operating Conditions ............................ 7 Recommended Crystal Specifications ........................... 7 DC Electrical Characteristics .......................................... 8 AC Electrical Characteristics .......................................... 8 Document Number: 38-07006 Rev. *O Test Circuit ........................................................................ 9 Switching Waveforms ...................................................... 9 Ordering Information ...................................................... 10 Possible Configurations ............................................. 10 Ordering Code Definitions ......................................... 10 16-pin TSSOP Package Characteristics ....................... 11 Package Drawing and Dimensions ............................... 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC® Solutions ...................................................... 15 Cypress Developer Community ................................. 15 Technical Support ..................................................... 15 Page 2 of 15 CY22050 Pin Configuration Figure 1. 16-pin TSSOP pinout XIN VDD 1 16 XOUT 2 15 AVDD 3 14 PWRDWN 4 13 CLK6 CLK5 VSS AVSS 5 12 LCLK4 VSSL 6 11 VDDL LCLK1 7 10 LCLK2 8 9 OE LCLK3 Pin Definitions Name Pin Number Description XIN 1 Reference Input. Driven by a crystal (8 MHz–30 MHz) or external clock (1 MHz–133 MHz). Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based on manufacturer, process, performance, or quality. VDD 2 3.3 V voltage supply AVDD 3 3.3 V analog voltage supply 4 Power Down. When pin 4 is driven LOW, the CY22050 goes into shut down mode. AVSS 5 Analog ground VSSL 6 LCLK ground PWRDWN [1] LCLK1 7 Configurable clock output 1 at VDDL level (3.3 V or 2.5 V) LCLK2 8 Configurable clock output 2 at VDDL level (3.3 V or 2.5 V) LCLK3 9 Configurable clock output 3 at VDDL level (3.3 V or 2.5 V) [1] 10 Output Enable. When pin 10 is driven LOW, all outputs are three-stated. VDDL 11 LCLK voltage supply (2.5 V or 3.3 V) OE LCLK4 12 Configurable clock output 4 at VDDL level (3.3 V or 2.5 V) VSS 13 Ground CLK5 14 Configurable clock output 5 (3.3 V) CLK6 15 Configurable clock output 6 (3.3 V) 16 Reference output XOUT [2] Notes 1. The CY22050 has no internal pull up or pull down resistors. PWRDWN and OE pins need to be driven as appropriate or tied to power or ground. 2. Float XOUT if XIN is driven by an external clock source. Document Number: 38-07006 Rev. *O Page 3 of 15 CY22050 Programming Description Applications Field Programming the CY22050F Controlling Jitter The CY22050 is programmed at the package level, that is, in a programmer socket, prior to installation on a PCB. The CY22050 is flash-technology based, so the parts can be reprogrammed up to 100 times. This allows for fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. Jitter is defined in many ways, including: phase noise, long-term jitter, cycle-to-cycle jitter, period jitter, absolute jitter, and deterministic jitter. These jitter terms are usually given in terms of rms, peak-to-peak, or in the case of phase noise dBC/Hz with respect to the fundamental frequency. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL (2.5 V or 3.3 V), temperature, and output load. Samples and small prototype quantities can be programmed on the CY3672 programmer. Cypress’s value-added distribution partners and third-party programming systems from BP Microsystems, HiLo Systems, and others are available for large-production quantities. CyberClocks Software CyberClocks is an easy-to-use software application that allows the user to custom-configure the CY22050. Within CyberClocks, select the CyClocksRT tool. Users can specify the REF, PLL frequency, output frequencies and/or post-dividers, and different functional options. CyClocksRT outputs an industry-standard JEDEC file used for programming the CY22050. CyClocksRT can be downloaded free of charge from the Cypress website at http://www.cypress.com. Install and run it on any PC running the Windows operating system. CY3672 Development Kit The Cypress CY3672 Development Kit comes complete with everything needed to design with the CY22050 and program samples and small prototype quantities. The kit comes with the latest version of CyClocksRT and a small portable programmer that connects to a PC for on-the-fly programming of custom frequencies. The JEDEC file output of CyClocksRT can be downloaded to the portable programmer for small-volume programming, or for use with a production programming system for larger volumes. Document Number: 38-07006 Rev. *O Power supply noise and clock output loading are two major system sources of clock jitter. Power supply noise can be mitigated by proper power supply decoupling (0.1-F ceramic cap) of the clock and ensuring a low-impedance ground to the chip. Reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter. Reducing the total number of active outputs also reduce jitter in a linear fashion. However, it is better to use two outputs to drive two loads than one output to drive two loads. The rate and magnitude that the PLL corrects the VCO frequency is directly related to jitter performance. If the rate is too slow, then long term jitter and phase noise is poor. Therefore, to improve long-term jitter and phase noise, reducing Q to a minimum is advisable. This technique increases the speed of the phase frequency detector, which in turn drives the input voltage of the VCO. In a similar manner, increasing P until the VCO is near its maximum rated speed also decreases long term jitter and phase noise. For example: input reference of 12 MHz; desired output frequency of 33.3 MHz. One might arrive at the following solution: Set Q = 3, P = 25, Post Div = 3. However, the best jitter results are Q = 2, P = 50, Post Div = 9. For additional information, refer to the application note, “Jitter in PLL-based Systems: Causes, Effects, and Solutions,” available at http://www.cypress.com (click on “Application Notes”), or contact your local Cypress Field Applications Engineer. Page 4 of 15 CY22050 CY22050 Frequency Calculation The CY22050 is an extremely flexible clock generator with up to six individual outputs, generated from an integrated PLL. There are four variables used to determine the final output frequency. They are: the input REF, the P and Q dividers, and the post divider. The three basic formulas for determining the final output frequency of a CY22150-based design are: ■ CLK = ((REF * P)/Q)/Post Divider ■ CLK = REF/Post Divider ■ CLK = REF The basic PLL block diagram is shown in Figure 2. Each of the six clock outputs has a total of seven output options available to it. There are six post divider options: /2 (two of these), /3, /4, /DIV1N, and DIV2N. DIV1N and DIV2N are separately calculated and can be independent of each other. The post divider options can be applied to the calculated PLL frequency or to the REF directly. In addition to the six post divider options, the seventh option bypasses the PLL and passes the REF directly to the crosspoint switch matrix. Figure 2. Basic PLL Block Diagram Divider Bank 1 REF Q VCO PFD /DIV1N LCLK1 /2 LCLK2 /3 LCLK3 P Divider Bank 2 /4 Crosspoint Switch Matrix /2 /DIV2N Clock Output Settings: Crosspoint Switch Matrix Each of the six clock outputs can come from any of seven unique frequency sources. The crosspoint switch matrix defines which LCLK4 CLK5 CLK6 source is attached to each individual clock output. Although it may seem that there are an unlimited number of divider options, there are several rules that must be taken into account when selecting divider options. Table 1. Clock Output Definition Clock Output Divider None Definition and Notes Clock output source is the reference input frequency. /DIV1N Clock output uses a generated /DIV1N option from Divider Bank 1. Allowable values for DIV1N are 4 to 130. If Divider Bank 1 is not being used, set DIV1N to 8. /2 Clock output uses a fixed /2 option from Divider Bank 1. If this option is used, DIV1N must be divisible by 4. /3 Clock output uses a fixed /3 option from Divider Bank 1. If this option is used, set DIV1N to 6. /DIV2N Clock output uses a generated /DIV2N option from Divider Bank 2. Allowable values for DIV2N are 4 to 130. If Divider Bank 2 is not being used, set DIV2N to 8. /2 Clock output uses a fixed /2 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 4. /4 Clock output 2 uses a fixed /4 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 8. Document Number: 38-07006 Rev. *O Page 5 of 15 CY22050 Reference Crystal Input The input crystal oscillator of the CY22050 is an important feature because of the flexibility it allows the user in selecting a crystal as a reference clock source. The oscillator inverter has programmable gain, allowing for maximum compatibility with a reference crystal, based on manufacturer, process, performance, and quality. The value of the input load capacitors is determined by eight bits in a programmable register. Total load capacitance is determined by the formula: CapLoad = (CL – CBRD – CCHIP)/0.09375 pF In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad is determined automatically and programmed into the CY22050. If you require greater control over the CapLoad value, consider using the CY22150 for serial configuration and control of the input load capacitors. For an external clock source, the default is 0. Input load capacitors are placed on the CY22050 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply, and temperature changes. Crystal Drive Level and Power Crystals are specified to accept a maximum drive level. Generally, larger crystals can accept more power. The drive level specification in the table below is a general upper bound for the power driven by the oscillator circuit in the CY22050. For a given voltage swing, power dissipation in the crystal is proportional to ESR and proportional to the square of the crystal frequency. (Note that actual ESR is sometimes much less than the value specified by the crystal manufacturer.) Power is also almost proportional to the square of CL. Power can be reduced to less than the DL specification in the table below by selecting a reduced frequency crystal with low CL and low R1 (ESR). Absolute Maximum Conditions Parameter Description Min Max Unit VDD Supply Voltage –0.5 7.0 V VDDL I/O Supply Voltage –0.5 7.0 V –65 125 °C [3] TS Storage Temperature TJ Junction Temperature – 125 °C Package Power Dissipation—Commercial Temp – 450 mW – 380 mW Package Power Dissipation—Industrial Temp ESD Digital Inputs AVSS – 0.3 AVDD + 0.3 Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDDL VSS – 0.3 VDDL +0.3 V – 2000 V Static Discharge Voltage per MIL-STD-833, Method 3015 V Note 3. Rated for 10 years Document Number: 38-07006 Rev. *O Page 6 of 15 CY22050 Recommended Operating Conditions Parameter Description Min Typ Max Unit VDD Operating Voltage 3.135 3.3 3.465 V VDDLHI Operating Voltage 3.135 3.3 3.465 V VDDLLO Operating Voltage 2.375 2.5 2.625 V TAC Ambient Commercial Temp 0 – 70 °C TAI Ambient Industrial Temp –40 – 85 °C CLOAD Max. Load Capacitance VDD/VDDL = 3.3 V – – 15 pF CLOAD Max. Load Capacitance VDDL = 2.5 V – – 15 pF fREFD Driven REF 1 – 133 MHz fREFC Crystal REF tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 8 – 30 MHz 0.05 – 500 ms Min Typ Max Unit 8 – 30 MHz 10 – 20 pF Recommended Crystal Specifications Parameter Description Comments fNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) Fundamental mode – – 50  DL Crystal drive level No external series resistor assumed – 0.5 2 mW Document Number: 38-07006 Rev. *O Parallel resonance, fundamental mode Page 7 of 15 CY22050 DC Electrical Characteristics Parameter [4] Condition Min Typ Max Unit IOH3.3 Output High Current Description VOH = VDD – 0.5 V, VDD/VDDL = 3.3 V 12 24 – mA IOL3.3 Output Low Current VOL = 0.5 V, VDD/VDDL = 3.3 V 12 24 – mA IOH2.5 Output High Current VOH = VDDL – 0.5 V, VDDL = 2.5 V 8 16 – mA IOL2.5 Output Low Current VOL = 0.5 V, VDDL = 2.5 V 8 16 – mA VIH Input High Voltage CMOS levels, 70% of VDD 0.7 – 1.0 VDD VIL Input Low Voltage CMOS levels, 30% of VDD 0 – 0.3 VDD IVDD[5, 6] IVDDL3.3[5, 6] IVDDL2.5[5, 6] Supply Current AVDD/VDD Current – 45 – mA Supply Current VDDL Current (VDDL = 3.465 V) – 25 – mA Supply Current VDDL Current (VDDL = 2.625 V) – 17 – mA IDDS Power Down Current VDD = VDDL = AVDD = 3.465 V – – 50 A IOHZ IOLZ Output Leakage VDD = VDDL = AVDD = 3.465 V – – 10 A Min Typ Max Unit Output frequency, Clock output limit, 3.3 V commercial temperature Clock output limit, 2.5 V 0.008 (8 kHz) – 200 MHz 0.008 (8 kHz) – 166.6 MHz Output frequency, industrial temperature Clock output limit, 3.3 V 0.008 (8 kHz) – 166.6 MHz Clock output limit, 2.5 V 0.008 (8 kHz) – 150 MHz Output duty cycle Duty cycle is defined in Figure 4, t1/t2, fOUT > 166 MHz, 50% of VDD 40 50 60 % Duty cycle is defined in Figure 4, t1/t2, fOUT < 166 MHz, 50% of VDD 45 50 55 % AC Electrical Characteristics Parameter [4] t1 t2 Description Condition t3LO Rising edge slew rate (VDDL = 2.5 V) Output clock rise time, 20%–80% of VDDL, defined in Figure 5 0.6 1.2 – V/ns t4LO Falling edge slew rate (VDDL = 2.5 V) Output clock fall time, 80%–20% of VDDL, defined in Figure 5 0.6 1.2 – V/ns t3HI Rising edge slew rate (VDDL = 3.3 V) Output clock rise time, 20%–80% of VDD/VDDL, defined in Figure 5 0.8 1.4 – V/ns t4HI Falling edge slew rate (VDDL = 3.3 V) Output clock fall time, 80%–20% of VDD/VDDL, defined in Figure 5 0.8 1.4 – V/ns t5 [7] Skew Output-output outputs – – 250 ps t6 [8] Clock jitter Peak-to-peak period jitter (see Figure 6) – 250 – ps t10 PLL lock time – 0.30 3 ms skew between related Notes 4. Not 100% tested, guaranteed by design. 5. IVDD currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz. All outputs are loaded with 15 pF. 6. Use CyClocksRT to calculate actual IVDD and IVDDL for specific output frequency configurations. 7. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram for more information. 8. Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL (2.5 V or 3.3 V), temperature, and output load. For more information, refer to the application note, “Jitter in PLL-based Systems: Causes, Effects, and Solutions,” available at http://www.cypress.com, or contact your local Cypress Field Applications Engineer. Document Number: 38-07006 Rev. *O Page 8 of 15 CY22050 Test Circuit Figure 3. Test Circuit VDD CLK out 0.1F OUTPUTS AVDD CLOAD VDDL 0.1 F 0.1 F GND Switching Waveforms Figure 4. Duty Cycle Definition: DC = t2/t1 t1 t2 CLK 50% 50% Figure 5. Rise and Fall Time Definitions t3 t4 80% CLK 20% Figure 6. Peak-to-Peak Jitter t6 CLK Document Number: 38-07006 Rev. *O Page 9 of 15 CY22050 Ordering Information Ordering Code Package Type CY22050KFI Temperature Operating Range Operating Voltage 16-pin TSSOP Industrial (–40 °C to 85 °C) 3.3 V CY22050KFZXC 16-pin TSSOP Commercial (0 °C to 70 °C) 3.3 V CY22050KFZXCT 16-pin TSSOP – Tape and Reel CY22050KFZXI 16-pin TSSOP Industrial (–40 °C to 85 °C) 3.3 V Pb-free Programmer CY3672-USB Programming Kit CY3695 CY22050F, CY22050KF Adapter for CY3672 Programmer Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales Representative for more information. Possible Configurations Ordering Code Package Type Temperature Operating Range Operating Voltage Commercial (0 °C to 70 °C) 3.3 V CY22050ZXC-xxxT [9] 16-pin TSSOP – Tape and Reel Commercial (0 °C to 70 °C) 3.3 V CY22050ZXI-xxx [9] 16-pin TSSOP Industrial (–40 °C to 85 °C) 3.3 V CY22050ZXI-xxxT [9] 16-pin TSSOP – Tape and Reel Industrial (–40 °C to 85 °C) 3.3 V CY22050KZXC-xxx [9] 16-pin TSSOP Commercial (0 °C to 70 °C) 3.3 V CY22050KZXC-xxxT [9] 16-pin TSSOP – Tape and Reel Commercial (0 °C to 70 °C) 3.3 V CY22050KZXI-xxx [9] 16-pin TSSOP Industrial (–40 °C to 85 °C) 3.3 V CY22050KZXI-xxxT [9] 16-pin TSSOP – Tape and Reel Industrial (–40 °C to 85 °C) 3.3 V CY22050ZXC-xxx 16-pin TSSOP [9] Ordering Code Definitions CY 22050X X Z X X - xxx X X = blank or T blank = tube; T = tape and reel Custom Configuration Code (Only for Factory Programmable Devices) Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: Z = 16-pin TSSOP Programming Option: X = F or blank F = Field Programmable, blank = Factory Programmed Device part number: 22050X = 22050K or 22050 X in Device part number: X = K or none K = Foundry Manufacturing Company ID: CY = Cypress Note 9. These are factory-programmed configurations. Factory programming is available for high-volume design opportunities of 100 Ku/year or more in production. For more details, contact your local Cypress field application engineer or Cypress sales representative. Document Number: 38-07006 Rev. *O Page 10 of 15 CY22050 16-pin TSSOP Package Characteristics Parameter Name Value Unit JA theta JA 115 °C/W Complexity Transistor Count 74,600 Transistors Package Drawing and Dimensions Figure 7. 16-pin TSSOP 4.40 mm Body Z16.173/ZZ16.173 Package Outline, 51-85091 51-85091 *E Document Number: 38-07006 Rev. *O Page 11 of 15 CY22050 Acronyms Acronym Document Conventions Description Units of Measure ESR Equivalent Series Resistance FAE Field Application Engineer °C degree Celsius I/O Input/Output dBC decibels relative to carrier JEDEC Joint Electron Devices Engineering Council Hz hertz OE Output Enable kHz kilohertz PC Personal Computer MHz megahertz PCB Printed Circuit Board µA microampere PLL Phase-Locked Loop µF microfarad TSSOP Thin Shrunk Small Outline Package mA milliampere VCO Voltage Controlled Oscillator mm millimeter ms millisecond mW milliwatt Document Number: 38-07006 Rev. *O Symbol Unit of Measure ns nanosecond  ohm % percent pF picofarad ps picosecond V volt W watt Page 12 of 15 CY22050 Document History Page Document Title: CY22050, One-PLL General-Purpose Flash-Programmable Clock Generator Document Number: 38-07006 Orig. of Change Submission Date Rev. ECN Description of Change ** 108185 CKN 08/08/01 New data sheet. *A 110054 CKN 03/04/02 Changed status from Preliminary to Final. *B 121862 RBI 12/14/02 Power up requirements added to Operating Conditions Information. *C 310575 RGL 01/20/05 Added Lead-free devices. *D 314233 RGL 01/31/05 Removed the Tape and Reel devices in the non-dash parts. *E 2440826 AESA 05/15/08 Added Note “Not recommended for new designs.” and “38-07409, CY3672 PTG Programming Kit”. Corrected “FTG” to “PTG” in Ordering information table. Added part numbers CY22050KFC, CY22050KFI, CY22050KFZXC, CY22050KFZXI, CY22050KZXC-xxx, CY22050KZXC-xxxT, CY22050KZXI-xxx, and CY22050KZXI-xxxT in ordering information table. Changed Lead-Free to Pb-free. Updated to new template. *F 2642064 KVM 01/21/09 Added CY220501 to title. Added CY220501KFZXI to ordering table. *G 2743347 KVM 07/24/09 Revised the Device Selection table on page 1 and renamed it. Updates to programmer and software descriptions. Clarified that IVDD and IVDDL are for loaded outputs. Updated footnotes to show that the standard part numbers are now with a “K”. Changed CY3672 part number to CY3672-USB, changed CY3672ADP000 to CY3695, and repositioned them in the Ordering Information table. Deleted part numbers CY22050ZC-xxxT, CY22050ZI-xxx and CY22050ZI-xxxT. *H 2899683 KVM 03/26/10 Updated Ordering Information: Removed inactive parts from ordering information table. Updated Possible Configurations: Moved xxx parts to ‘Possible Configurations’ table. Updated Package Drawing and Dimensions. *I 3167517 BASH 02/09/11 Add crystal parameter table on page 6, ordering code definition, acronym and units tables. Remove references to FTG. Deleted table 1 from page 1, device selection: this table provides no additional information. Consolidated its input/output range information as a “features” bullet. Removed “benefits” section. Updated footnote#9 on page 8. *J 3210223 BASH 03/30/2011 Updated Ordering Information (Removed CY220501KFZXI, CY22050KZXC-139 and CY22050KZXC-139T). Updated Package Drawing and Dimensions (spec 51-85091 (Changed revision from *B to *C)). *K 3366417 PURU 09/08/2011 Updated to new template. *L 3776296 PURU 10/12/2012 Updated Ordering Information (Updated part numbers (Added a new MPN namely CY22050KFZXCT)). Updated Package Drawing and Dimensions (spec 51-85091 (Changed revision from *C to *D)). Document Number: 38-07006 Rev. *O Page 13 of 15 CY22050 Document History Page (continued) Document Title: CY22050, One-PLL General-Purpose Flash-Programmable Clock Generator Document Number: 38-07006 Rev. ECN Orig. of Change Submission Date Description of Change *M 4531394 TAVA 10/15/2014 Updated Features: Replaced 80 kHz with 8 kHz under “Output frequency range”. Updated Clock Output Settings: Crosspoint Switch Matrix: Updated Table 1: Replaced “127” with “130” in “Definition and Notes” column corresponding to “/DIV1N” and “/DIV2N”. Updated AC Electrical Characteristics: Replaced 80 kHz with 8 kHz and 0.08 MHz with 0.008 MHz in minimum value of t1 parameter. Updated to new template. Completing Sunset Review. *N 4575273 TAVA 11/20/2014 Added related documentation hyperlink in page 1. Updated Ordering Information: Removed pruned part CY22050KFC. Updated Package Drawing and Dimensions. *O 4643736 TAVA 01/28/2015 Removed CY220501 related information in all instances across the document as the CY220501 MPN has already been removed in ordering information as the part got pruned. Updated Document Title to read as “CY22050, One-PLL General-Purpose Flash-Programmable Clock Generator”. Updated Ordering Information: Updated Possible Configurations: Updated details in “Ordering Code” column. Document Number: 38-07006 Rev. *O Page 14 of 15 CY22050 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2015. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07006 Rev. *O Revised January 28, 2015 Page 15 of 15 BP Microsystems is a trademark of BP Microsystems. Hilo Systems is a trademark of Hi-Lo Systems. All products and company names mentioned in this document may be the trademarks of their respective holders.