CY2210PVC-3

0 CY2210 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support Features • Mixed 2.5V and 3.3V Operation • Compliant to Intel® CK133 (CY2210-3) & CK133W (CY2210-2) synthesizer and driver specification • Multiple output clocks at different frequencies — Four CPU clocks, up to 133 MHz — Eight synchronous PCI clocks, 1 free-running — Two CPU/2 clocks, at one-half the CPU frequency — Four AGP clocks at 66 MHz — Three synchronous APIC clocks, at 16.67 MHz — One USB clock at 48 MHz — Two reference clocks at 14.318 MHz • Spread Spectrum clocking — 32.5-kHz modulation frequency @ 133 MHz — 33.1-kHz modulation frequency @ 100 MHz for CY2210-02/03 — 33.4-kHz modulation frequency @ 100 MHz for CY2210-04 — EPROM programmable percentage of spreading. Default is –0.6%, which is recommended by Intel • Power-down features • Three Select inputs • Low-skew and low-jitter outputs • OE and Test Mode support • 56-pin SSOP package Benefits Usable with Pentium® II and Pentium® III processors Single-chip main motherboard clock generator — Driven together, support 4 CPUs and a chipset — Support for 4 PCI slots and chipset — Drives up to two main memory clock generators, including DRCG (CPUCLK/2) — Support for multiple AGP slots — Support multiprocessing systems — Supports USB frequencies and I/O chip Enables reduction of EMI in some systems Supports mobile systems Supports up to eight CPU clock frequencies Meets tight system timing requirements at high frequency Enables ATE and “bed of nails” testing Widely available, standard package enables lower cost Logic Block Diagram Pin Configuration SSOP Top View REFCLK [0–1] (14.318 MHz) VSSREF REFCLK0 REFCLK1 VDDREF 1 2 3 4 5 6 7 8 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDAPIC APICCLK2 APICCLK1 APICCLK0 VSSAPIC VDDCPU/2 CPUCLK/2 (DRCG) CPUCLK/2 (DRCG) VSSCPU/2 VDDCPU CPUCLK3 CPUCLK2 VSSCPU VDDCPU CPUCLK1 CPUCLK0 VSSCPU AVDD AVSS PCI_STOP CPU_STOP PWR_DWN SPREAD SEL1 SEL0 VDDUSB USBCLK VSSUSB CPUCLK [0–3] CPU_STOP XTALIN XTALOUT 14.318 MHz OSC. XTALIN XTALOUT VSSPCI PCICLK_F (33.33 MHz) PCICLK [1–7] (33.33 MHz) APICCLK [0–2] (16.67 MHz) AGPCLK [0–3] (66.67 MHz) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PCICLK2 PCICLK3 VSSPCI PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 VSSPCI VSSAGP AGPCLK0 AGPCLK1 VDDAGP VSSAGP AGPCLK2 AGPCLK3 VDDAGP SEL133 SEL1 SEL0 SEL133 SPREAD PCI_STOP PWR_DWN EPROM SYS PLL USBCLK (48 MHz) Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07204 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY2210-2/-3/-4 CPU PLL Divider, EPROMProgDelay and Stop Logic CPUCLK/2 [0–1] (DRCG) PCICLK_F PCICLK1 VDDPCI 9 CY2210 Pin Summary Name VSSREF VDDREF VSSPCI VDDPCI VSSAGP VDDAGP VSSUSB VDDUSB VSSCPU VDDCPU VSSCPU/2 VDDCPU/2 VSSAPIC VDDAPIC AVSS AVDD XTALIN [1] Pins 1 4 7, 13, 19 10, 16 20, 24 23, 27 29 31 40, 44 43, 47 48 51 52 56 38 39 5 6 41, 42, 45, 46 9, 11, 12, 14, 15, 17, 18 8 49, 50 21, 22, 25, 26 53, 54, 55 2, 3 30 36 37 35 34 33 32 28 Description 3.3V Reference ground 3.3V Reference voltage supply 3.3V PCI ground 3.3V PCI voltage supply 3.3V AGP ground 3.3V AGP voltage supply 3.3V USB ground 3.3V USB voltage supply 2.5V CPU ground 2.5V CPU voltage supply 2.5V CPU/2 ground 2.5V CPU/2 voltage supply 2.5V APIC ground 2.5V APIC voltage supply Analog ground to PLL and Core Analog voltage supply to PLL and Core Reference crystal input Reference crystal feedback CPU clock outputs PCI clock outputs, synchronously running at 33.33 MHz Free running PCI clock CPU/2 clock outputs, drive memory clock generator AGP clock outputs, running at 66.66 MHz APIC clock outputs, running at 16.67 MHz Reference clock outputs, 14.318 MHz 48-MHz USB clock output Active LOW input, disables CPU and AGP clocks when asserted Active LOW input, disables PCI clocks when asserted Active LOW input, powers down part when asserted Active LOW input, enables spread spectrum when asserted CPU frequency select input (See Function Table) CPU frequency select input (See Function Table) CPU frequency select input (See Function Table) XTALOUT[1] CPUCLK [0–3] PCICLK [1–7] PCICLK_F CPUCLK/2 AGPCLK [0–3] APICCLK [0–2] REFCLK [0–1] USBCLK CPU_STOP PCI_STOP PWR_DWN SPREAD SEL1 SEL0 SEL133 Note: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, “Crystal Oscillator Topics.” Document #: 38-07204 Rev. *A Page 2 of 10 CY2210 Function Table[2] SEL133 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 SEL1 0 1 0 1 0 1 0 1 SEL0 CPUCLK (MHz) Hi-Z 100.227 100 100 TCLK/2 N/A 133.33 133.33 [3] CPUCLK/2 (MHz) Hi-Z 50.114 50 50 TCLK/4 N/A 66.67 66.67 [3] AGPCLK (MHz) Hi-Z 66.818 66.67 66.67 TCLK/4 N/A 66.67 66.67 [3] PCICLK (MHz) Hi-Z 33.409 33.33 33.33 TCLK/8 N/A 33.33 33.33 [3] USBCLK (MHz) Hi-Z 48.008 OFF 48 TCLK/2 N/A OFF 48 [3] REFCLK (MHz) Hi-Z 14.318 14.318 14.318 TCLK N/A 14.318 14.318 [3] APICCLK (MHz) Hi-Z 16.705[3] 16.67 16.67 TCLK/16 N/A 16.67 16.67 Actual Clock Frequency Values Target Frequency (MHz) -2 100.0 133.33 48.0 -3 100.0 133.33 48.0 -4 100.0 133.33 48.0 -2 99.126 132.769 48.008 Actual Frequency (MHz) -3 99.126 132.769 48.008 -4 100.227 132.769 48.008 -2 –8740 –4208 167 PPM -3 –8740 –4208 167 -4 +2714 –4208 167 Clock Output CPUCLK CPUCLK USBCLK Clock Enable Configuration CPU_STOP X 0 0 1 1 PWR_DWN 0 1 1 1 1 PCI_STOP X 0 1 0 1 CPUCLK LOW LOW LOW ON ON CPUCLK/2 LOW ON ON ON ON AGP LOW LOW LOW ON ON PCI LOW LOW ON LOW ON PCI_F LOW ON ON ON ON REF APIC LOW ON ON ON ON OSC. OFF ON ON ON ON VCOs OFF ON ON ON ON Clock Driver Impedances Impedance Buffer Name CPU, CPU/2, APIC USB, REF PCI, AGP VDD Range 2.375–2.625 3.135–3.465 3.135–3.465 Buffer Type Type 1 Type 3 Type 5 Minimum Ω 13.5 20 12 Typical Ω 29 40 30 Maximum Ω 45 60 55 Notes: 2. TCLK is a test clock driven in on the XTALIN input in test mode. 3. Only CY2210-2 supports this option. In CY2210-3, this selection is defined as “N/A” or “Reserved”. Document #: 38-07204 Rev. *A Page 3 of 10 CY2210 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage .................................................. –0.5 to +7.0V Input Voltage .............................................. –0.5V to VDD+0.5 Storage Temperature (Non-Condensing) ... –65°C to +150°C Junction Temperature............................................... +150°C Package Power Dissipation.............................................. 1W Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions Over which Electrical Parameters are Guaranteed Parameter VDDREF, VDDPCI, AVDD, VDDAGP, VDDUSB VDDCPU, VDDCPU/2 VDDAPIC TA CL Description 3.3V Supply Voltages CPU and CPU/2 Supply Voltage APIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK, CPUCLK/2, USBCLK, REF, APIC PCICLK, AGP Reference Frequency, Oscillator Nominal Value Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 14.318 0.05 Min. 3.135 2.375 2.375 0 Max. 3.465 2.625 2.625 70 20 30 14.318 50 MHz ms Unit V V V °C pF f(REF) tPU Electrical Characteristics Over the Operating Range Parameter VIH VIL VOH VOL IIH IIL IOH Description High-level Input Voltage Low-level Input Voltage Except Crystal Pads IOH = –1 mA IOH = –1 mA IOL = 1 mA IOL = 1 mA 2.0 2.4 0.4 0.4 10 10 VOH = 2.0V VOH = 2.0V VOH = 2.4V VOH = 2.4V VOL = 0.4V VOL = 0.4V VOL = 0.4V VOL = 0.4V –16 –20 –15 19 25 10 20 –60 –72 –51 49 58 24 49 10 90 160 100 200 µA mA mA µA µA mA µA µA mA V USB, REF, PCI, AGP Low-level Output Voltage Input High Current Input Low Current High-level Output Current[4] [4] Test Conditions Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 Min. Max. Unit 2.0 0.8 V V V High-level Output Voltage[4] CPU, CPU/2, APIC CPU, CPU/2, APIC USB, REF, PCI, AGP 0 < VIN < VDD 0 < VIN < VDD CPU, CPU/2 APIC USB, REF AGP, PCI –30 –100 IOL Low-level Output Current[4] CPU, CPU/2 APIC USB, REF AGP, PCI IOZ IDD2 IDD3 IDDPD2 IDDPD3 Output Leakage Current Three-state 2.5V Power Supply Current AVDD/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz 3.3V Power Supply Current AVDD/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz 2.5V Shutdown Current 3.3V Shutdown Current AVDD/VDD33 = 3.465V, VDD25 = 2.625V AVDD/VDDQ3 = 3.465V, VDD25 = 2.625V Note: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07204 Rev. *A Page 4 of 10 CY2210 Switching Characteristics[4, 5] Over the Operating Range Parameter t1 t2 t2 t2 t3 t3 t3 t6 t7 t8 t9 t10 t11 t12 t13 t14 All CPU, CPU/2, APIC USB, REF PCI, AGP CPU, CPU/2, APIC USB, REF PCI, AGP CPU CPU/2 APIC AGP PCI CPU, AGP AGP, PCI CPU, APIC CPU, PCI CPU CPU CPU CPU/2 APIC USB AGP REF CPU, PCI Output Description Output Duty Cycle[6] t1A/t1B Between 0.4V and 2.0V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 2.0V and 0.4V Between 2.4V and 0.4V Between 2.4V and 0.4V Measured at 1.25V Measured at 1.25V Measured at 1.25V Measured at 1.5V Measured at 1.5V CPU leads. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks AGP leads. Measured at 1.5V CPU leads. Measured at 1.25V CPU leads. Measured at 1.25V clocks and 1.5V for 3.3V clocks With all outputs running (CY2210-2) With all outputs running (CY2210-3/-4) With the USB output turned off (CY2210-3/-4) 0 1.5 1.5 1.5 Rising Edge Rate Rising Edge Rate Rising Edge Rate Falling Edge Rate Falling Edge Rate Falling Edge Rate CPU-CPU Skew CPU/2-CPU/2 Skew APIC-APIC Skew AGP-AGP Skew PCI-PCI Skew CPU-AGP Clock Skew AGP-PCI Clock Skew CPU-APIC Clock Skew CPU-PCI Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Settle Time CPU and PCI clock stabilization from power-up Test Conditions Min. 45 1.0 0.5 1.0 1.0 0.5 1.0 Max. 55 4.0 2.0 4.0 4.0 2.0 4.0 175 175 250 250 500 1.5 4.0 4 4 150 250 200 250 500 500 500 1000 3 Unit % V/ns V/ns V/ns V/ns V/ns V/ns ps ps ps ps ps ns ns ns ns ps ps ps ps ps ps ps ps ms Notes: 5. All parameters specified with loaded outputs. 6. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. Document #: 38-07204 Rev. *A Page 5 of 10 CY2210 Switching Waveforms Duty Cycle Timing t1A t1B All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t3 CPU-CPU Clock Skew CPUCLK CPUCLK t6 CPU/2 - CPU/2 Clock Skew CPU/2 CPU/2 t7 APIC-APIC Clock Skew APIC APIC t8 Document #: 38-07204 Rev. *A Page 6 of 10 CY2210 Switching Waveforms (continued) AGP-AGP Clock Skew AGP AGP t9 PCI-PCI Clock Skew PCI PCI t10 CPU-AGP Clock Skew CPU AGP t11 AGP - PCI Clock Skew AGP PCI t12 CPU-APIC Clock Skew CPU t13 APIC Document #: 38-07204 Rev. *A Page 7 of 10 CY2210 Switching Waveforms (continued) CPU-PCI Clock Skew CPU t14 PCI CPU_STOP Timing CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPU, CPU/2, AGP (External) [7, 8] PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Notes: 7. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles. 8. CPU_STOP may be applied asynchronously. It is synchronized internally. Document #: 38-07204 Rev. *A Page 8 of 10 CY2210 Test Circuit VDDPCI, VDDAGP, VDDUSB, VDDREF, AVDD 1, 7, 13, 19, 20, 24, 29, 38, 40, 44, 48, 52 4, 10, 16, 23, 27, 31 CY2210 VDDCPU, VDDCPU/2, VDDAPIC 43, 47, 51, 56 OUTPUTS CLOAD Note: Each supply pin must have an individual decoupling capacitor. Note: All capacitors must be placed as close to the pins as is physically possible. Ordering Information Ordering Code CY2210PVC-2/-3/-4 Package Name O56 Package Type 56-Pin SSOP Operating Range Commercial Package Diagram 56-Lead Shrunk Small Outline Package O56 51-85062-*C Document #: 38-07204 Rev. *A Page 9 of 10 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2210 Document Title: CY2210 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support Document Number: 38-07204 REV. ** *A ECN NO. 111724 121839 Issue Date 01/10/02 12/14/02 Orig. of Change DSG RBI Description of Change Change from Spec number: 38-00888 to 38-07204 Power up requirements added to Operating Conditions Information Document #: 38-07204 Rev. *A Page 10 of 10