CY22313ZXC

CY22313 Two-PLL Clock Generator with Direct Rambus™ (Lite) Support Features • • • • • • Benefits Two integrated phase-locked loops (PLLs) Ultra-accurate PLLs Direct Rambus™ clock support Two input selects 3.45V core; 3.45V, 2.5V, 1.8V, and 1.675V outputs 24-pin TSSOP package • High-performance PLL tailored for multimedia applications • Frequency tolerance within 1 PPM on all frequencies • One pair of differential output drivers, identical specification to CY2212 • Selectable 54.0-/53.946-MHz output and 294.912-/393.216-MHz Rambus® output • Supports output voltage requirements • Industry-standard packaging saves on board space Block Diagram XIN XOUT XTAL. OSC. Divide by 2 CONFIGURATION LOGIC LCLK Divider PLL1 54MOUT FS CLK S PLL2 CLKB Pin Configuration Frequency Select Tables VDDRP 1 24 S VSSRP 2 23 VDDR Xout 3 22 VSSR Xin 4 21 NC 5 VSSVPA FS 54MOUT Unit PPM 0 54 MHz 0 1 53.94605395 MHz –1 CLK S CLK, CLKB Unit PPM 20 CLKB 0 294.912 MHz 0 6 19 VSSR 1 393.216 MHz 0 VDDVPA 7 18 VDDR VSS54 8 17 NC LCLK Unit PPM 54MOUT 9 16 VDDL 9.216 MHz 0 10 15 VSSL FS VDD54 11 14 LCLK VDDVP 12 13 VSSVP Cypress Semiconductor Corporation Document #: 38-07434 Rev. *E • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 29, 2004 [+] Feedback CY22313 Pin Definitions Name Pin Numbers Pin Description VDDRP 1 Power for DRCG PLL VSSRP 2 Ground for DRCG PLL Xout 3 Crystal Output Xin 4 Crystal Input NC 5 Do Not Connect, Leave Floating VSSVPA 6 Analog Ground For Video PLL VDDVPA 7 Analog Power for Video PLL VSS54 8 Ground for 54MOUT 54MOUT 9 54-MHz/53.94605395-MHz Output FS 10 Frequency Select Pin for 54MOUT (internal pull-down resistor) VDD54 11 Power for 54MOUT VDDVP 12 Power for Video PLL VSSVP 13 Ground for Video PLL LCLK 14 LCLK Output VSSL 15 Ground for LCLK VDDL 16 Power for LCLK NC 17 Do Not Connect, Leave Floating VDDR 18 Power for DRCG CLK/CLKB VSSR 19 Ground for DRCG CLK/CLKB CLKB 20 Output Clock to Rambus (complement) CLK 21 Output Clock to Rambus VSSR 22 Ground for DRCG CLK/CLKB VDDR 23 Power for DRCG CLK/CLKB S 24 Frequency Select Pin for DRCG CLK/CLKB (internal pull-up resistor) Document #: 38-07434 Rev. *E Page 2 of 9 [+] Feedback CY22313 Absolute Maximum Conditions DC Input Voltage ..............................–0.5V to + (VDD + 0.5V) (Above which the useful life may be impaired. For user guidelines; not tested.) Supply Voltage ............................................... –0.5V to +4.0V Storage Temperature .................................. –65°C to +125°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................... 2000V Latch-up (per JEDEC 17) .................................... > ±200 mA [1] Recommended Operating Conditions Parameter VDDRP, VDDVPA, VDDVP, VDDR Description Min. Typ Max. Unit Supply Voltage for PLL’s, Crystal Oscillator, and 3.45V Outputs 3.15 3.45 3.6 V VDD54 (2.5V) Supply Voltage for 2.5V Outputs 2.25 2.5 2.75 V VDD54 (1.675V) Supply Voltage for 1.675V Outputs 1.6 1.675 1.75 V VDDL Supply Voltage for 1.8V Outputs 1.6 1.8 2.0 V tPU Power-up time for all VDDS to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms TA Operating Temperature, Ambient 0 +85 °C CLOAD_54MOUT Max. Load Capacitance, CMOS Output fREF External Reference Crystal 15 18.432 pF MHz Electrical Specifications Parameter IOH [2] Description Conditions outputs[3] Output High Current, 1.8V outputs[3] Output High Current, 2.5V Output High Current, 1.675V IOL[2] outputs[3] Min. Typ. Max. Unit VOH = VDD – 0.5, VDD = 2.5V 8 16 mA VOH = VDD – 0.5, VDD = 1.8V 6 12 mA VOH = VDD – 0.5, VDD = 1.675V 5 10 mA Output Low Current, 2.5V outputs[3] VOL = 0.5V, VDD = 2.5V 8 16 mA Output Low Current, 1.8V outputs[3] VOL = 0.5V, VDD = 1.8V Output Low Current, 1.675V outputs[3] VOL = 0.5V, VDD = 1.675V CXTAL Crystal Load Capacitance[3] Total effective load of internal load caps CLOAD_IN Input Pin Capacitance[3] Except crystal pins VIH HIGH-Level Input Voltage CMOS levels,% of VDDRP/VDDVPA/VDDVP VIL LOW-Level Input Voltage CMOS levels,% of VDDRP/VDDVPA/VDDVP 6 12 mA 5 10 mA 11[4] pF 7 pF 70% VDD 30% RI_FS FS Input Resistor Pull-down resistor on FS 60 RI_S S Input Resistor Pull-up resistor on S 10 IDD Total Power Supply Current Sum of all supply currents 150 VDD 225 kΩ 100 kΩ 125 mA Direct Rambus Electrical Specifications[3] Parameter Description Min. Typ. Max. Unit VCM Differential output common-mode voltage 1.35 1.75 V VX Differential output crossing-point voltage[5] 1.25 1.85 V single-ended)[6] 0.4 0.7 V 2.1 V 50 Ω VCOS Output Voltage swing (p-p VCOH Output high voltage VCOL Output low voltage 1.0 rOUT Output dynamic resistance (at pins)[7] 12 V Notes: 1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions. 2. LCLK and 54MOUT outputs only. 3. Guaranteed by design, not 100% tested. 4. Identical Crystal Load Capacitance as CY2212ZC-2. Use the same crystal and XIN / XOUT board layout as implemented with the original crystal-driven CY2212ZC-2. 5. Differential output crossing point voltages shown in Figure 1. 6. VCOS = VOH – VOL. 7. rOUT = ∆ VO/ ∆ IO. This is defined at the output pins, not at the measurement point of Figure 9. Document #: 38-07434 Rev. *E Page 3 of 9 [+] Feedback CY22313 Switching Characteristics[3] Parameter FPPM Description Conditions Frequency Error Part to Part, does not include PCB variation Min. [8] Over commercial temperature range[9] Duty cycle for all outputs, measured at VDD/2 Typ. Max. Unit ±5 ±10 PPM ±2 ±5 PPM DC Output Duty Cycle t3_54, 2.5 54MOUT Rising Edge Slew Rate 20% to 80% of VDD54, VDD54 = 2.5V t3_54, 1.675 54MOUT Rising Edge Slew Rate 20% to 80% of VDD54, VDD54 = 1.675V 0.35 0.5 2.5 V/ns t4_54, 2.5 54MOUT Falling Edge Slew Rate 80% to 20% of VDD54, VDD54 = 2.5V 0.75 1.2 4.0 V/ns t4_54, 1.675 54MOUT Falling Edge Slew Rate 80% to 20% of VDD54, VDD54 = 1.675V 0.35 0.5 tCR, tCF CLK/CLKB Rise and Fall Times 20% to 80% of output voltage 160 tCR-CF CLK/CLKB Rise and Fall Difference[10] 20% to 80% of output voltage t5 Lock Time[11] PLL lock time from power-up 45 50 55 % 0.75 1.2 4.0 V/ns 2.5 V/ns 400 ps 100 ps 1.0 3.0 ms Typ. Max. Unit Phase Noise Specifications Parameter Description Conditions Min. Phase Noise 54 MHz at 10-kHz offset –95 dBc Phase Noise 53.946 MHz at 10-kHz offset –92 dBc Jitter Specifications[3] Parameter Description Conditions Jitter[12] t6_LCLK LCLK t6_54, 2.5 54MOUT Jitter[12] t6_54, 1.675 Typ. Max. Unit Cycle-Cycle Jitter – 9.216 MHz 250 ps Cycle-Cycle Jitter – 54 MHz, VDD = 2.5V 150 ps Cycle-Cycle Jitter – 53.946 MHz, VDD = 2.5V 150 ps Cycle-Cycle Jitter – 54 MHz, VDD = 1.675V 250 ps Cycle-Cycle Jitter – 53.946 MHz, VDD = 1.675V 250 ps t7_LCLK LCLK 1000 Cycle Jitter[13] 1000 Cycle Jitter – 9.216 MHz 250 ps t7_54 54MOUT 1000 Cycle Jitter[13] 1000 Cycle Jitter – 54 MHz, 400 ps 1000 Cycle Jitter – 53.946 MHz, 400 ps Cycle-Cycle Jitter, 1–6 Cycles, 400 MHz 50 ps Cycle-Cycle Jitter, 1–6 Cycles, 300 MHz 70 ps Long-term Jitter, 400 MHz 300 ps Long-term Jitter, 300 MHz 400 ps Cycle-Cycle Duty Cycle Error, 400 MHz 50 ps Cycle-Cycle Duty Cycle Error, 300 MHz 70 ps t8 t9 t10 CLK/CLKB 1–6 Cycle CLK/CLKB Long-term Jitter[14] Jitter[15] [16] CLK/CLKB Duty Cycle Error Notes: 8. Tested across three lots on same board, PCB boards can vary more than ± 5 PPM. 9. Crystal should not be heated for this test, only IC. 10. Measured on same pin of a single device. 11. Lock Time shown in Figure 2. 12. LCLK and 54MOUT Cycle-Cycle Jitter shown in Figure 3. 13. LCLK and 54MOUT 1000 Cycle Jitter shown in Figure 4. 14. CLK/CLKB 1-6 Cycle Jitter specification is absolute value of worst case deviation, and is shown in Figure 5 and Figure 6. 15. CLK/CLKB Long Term Jitter shown in Figure 7. 16. CLK/CLKB Duty Cycle Error shown in Figure 8. Document #: 38-07434 Rev. *E Page 4 of 9 [+] Feedback CY22313 CLK Vx CLKB Figure 1. Direct Rambus Crossing Point Voltage VDD 80% Output t5 Output stable within PPM spec. Figure 2. PLL Lock Time tcycle,i tcycle,i+1 t6 = tcycle,i - tcycle,i+1 Figure 3. 54MOUT, LCLK Cycle-to-Cycle Jitter 1000 cycles ... 1000 cycles ... t1000cycle,i t1000cycle,i+1 t7 = t1000cycle,i - t1000cycle,i+1 Figure 4. 54MOUT, LCLK 1000 Cycle Jitter Document #: 38-07434 Rev. *E Page 5 of 9 [+] Feedback CY22313 CLK CLKB tCYCLE,i tCYCLE,i+1 t8 = tCYLCE,i – tCYCLE,i+1 over 10000 consecutive cycles Figure 5. CLK, CLKB Cycle-to-Cycle Jitter CLK CLKB t4CYCLE,i+1 t4CYCLE,i t8 = t4CYCLE,i - t4CYCLE,i+1 over 10000 consecutive cycles Figure 6. CLK, CLKB 4-Cycle-to-Cycle Jitter CLK CLKB tCYCLE t9 = tCYCLE,max – tCYCLE,min over 10000 cycles Figure 7. CLK, CLKB Long-term Jitter CLK Cycle i Cycle i+1 CLKB tPW+,i tCYCLE,i tPW+,i+1 tCYCLE,i+1 t10 = tPW+,i – tPW+,i+1 Figure 8. CLK, CLKB Duty Cycle Error Document #: 38-07434 Rev. *E Page 6 of 9 [+] Feedback CY22313 CF RS 22313 Measurement Point RT = ZCH RP CMID ZCH RP RS CF CMID RT = ZCH ZCH Measurement Point Figure 9. Direct Rambus Test Circuit All VDD 0.1 µF OUTPUTS CLK out CLOAD GND Figure 10. LCLK, 54MOUT Output Test Circuits Table 1. Direct Rambus Test Circuit Component Values Parameter Description Value Tolerance Unit RS Series Resistor 68 ±5% Ω RP Parallel Resistor 39 ±5% Ω Capacitor[17] CF Edge-Rate Filter CMID AC Ground Capacitor 15 ±10% pF 0.01 ±20% µF Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltages CY22313ZC Z24 24-lead TSSOP Commercial (TA = 0°C to 85°C) 3.45V CY22313ZCT Z24 24-lead TSSOP – Tape and Reel Commercial (TA = 0°C to 85°C) 3.45V Z24 24-lead TSSOP Commercial (TA = 0°C to 85°C) 3.45 Lead Free CY22313ZXC Z24 24-lead TSSOP − Tape and Reel Commercial (TA = 0°C to 85°C) Notes: 17. CF is OPTIONAL filter capacitor for adjusting edge rates and EMI. No filter capacitors are used for characterization and test data. CY22313ZXCT Document #: 38-07434 Rev. *E 3.45 Page 7 of 9 [+] Feedback CY22313 Package Drawing and Dimensions 24-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24 PIN 1 ID 1 6.25[0.246] 6.50[0.256] DIMENSION IN MM(INCHES) 4.30[0.169] 4.50[0.177] 24 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.25[0.010] BSC 1.10[0.043] MAX. GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 7.70[0.303] 7.90[0.311] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85119-*A Rambus is a registered trademark, and Direct Rambus is a trademark, of Rambus Inc. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07434 Rev. *E Page 8 of 9 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY22313 Document History Page Document Title: CY22313 Two-PLL Clock Generator with Direct Rambus™ (Lite) Support Document Number: 38-07434 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 117092 07/02/02 CKN New Data Sheet *A 121365 11/15/02 CKN Reordered Pin Description table Changed all 3.3V references to 3.45V Changed RI_FS min. spec to 60 KOhms Changed note 4 Inserted max. spec for Edge Rates Reduced min. spec for Edge Rates on 1.8V and 1.675V outputs Inserted phase noise specifications Created separate specs for Jitter, depending on output voltage Correctly specified CF in Table 1 *B 121773 02/17/03 CKN Added tPU row to the Recommended Operating Conditions table *C 125454 05/19/03 CKN Updated Switching Characteristics table Added CY22313LF ordering information and corresponding note *D 127393 06/12/03 RGL Removed “PRELIMINARY” Rephrased Note 18 to provide clarity on marking *E 239051 See ECN RGL Corrected the Lead Free Coding in the Ordering Information table Document #: 38-07434 Rev. *E Page 9 of 9 [+] Feedback