CY22392FC

CY22392 Three-PLL General Purpose FLASH Programmable Clock Generator Features ■ Three Integrated Phase-locked Loops ■ Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit Post Divide) ■ Improved Linear Crystal Load Capacitors ■ Flash Programmability ■ Field Programmable ■ Low-jitter, High-accuracy Outputs ■ Power Management Options (Shutdown, OE, Suspend) ■ Configurable Crystal Drive Strength ■ Frequency Select through three External LVTTL Inputs ■ 3.3V Operation ■ 16-pin TSSOP Packages ■ CyClocksRT™ Support Benefits ■ Generates up to three unique frequencies on six outputs up to 200 MHz from an external source. Functional upgrade for current CY2292 family. ■ Enables 0 ppm frequency generation and frequency conversion under the most demanding applications. ■ Improves frequency accuracy over temperature, age, process, and initial offset. ■ Nonvolatile programming enables easy customization, fast turnaround, performance tweaking, design timing margin testing, inventory control, lower part count, and more secure product supply. In addition, any part in the family can also be programmed multiple times, which reduces programming errors and provides an easy upgrade path for existing designs. ■ In-house programming of samples and prototype quantities is available using the CY3672 development kit. Production quantities are available through Cypress Semiconductor’s value added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. ■ Performance suitable for high-end multimedia, communications, industrial, A/D Converters, and consumer applications. ■ Supports numerous low power application schemes and reduces EMI by enabling unused outputs to be turned off. ■ Adjusts crystal drive strength for compatibility with virtually all crystals. ■ 3-bit external frequency select options for PLL1, CLKA, and CLKB. ■ Industry-standard supply voltage. ■ Industry-standard packaging saves on board space. ■ Easy to use software support for design entry. Logic Block Diagram XTALIN XTALOUT XBUF OSC. CONFIGURATION FLASH PLL1 11 BIT P 8 BIT Q SHUTDOWN/OE PLL2 S0 11 BIT P 8 BIT Q S1 S2/SUSPEND 4x4 Crosspoint Switch PLL3 11 BIT P 8 BIT Q Cypress Semiconductor Corporation Document #: 38-07013 Rev. *F • 198 Champion Court • Divider /2,3, or 4 CLKE Divider 7 BIT CLKD Divider 7 BIT CLKC Divider 7 BIT CLKB Divider 7 BIT CLKA San Jose, CA 95134-1709 • 408-943-2600 Revised July 16, 2009 [+] Feedback CY22392 Pinouts Figure 1. CY22392 - 16-pin TSSOP CLKC 1 16 VDD 2 15 S2/SUSPEND SHUTDOWN/OE AGND 3 14 AVDD XTALIN 4 13 S1 XTALOUT XBUF 5 12 6 11 S0 GND CLKD 7 10 CLKA CLKE 8 9 CLKB Table 1. Pin Definitions Name Pin Number Description CLKC 1 Configurable clock output C VDD 2 Power supply AGND 3 Analog Ground XTALIN 4 Reference crystal input or external reference clock input XTALOUT 5 Reference crystal feedback XBUF 6 Buffered reference clock output CLKD 7 Configurable clock output D CLKE 8 Configurable clock output E CLKB 9 Configurable clock output B CLKA 10 Configurable clock output A GND 11 Ground S0 12 General Purpose Input for Frequency Control; bit 0 S1 13 General Purpose Input for Frequency Control; bit 1 AVDD 14 Analog Power Supply S2/SUSPEND 15 General Purpose Input for Frequency Control; bit 2. Optionally Suspend mode control input. SHUTDOWN/OE 16 Places outputs in three-state condition and shuts down chip when Low. Optionally, only places outputs in tristate condition and does not shut down chip when Low Document #: 38-07013 Rev. *F Page 2 of 9 [+] Feedback CY22392 Operation The CY22392 is an upgrade to the existing CY2292. The new device has a wider frequency range, greater flexibility, improved performance, and incorporates many features that reduce PLL sensitivity to external system issues. The device has three PLLs which, when combined with the reference, enable up to four independent frequencies to be output on up to six pins. These three PLLs are completely programmable. Configurable PLLs PLL1 generates a frequency that is equal to the reference divided by an 8-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL1 is sent to the crosspoint switch. The output of PLL1 is also sent to a /2, /3, or /4 synchronous post-divider that is output through CLKE. The frequency of PLL1 can be changed by external CMOS inputs, S0, S1, S2. See the following section on General Purpose Inputs for more details. PLL2 generates a frequency that is equal to the reference divided by an 8-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL2 is sent to the crosspoint switch. PLL3 generates a frequency that is equal to the reference divided by an 8-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL3 is sent to the cross-point switch. General Purpose Inputs S0, S1, and S2 are general purpose inputs that can be programmed to enable eight different frequency settings. Options that may be switched with these general purpose inputs are as follows: the frequency of PLL1, the output divider of CLKB, and the output divider of CLKA. CLKA and CLKB both have 7-bit dividers that point to one of two programmable settings (register 0 and register 1). Both clocks share a single register control, so both must be set to register 0, or both must be set to register 1. The value of the load capacitors is determined by six bits in a programmable register. The load capacitance can be set with a resolution of 0.375 pF for a total crystal load range of 6 pF to 30 pF. For driven clock inputs the input load capacitors may be completely bypassed. This enables the clock chip to accept driven frequency inputs up to 166 MHz. If the application requires a driven input, then XTALOUT must be left floating. Output Configuration Under normal operation there are four internal frequency sources that may be routed through a programmable crosspoint switch to any of the four programmable 7-bit output dividers. The four sources are: reference, PLL1, PLL2, and PLL3. In addition, many outputs have a unique capability for even greater flexibility. The following is a description of each output. CLKA’s output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one of two programmable registers. Each of the eight possible combinations of S0, S1, S2 controls which of the two programmable registers is loaded into CLKA’s 7-bit post divider. See the section General Purpose Inputs for more information. CLKB’s output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one of two programmable registers. Each of the eight possible combinations of S0, S1, and S2 controls which of the two programmable registers is loaded into CLKA’s 7-bit post divider. See the section General Purpose Inputs for more information. CLKC’s output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one programmable register. CLKD’s output originates from the crosspoint switch and goes through a programmable 7-bit post divider. The 7-bit post divider derives its value from one programmable register. CLKE’s output originates from PLL1 and goes through a post divider that may be programmed to /2, /3, or /4. For example, the part may be programmed to use S0, S1, and S2 (0,0,0 to 1,1,1) to control eight different values of P and Q on PLL1. For each PLL1 P and Q setting, one of the two CLKA and CLKB divider registers can be chosen. Any divider change as a result of switching S0, S1, or S2 is guaranteed to be glitch free. XBUF is simply the buffered reference. Crystal Input Power Saving Features The input crystal oscillator is an important feature of this device because of its flexibility and performance features. The SHUTDOWN/OE input tristates the outputs when pulled low. If system shutdown is enabled, a Low on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins is less than 5 μA (typical). After leaving shutdown mode, the PLLs must relock. The oscillator inverter has programmable drive strength. This enables maximum compatibility with crystals from various manufacturers, processes, performances, and qualities. The input load capacitors are placed on-die to reduce external component cost. These capacitors are true parallel-plate capacitors for ultra-linear performance. These were chosen to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes. Non-linear (FET gate) crystal load capacitors must not be used for MPEG, POTS dial tone, communications, or other applications that are sensitive to absolute frequency requirements. Document #: 38-07013 Rev. *F The clock outputs have been designed to drive a single point load with a total lumped load capacitance of 15 pF. While driving multiple loads is possible with proper termination, it is generally not recommended. The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a tristate condition. Page 3 of 9 [+] Feedback CY22392 Improving Jitter Jitter Optimization Control is useful in mitigating problems related to similar clocks switching at the same moment, causing excess jitter. If one PLL is driving more than one output, the negative phase of the PLL can be selected for one of the outputs (CLKA–CLKD). This prevents the output edges from aligning, enabling superior jitter performance. Power Supply Sequencing For parts with multiple VDD pins, there are no power supply sequencing requirements. The part is not fully operational until all VDD pins have been brought up to the voltages specified in the Operating Conditions table. All grounds must be connected to the same ground plane. CyberClocks™ Software The CyberClocks application enables users to configure this device. Within CyberClocks, select the CyClocksRT tool. The easy-to-use interface offers complete control of the many features of this family including input frequency, PLL, output frequencies, and different functional options. Data sheet frequency range limitations are checked and performance tuning is automatically applied. CyClocksRT also has a power estimation feature that enables you to see the power consumption of your specific configuration. Download a copy of CyberClocks free on Cypress’s web site at www.cypress.com. Install and run it on any PC running Windows. CyberClocks software, devices can be programmed in small quantities using the CY3672 programmer and CY3698 adapter. Volume programming is available through Cypress Semiconductor’s value added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. For sufficiently large volumes, Cypress can supply pre-programmed devices with a part number extension that is configuration-specific. Junction Temperature Limitations It is possible to program the CY22392 such that the maximum junction temperature rating is exceeded. The package θJA is 115 C/W. Use the CyClocksRT power estimation feature to verify that the programmed configuration meets the junction temperature and package power dissipation maximum ratings. Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply Voltage................................................–0.5V to +7.0V DC Input Voltage ........................... –0.5V to + (AVDD + 0.5V) Storage Temperature ................................. –65°C to +125°C Junction Temperature .................................................. 125°C Data Retention at Tj = 125°C .................................>10 years Maximum Programming Cycles........................................100 Package Power Dissipation...................................... 350 mW Device Programming Part numbers starting with CY22392F are ‘field programmable’ devices. Field programmable devices are shipped unprogrammed, and must be programmed prior to installation on a PCB. After a programming file (.jed) is created using Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................... 2000V Latch up (according to JEDEC 17) ...................... > ±200 mA Operating Conditions The following table lists the recommended operating conditions.[1] Parameter Description VDD/AVDD Supply Voltage TA Commercial Operating Temperature, Ambient Industrial Operating Temperature, Ambient CLOAD_OUT Maximum Load Capacitance fREF External Reference Crystal [2], External Reference Clock Commercial External Reference Clock[2], Industrial tPU Power up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Min Typ Max Unit 3.135 3.3 3.465 V 0 – +70 °C –40 – +85 °C – – 15 pF 8 – 30 MHz 1 – 166 MHz 1 – 150 MHz 0.05 – 500 ms Notes 1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions. 2. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. Document #: 38-07013 Rev. *F Page 4 of 9 [+] Feedback CY22392 Electrical Characteristics Parameter Description Conditions IOH Output High Current[3] IOL Output Low Current [3] CXTAL_MIN Crystal Load Capacitance[3] [3] Min Typ Max Unit VOH = VDD – 0.5, VDD = 3.3 V 12 24 – mA VOL = 0.5V, VDD = 3.3 V 12 24 – mA Capload at minimum setting – 6 – pF Capload at maximum setting – 30 – pF Except crystal pins – 7 – pF CXTAL_MAX Crystal Load Capacitance CLOAD_IN Input Pin Capacitance[3] VIH High Level Input Voltage CMOS levels,% of AVDD 70% – – AVDD VIL Low Level Input Voltage CMOS levels,% of AVDD – – 30% AVDD IIH Input High Current VIN = AVDD – 0.3 V – 100 MHz or divider = 1, measured at VDD/2 40% 50% 60% t3 Rising Edge Slew Rate[3] Output clock rise time, 20% to 80% of VDD 0.75 1.4 – V/ns t4 Falling Edge Slew Rate[3] Output clock fall time, 80% to 20% of VDD 0.75 1.4 – V/ns t5 Output three-state Timing[3] Time for output to enter or leave three-state mode after SHUTDOWN/OE switches – 150 300 ns t6 Clock Jitter[3, 6] Peak-to-peak period jitter, CLK outputs measured at VDD/2 – 400 – ps t7 Lock Time[3] PLL Lock Time from Power up – 1.0 3 ms Notes 3. Guaranteed by design, not 100% tested. 4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications. 5. Reference Output duty cycle depends on XTALIN duty cycle. 6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate. Document #: 38-07013 Rev. *F Page 5 of 9 [+] Feedback CY22392 Switching Waveforms Figure 2. All Outputs, Duty Cycle, and Rise/Fall Time t1 t2 OUTPUT t3 t4 Figure 3. Output Three-State Timing OE t5 t5 ALL THREE-STATE OUTPUTS Figure 4. CLK Output Jitter t6 CLK OUTPUT Figure 5. Frequency Change SELECT OLD SELECT Fold NEW SELECT STABLE t7 Fnew OUTPUT Test Circuit AVDD 0 .1 μF OUTPUTS CLK out CLOAD VDD 0.1 μF GND Document #: 38-07013 Rev. *F Page 6 of 9 [+] Feedback CY22392 Ordering Information Ordering Code [8] Package Name Package Type Operating Range Operating Voltage CY22392FC Z16 16-TSSOP Commercial (TA = 0°C to 70°C) 3.3V CY22392ZC-xxx[7, 8] Z16 16-TSSOP Commercial (TA = 0°C to 70°C) 3.3V Z16 16-TSSOP – Tape and Reel Commercial (TA = 0°C to 70°C) 3.3V Z16 16-TSSOP Industrial (TA = –40°C to 85°C) 3.3V Z16 16-TSSOP – Tape and Reel Industrial (TA = –40°C to 85°C) 3.3V CY22392ZC-xxxT CY22392ZI-xxx [7, 8] [7, 8] [7, 8] CY22392ZI-xxxT CY3672-USB FTG Programmer CY3698 CY22392F, CY22393F CY22394F and CY22395F Adapter for CY3672-USB Pb Free CY22392FXC ZZ16 16-TSSOP Commercial (TA = 0°C to 70°C) 3.3V CY22392FXCT ZZ16 16-TSSOP – Tape and Reel Commercial (TA = 0°C to 70°C) 3.3V CY22392FXI ZZ16 16-TSSOP Industrial (TA = –40°C to 85°C) 3.3V CY22392FXIT ZZ16 16-TSSOP – Tape and Reel Industrial (TA = –40°C to 85°C) 3.3V CY22392ZXC-xxx[7] ZZ16 16-TSSOP Commercial (TA = 0°C to 70°C) 3.3V CY22392ZXC-xxxT[7] ZZ16 16-TSSOP – Tape and Reel Commercial (TA = 0°C to 70°C) 3.3V CY22392ZXI-xxx[7] ZZ16 16-TSSOP Industrial (TA = –40°C to 85°C) 3.3V CY22392ZXI-xxxT[7] ZZ16 16-TSSOP – Tape and Reel Industrial (TA = –40°C to 85°C) 3.3V Notes 7. The CY22392ZC-xxx, CY22392ZI-xxx, CY22392ZXC-xxx, and CY22392ZXI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of 100 Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative. 8. Not recommended for new designs. New designs should use P.-free devices. Document #: 38-07013 Rev. *F Page 7 of 9 [+] Feedback CY22392 Package Diagram Figure 6. 16-Pin TSSOP 4.40 MM Body PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A Document #: 38-07013 Rev. *F Page 8 of 9 [+] Feedback CY22392 Document History Page Document Title: CY22392 Three PLL General Purpose Flash Programmable Clock Generator Document Number: 38-07013 REV. ECN Orig. of Change Submission Description of Change Date ** 106738 TLG 07/03/01 New Data Sheet *A 108515 JWK 08/23/01 Updates based on characterization results. Removed “Preliminary” heading. Added paragraph on Junction Temperature limitations and part configurations. Removed soldering temperature rating. Split crystal load into two typical specs representing digital settings range. Changed t5 max to 300 ns. Changed t7 typical to 1.0 ms. *B 110052 CKN 12/09/01 Preliminary to Final. *C 121864 RBI 12/14/02 Power up requirements added to Operating Conditions Information *D 237811 RGL See ECN Added Lead Free Devices *E 2584052 AESA 10/10/08 Updated template. Added Note “Not recommended for new designs.” Added part number CY22392FC, CY22392FCT, CY22392ZC-xxxT, CY22392ZI-xxxT, CY3672-USB, CY3698, CY22392FXCT, CY22392FXIT, CY22392ZXC-xxxT, and CY22392ZXI-xxxT, in ordering information table. Removed part number CY22392FI in ordering information table. Changed Lead-Free to Pb-Free. *F 2740247 KVM/PYRS 07/17/2009 Updated the software section and added a section on programming. Added Electrical Characteristics table which was accidentally dropped in rev *E Ordering Information table: changed package name for Pb-free devices from Z16 to ZZ16; removed part number CY22392FCT Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers psoc.cypress.com clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com © Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07013 Rev. *F Revised July 16, 2009 Page 9 of 9 CyClocksRT is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback