CY2273A-1

CY2273A Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs Features • Mixed 2.5V and 3.3V operation • Complete clock solution for Pentium®, Pentium® II, Cyrix, and AMD processor-based motherboards — Four CPU clocks at 2.5V or 3.3V — Up to twelve 3.3V SDRAM clocks — Seven synchronous PCI clocks, one free-running — One 3.3V 48 MHz USB clock — One 2.5V IOAPIC clock (-3 option only) — Two AGP clocks at 60 or 66.6MHz (-2 option only) — One 3.3V Ref. clock at 14.318 MHz • I2C™ Serial Configuration Interface • Factory-EPROM programmable output drive and slew rate for EMI customization • Factory-EPROM programmable CPU clock frequencies for custom configurations • Power-down, CPU stop and PCI stop pins • Available in space-saving 48-pin SSOP package The CY2273A possesses power-down, CPU stop, and PCI stop pins for power management control. These inputs are multiplexed with SDRAM clock outputs, and are selected when the MODE pin is driven low. Additionally, the signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2273A outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits and factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control. CY2273A Selector Guide Clocks Outputs CPU (60, 66.6, 75, 83.3 MHz) CPU (60, 66.6 MHz) SDRAM PCI (30, 33.3MHz) USB/IR (48MHz) AGP (60 or 66MHz) IOAPIC (14.318MHz) Ref (14.318MHz) CPU-PCI delay Note: 1. One free-running PCI clock. CY2273A-3 only -1 4 -9/12 7[1] 1 --1 -2 4 -9/12 5[1] 1 2 -1 -3 -4 9/12 7[1] 1 -1 1 0 ns -4 4 -9/12 7[1] 1 --1 0 ns Functional Description The CY2273A is a clock synthesizer/driver for a Pentium, Pentium II, Cyrix, or AMD processor-based PC using Intel’s 82430TX, 82440LX, ALI Aladdin IV or Aladdin IV+ chipsets. The CY2273A-1 outputs four CPU clocks at 2.5V or 3.3V with up to 83.3MHz operation. There are seven PCI clocks, running at 30 and 33.3MHz. One of the PCI clocks is free-running. Additionally, the part outputs up to twelve 3.3V SDRAM clocks, one 3.3V USB clock at 48 MHz, and one 3.3V reference clock at 14.318 MHz. The CY2273A-2 is similar, except that PCICLK4 and PCICLK5 are now AGP clocks. The CY2273A-3 is more suited to Pentium II systems, as it outputs one 2.5V IOAPIC clock. Finally, the CY2273A-4 is similar to the CY2273A-1 except that is supports 0-ns CPU-PCI delay. 1–5.5 ns 1–5.5 ns Logic Block Diagram IOAPIC VDDQ2 XTALIN XTALOUT 14.318 MHz OSC. REF0 (14.318 MHz) CPU PLL STOP LOGIC CPUCLK [0-3] VDDCPU SEL0 SEL1 CY2273A-1,-2,-4 only EPROM SDRAM5/PWR_DWN SDRAM [0-4],[8-11] SDRAM6/CPU_STOP MODE SYS PLL Delay (-1,-2 option) /1 or /1.25 SDRAM7/PCI_STOP CY2273A-2 only AGP [0,1] /1 or /2 SERIAL INTERFACE CONTROL LOGIC STOP LOGIC PCI [0-5], PCI [0-3] PCICLK_F USBCLK (48 MHz) SCLK SDATA Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 12, 1998 CY2273A Pin Configurations CY2273A-1,-4 SSOP Top View AVDD REF0 VSS XTALIN XTALOUT VDDQ3 PCICLK_F PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDQ3 PCICLK5 VSS SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 VSS SDATA SCLK 1 2 3 4 5 6 7 8 CY2273A-1,-4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ3 USBCLK SEL1 VSS CPUCLK0 CPUCLK1 VDDCPU CPUCLK2 CPUCLK3 VSS SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5/PWR_DWN VDDQ3 SDRAM6/CPU_STOP SDRAM7/PCI_STOP VSS SEL0 MODE AVDD REF0 VSS XTALIN XTALOUT VDDQ3 PCICLK_F PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 AGP0 VDDQ3 AGP1 VSS SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 VSS SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CY2273A-2 SSOP Top View 48 47 46 45 44 43 42 41 40 CY2273A-2 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ3 USBCLK SEL1 VSS CPUCLK0 CPUCLK1 VDDCPU CPUCLK2 CPUCLK3 VSS SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5/PWR_DWN VDDQ3 SDRAM6/CPU_STOP SDRAM7/PCI_STOP VSS SEL0 MODE USBCLK REF0 VSS XTALIN XTALOUT VDDQ3 PCICLK_F PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDQ3 PCICLK5 VSS SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 VSS AVDD SDATA CY2273A-3 SSOP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 CY2273A-3 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ2 IOAPIC SEL0 VSS CPUCLK0 CPUCLK1 VDDCPU CPUCLK2 CPUCLK3 VSS SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5/PWR_DWN VDDQ3 SDRAM6/CPU_STOP SDRAM7/PCI_STOP VSS MODE SCLK 2 CY2273A Pin Summary Name VDDQ3 VDDQ2 VDDCPU AVDD VSS XTALIN[2] XTALOUT[2] SDRAM7/ PCI_STOP SDRAM6/ CPU_STOP SDRAM5/ PWR_DWN SDRAM[0:4], [8:11] SEL0 SEL1 CPUCLK[0:3] PCICLK[0:5] or PCICLK[0:3] PCICLK_F AGPCLK[0:1] IOAPIC REF0 USBCLK SDATA SCLK MODE Pins (-1, -4) 6, 14, 19, 30, 36, 48 N/A 42 1 3, 9, 16, 22, 27, 33, 39, 45 4 5 28 29 31 Pins (-2) 6, 14, 19, 30, 36, 48 N/A 42 1 3, 9, 16, 22, 27, 33, 39, 45 4 5 28 29 31 Pins (-3) 6, 14, 19, 30, 36 48 42 23 3, 9, 16, 22, 27, 33, 39, 45 4 5 28 29 31 Description 3.3V Digital voltage supply IOAPIC Digital voltage supply, 2.5V CPU Digital voltage supply, 2.5V or 3.3V Analog voltage supply, 3.3V Ground Reference crystal input Reference crystal feedback SDRAM clock output. Also, active low control input to stop PCI clocks, enabled when MODE is LOW. SDRAM clock output. Also, active low control input to stop CPU clocks, enabled when MODE is LOW. SDRAM clock output. Also, active low control input to power down device, enabled when MODE is LOW. 38, 37, 35, 34, 38, 37, 35, 34, 38, 37, 35, 34, SDRAM clock outputs 32, 21, 20, 18, 17 32, 21, 20, 18, 17 32, 21, 20, 18, 17 26 46 44, 43, 41, 40 8, 10, 11, 12, 13, 15 7 N/A N/A 2 47 23 24 25 26 46 44, 43, 41, 40 8, 10, 11, 12 7 13, 15 N/A 2 47 23 24 25 46 N/A 44, 43, 41, 40 8, 10, 11, 12, 13, 15 7 N/A 47 2 1 24 25 26 CPU frequency select input, bit 0 (See table below.) CPU frequency select input, bit 0 (See table below.) CPU clock outputs PCI clock outputs, at 30 or 33.33 MHz Free-running PCI clock output AGP clock outputs at 60 or 66.66 MHz IOAPIC clock output 3.3V Reference clock output USB Clock output at 48 MHz Serial data input for serial configuration port Serial clock input for serial configuration port Mode Select pin for enabling power management features Note: 2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. Function Table (-1, -2 and -4) SEL1 0 0 1 1 SEL0 0 1 0 1 2 2 2.5 2.5 CPU/PCI Ratio CPUCLK[0:3] SDRAM[0:11] 60.0 MHz 66.67 MHz 75.0 MHz 83.33 MHz PCICLK[0:5] PCICLK_F 30.0 MHz 33.33 MHz 30.0 MHz 33.33 MHz AGP (-2 Only) 60.0 MHz 66.66 MHz 60.0 MHz 66.66 MHz REF0 IOAPIC 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz USBCLK 48 MHz 48 MHz 48 MHz 48 MHz Function Table (-3) SEL0 0 1 CPU/PCI Ratio 2 2 CPUCLK[0:3]/SDRAM[0:11] 60.0 MHz 66.67 MHz PCICLK[0:5],PCICLK_F 30.0 MHz 33.33 MHz REF0/IOAPIC 14.318 MHz 14.318 MHz USBCLK 48 MHz 48 MHz 3 CY2273A Actual Clock Frequency Values Clock Output CPUCLK CPUCLK CPUCLK CPUCLK USBCLK Target Frequency (MHz) 66.67 60.0 75.0 83.33 48.0 Actual Frequency (MHz) 66.654 60.0 75.0 83.138 48.008 0 0 –1947 167 PPM –195 • Output impedance: 25Ω (typical) measured at 1.5V Power Management Logic[3] - Active when MODE pin is held ‘LOW’ CPU_STOP X 0 0 1 1 PCI_STOP PWR_DWN X 0 1 0 1 0 1 1 1 1 CPUCLK Low Low Low Low Low 33/30 MHz PCICLK PCICLK_F Stopped Running Running Running Running Other Clocks Stopped Running Running Running Running Osc. Off PLLs Off Running Running Running Running Running Running Running Running 60/66/75/83 MHz Low 60/66/75/83 MHz 30/33/30/33 MHz Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits should be programmed to “0”. • I2C Address for the CY2273 is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ---- Byte 0: Functional and Frequency Select Clock Register (1 = Enable, 0 = Disable) Bit Pin # Description (Reserved) drive to ‘0’ (Reserved) drive to ‘0’ (Reserved) drive to ‘0’ (Reserved) drive to ‘0’ (Reserved) drive to ‘0’ (Reserved) drive to ‘0’ Bit 1 1 1 0 0 Bit 0 1 - Three-State 0 - N/A 1 - Testmode 0 - Normal Operation Bit 7 -Bit 6 -Bit 5 -Bit 4 -Bit 3 -Bit 2 -Bit 1 -Bit 0 Select Functions Outputs Functional Description Three-State Test Mode[5] CPU Hi-Z TCLK/2[4] PCI, PCI_F Hi-Z TCLK/4 SDRAM Hi-Z TCLK/2 Ref Hi-Z TCLK IOAPIC Hi-Z TCLK USBCLK Hi-Z TCLK/2 -2 only AGP Hi-Z TCLK/2 Notes: 3. AGP clocks are driven on PCICLK5 and PCICLK4 on -2 option. These clocks behave similar to the PCICLK_F output, in that they are free-running and stop only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table. 4. TCLK supplied on the XTALIN pin in Test Mode. 5. Valid only for SEL1=0. 4 CY2273A Byte 1: CPU Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 47 (-1,-2, and -4) 1 (-3 only) N/A N/A N/A 40 41 43 44 Description USBCLK (Reserved) drive to ‘0’ (Reserved) drive to ‘0’ Not used - drive to ‘0’ CPUCLK3 (Active/Inactive) CPUCLK2 (Active/Inactive) CPUCLK1 (Active/Inactive) CPUCLK0 (Active/Inactive) Bit 3 Bit 2 Bit 1 Bit 0 12 11 10 8 Bit 4 13 Byte 2: PCI Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 -7 15 Pin # Description (Reserved) drive to ‘0’ PCICLK_F (Active/Inactive) PCICLK5 (Active/Inactive) (-1,-3 and -4) AGP1 (Active/Inactive) (-2 only) PCICLK4 (Active/Inactive) (-1,-3 and -4) AGP0 (Active/Inactive) (-2 only) PCICLK3 (Active/Inactive) PCICLK2 (Active/Inactive) PCICLK1 (Active/Inactive) PCICLK0 (Active/Inactive) Byte 3: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Bit 7 28 Bit 6 29 Bit 5 31 Bit 4 32 Bit 3 34 Bit 2 35 Bit 1 37 Bit 0 38 Byte 4: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # N/A N/A N/A N/A 17 18 20 21 Description Not used - drive to ‘0’ Not used - drive to ‘0’ Not used - drive to ‘0’ Not used - drive to ‘0’ SDRAM11 SDRAM10 SDRAM9 SDRAM8 Byte 5: Peripheral Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # N/A N/A N/A 47 N/A N/A N/A 2 Description (Reserved) drive to ‘0’ (Reserved) drive to ‘0’ (Reserved) drive to ‘0’ IOAPIC (Active/Inactive) (-3 only) (Reserved) drive to ‘0’ (Reserved) drive to ‘0’ (Reserved) drive to ‘0’ REF0 (Active/Inactive) Byte 6: Reserved, for future use 5 CY2273A Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................–0.5 to +7.0V Input Voltage .............................................. –0.5V to VDD+0.5 Storage Temperature (Non-Condensing) ... –65°C to +150°C Max. Soldering Temperature (10 sec) ...................... +260°C Junction Temperature ............................................... +150°C Package Power Dissipation .............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together) Operating Conditions[6] Parameter AVDD, V DDQ3 VDDCPU VDDQ2 TA CL CPU Supply Voltage IOAPIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK, USBCLK, IOAPIC PCICLK, AGP(-2 only), SDRAM REF0 Reference Frequency, Oscillator Nominal Value Description Analog and Digital Supply Voltage Min. 3.135 2.375 3.135 2.375 0 10 30, 20 20 14.318 Max. 3.465 2.9 3.465 2.9 70 20 30 45 14.318 MHz Unit V V V °C pF f(REF) Electrical Characteristics Over the Operating Range Parameter VIH VIL VILiic VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Low-level Input Voltage Except Crystal Inputs Except Crystal Inputs I2C inputs only IOH = 16 mA CPUCLK IOH = 18 mA IOAPIC Low-level Output Voltage VDDCPU = VDDQ2 = 2.375V IOL = 27 mA CPUCLK IOL = 29 mA IOAPIC High-level Output Voltage VDDQ3, AVDD, V DDCPU = 3.135V IOH = 16 mA CPUCLK IOH = 36 mA SDRAM IOH = 32 mA PCICLK IOH = 26 mA USBCLK IOH = 36 mA REF0 VOL Low-level Output Voltage VDDQ3, AVDD, V DDCPU = 3.135V IOL = 27 mA CPUCLK IOL = 29 mA SDRAM IOL = 26 mA PCICLK IOL = 21 mA USBCLK IOL = 29 mA REF0 IIH IIL IOZ IDD IDD IDDS Input High Current Input Low Current Output Leakage Current Power Supply Current[7] Power Supply Current[7] Power-down Current VIH = V DD VIL = 0V Three-state VDD = 3.465V, V IN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz VDD = 3.465V, V IN = 0 or VDD, Unloaded Outputs Current draw in power-down state –10 –10 +10 10 +10 300 120 500 µA µA µA mA mA µA 0.4V V 2.4 V 0.4 V 2.0 Test Conditions Min. Max. Unit 2.0 0.8 0.7 V V V V High-level Output Voltage VDDCPU = VDDQ2 = 2.375V Notes: 6. Electrical parameters are guaranteed with these operating conditions. 7. Power supply current will vary with number of outputs which are running. 6 CY2273A Switching Characteristics for CY2273A-1, CY2273A-2[8]Over the Operating Range Parameter t1 t2 t2 All CPUCLK SDRAM, PCI, REF0, USB AGP (-2 only) CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM PCICLK, PCICLK PCICLK, AGP (-2 only) CPUCLK, SDRAM PCICLK, AGP (-2 only) CPUCLK, PCICLK, AGP (-2 only), SDRAM Output Description Output Duty Cycle [9, 10] Test Conditions t1 = t1A ÷ t1B Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V Min. 45 0.75 0.85 Typ. 50 Max. 55 4.0 4.0 Unit % V/ns V/ns CPU Clock Rising and Falling Edge Rate[10] SDRAM, PCI, REF0 Clock Rising and Falling Edge Rate[10] AGP Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew CPU-SDRAM Clock Skew[10] PCI-PCI Clock Skew PCICLK-AGP Clock Skew (-2 only) Cycle-Cycle Clock Jitter[10] Cycle-Cycle Clock Jitter[10] Power-up Time t2 t3 t4 t5 t6 t7 t8 t9 t10 t10 t11 Between 0.4V and 2.4V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V, VDDCPU = 3.3V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V CPU, PCI, AGP, and SDRAM clock stabilization from power-up 0.85 0.4 0.5 0.4 0.5 100 1.0 3.0 4.0 2.13 2.67 2.13 2.67 250 5.5 650 500 500 250 500 3 V/ns ns ns ps ns ps ps ps ps ps ms Notes: 8. All parameters specified with loaded outputs. 9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V. 10. Measured at CPU=66.6 MHz, SDRAM=66.6 MHz, PCI=33.3 MHz, AGP=66.6 MHz. 7 CY2273A Switching Characteristics for CY2273A-3[8]Over the Operating Range Parameter t1 t2 Output All CPUCLK, IOAPIC REF0 USBCLK SDRAM PCI CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM PCICLK, PCICLK CPUCLK, SDRAM PCICLK CPUCLK, PCICLK, SDRAM Description Output Duty Cycle [9] Test Conditions t1 = t1A ÷ t1B Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Min. 45 0.75 Typ. 50 1.0 Max. 55 4.0 Unit % V/ns CPU and IOAPIC Clock Rising and Falling Edge Rate t2 t2 REF0 and USBCLK Ris- Between 0.4V and 2.4V ing and Falling Edge Rate SDRAM and PCI Clock Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew CPU-SDRAM Clock Skew PCI-PCI Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time Between 0.4V and 2.4V 1.0 0.85 1.0 4.0 4.0 V/ns V/ns t3 t4 t5 t6 t7 t8 t10 t10 t11 Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V, VDDCPU = 3.3V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V CPU, PCI, AGP, and SDRAM clock stabilization from power-up 0.4 0.5 0.4 0.5 100 2.13 2.67 2.13 2.67 300 900 600 500 750 500 3 ns ns ps ps ps ps ps ps ms 8 CY2273A Switching Characteristics for CY2273A-4[8]Over the Operating Range Parameter t1 t2 t2 Output All CPUCLK SDRAM PCI, REF0, USB CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM PCICLK, PCICLK CPUCLK, SDRAM PCICLK CPUCLK, PCICLK, SDRAM Description Output Duty Cycle [9] Test Conditions t1 = t1A ÷ t1B Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V Min. 45 0.75 0.85 Typ. 50 1.0 1.0 Max. 55 4.0 4.0 Unit % V/ns V/ns CPU Clock Rising and Falling Edge Rate SDRAM, PCI, REF0, USB Clock Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew CPU-SDRAM Clock Skew PCI-PCI Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time t3 t4 t5 t6 t7 t8 t10 t10 t10 t11 Between 0.4V and 2.0V, VDDCPU = 2.5V Between 2.0V and 0.4V, VDDCPU = 2.5V Measured at 1.25V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V Measured at 1.5V CPU, PCI, AGP, and SDRAM clock stabilization from power-up 0.4 0.4 100 2.13 2.13 250 1200 650 500 650 650 1200 3 ns ns ps ps ps ps ps ps ps ms Timing Requirement for the I2C Bus Parameter t12 t13 t14 t15 t16 t17 t18 SCLK Clock Frequency Time the bus must be free before a new transmission can start Hold time start condition. After this period the first clock pulse is generated. The Low period of the clock. The High period of the clock. Set-up time for start condition. (Only relevant for a repeated start condition.) Hold time DATA for CBUS compatible masters. for I2C devices DATA input set-up time Rise time of both SDATA and SCLK inputs Fall time of both SDATA and SCLK inputs Se-up time for stop condition 4.0 Description Min. 0 4.7 4 4.7 4 4.7 5 0 250 1 300 ns µs ns µs Max. 100 Unit kHz µs µs µs µs µs µs t19 t20 t21 t22 Switching Waveforms Duty Cycle Timing t1A t1B 9 CY2273A Switching Waveforms (continued) All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t3 t2 t4 CPU-CPU Clock Skew CPUCLK CPUCLK t5 CPU-SDRAM Clock Skew CPUCLK SDRAM t7 CPU-PCI Clock Skew CPUCLK PCICLK t6 PCI-PCI Clock Skew PCICLK PCICLK t8 AGP-PCI Clock Skew (-2 only) AGPCLK PCICLK t9 10 CY2273A Switching Waveforms (continued) CPU_STOP[11, 12] CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) PCI_STOP[13, 14] CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Timing Requirements for the I2C Bus SDA t13 SCL t14 t15 t20 t21 t14 t18 t16 t19 t17 t22 Notes: 11. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles. 12. CPU_STOP may be applied asynchronously. It is synchronized internally. 13. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK. 14. PCI_STOP may be applied asynchronously. It is synchronized internally. 11 CY2273A Application Information Clock traces must be terminated with either series or parallel termination, as they are normally done. Application Circuit Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF. In some cases, smaller value capacitors may be required. • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, R out is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > R trace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout and Termination Techniques for Cypress Clock Generators” for more details. • If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. 12 CY2273A Test Circuit VDDQ3 VDDQ3 1 0.1 µF 3 48 0.1 µF 45 23 0.1 µF 3 VDDQ2 48 0.1 µF 45 6 0.1 µF 9 39 CY2273A-1, -2, -4 14 0.1 µF 42 0.1 µF VDDCPU 0.1 µF 6 42 9 39 14 CY2273A-3 0.1 µF VDDCPU 36 0.1 µF 0.1 µF 36 0.1 µF 16 33 30 0.1 µF 27 0.1 µF 16 33 30 0.1 µF 27 0.1 µF 19 19 22 22 OUTPUTS CLOAD OUTPUTS CLOAD Note: All Capacitors must be placed as close to the pins as is possible Ordering Information Ordering Code CY2273APVC–1 CY2273APVC–2 CY2273APVC–3 CY2273APVC–4 Document #: 38–00615–D Package Name O48 O48 O48 O48 Package Type 48-Pin SSOP 48-Pin SSOP 48-Pin SSOP 48-Pin SSOP Operating Range Commercial Commercial Commercial Commercial 13 CY2273A Package Diagram 48-Lead Shrunk Small Outline Package O48 51-85061-B © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.