CY2277APAC-12M

7A CY2277A Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel® 82430TX and 2 DIMMs or 3 SO-DIMMs Features • Mixed 2.5V and 3.3V operation • Complete clock solution to meet requirements of Pentium®, Pentium® II, 6x86, or K6 motherboards — Four CPU clocks at 2.5V or 3.3V — Up to eight 3.3V SDRAM clocks — Seven 3.3V synchronous PCI clocks, one free running — Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable by serial interface — One 2.5V IOAPIC clock at 14.318 MHz — Two 3.3V Ref. clocks at 14.318 MHz • Factory-EPROM programmable CPU, PCI, and USB/IO clock frequencies for custom configuration • Factory-EPROM programmable output drive and slew rate for EMI customization • MODE Enable pin for CPU_STOP and PCI_STOP • SMBus serial configuration interface • Available in space-saving 48-pin SSOP and TSSOP packages. The CY2277A has power-down, CPU stop and PCI stop pins for power management control. The CPU stop and PCI stop are controlled by the MODE pin. They are multiplexed with SDRAM clock outputs, and are selected when the MODE pin is driven LOW. Additionally, these inputs are synchronized on-chip, enabling glitch-free transitions. When the CPU_STOP input is asserted, the CPU outputs are driven LOW. When the PCI_STOP input is asserted, the PCI outputs (except the free-running PCI clock) are driven LOW. Finally, when the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2277A outputs are designed for low EMI emission. Controlled rise and fall times, unique output driver circuits and factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control. CY2277A Selector Guide Clock Outputs CPU (60, 66.6 MHz) CPU (33.3, 66.6 MHz) CPU (SMBus selectable) PCI (CPU/2) SDRAM USB/IO (48 or 24 MHz) IOAPIC (14.318 MHz) Ref (14.318 MHz) CPU-PCI delay Note: 1. One free-running PCI clock. -1/-1M 4 --7[1] 6/8 2 1 2 -3 -4 -7[1] 6/8 2 1 2 -7M 4 --7[1] 6/8 2 1 2 2000V (per MIL-STD-883, Method 3015, like VDD pins tied together) Document #: 38-07332 Rev. *A Page 5 of 19 CY2277A Operating Conditions[6] Parameter AVDD, VDDQ3 VDDCPU Description Analog and Digital Supply Voltage 2.5V CPU Supply Voltage (-1,-1M, -3, -7M) 2.5V CPU Supply Voltage (-12, -12M, -12I) 3.3V CPU Supply Voltage 2.5V IOAPIC Supply Voltage (-1,-1M, -3, -7M) 2.5V IOAPIC Supply Voltage (-12, -12M, -12I) 3.3V IOAPIC Supply Voltage Operating Temperature, Commercial Operating Temperature, Industrial Max. Capacitive Load on CPUCLK, USBCLK/IOCLK, REF1, IOAPIC PCICLK, SDRAM REF0 Reference Frequency, Oscillator Nominal Value Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Min. 3.135 2.375 2.375 3.135 2.375 2.375 3.135 0 –40 10 30, 20 20 14.318 0.05 Max. 3.465 2.9 2.625 3.465 2.9 2.625 3.465 70 85 20 30 45 14.318 50 Unit V V VDDQ2 V °C °C pF TA TA CL f(REF) tPU MHz ms Electrical Characteristics (-1, -3, -12) Parameter VIH VIL VILiic VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Low-level Input Voltage High-level Output Voltage[7] Except Crystal Inputs Except Crystal Inputs SMBus inputs only VDDQ2 = VDDCPU = 2.375V VDDQ2 = VDDCPU = 2.375V IOH = 18 mA CPUCLK IOH = 18 mA IOAPIC Low-level Output Voltage[7] IOL = 29 mA CPUCLK IOL = 29 mA IOAPIC High-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V IOH = 32 mA CPUCLK IOH = 36 mA SDRAM IOH = 32 mA PCICLK IOH = 26 mA USBCLK IOH = 26 mA IOCLK IOH = 36 mA REF0 IOH = 26 mA REF1 VOL Low-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V IOL = 24 mA CPUCLK IOL = 29 mA SDRAM IOL = 26 mA PCICLK IOL = 21 mA USBCLK IOL = 21 mA IOCLK IOL = 29 mA REF0 IOL = 21 mA REF1 IIH IIL IIL IOZ IDD IDD IDDS Input High Current Input Low Current Input Low Current Output Leakage Current Power Supply Current[7, 8] Power Supply Current[7, 8] Power-down Current VIH = VDD VIL = 0V, except PWR_SEL VIL = 0V, PWR_SEL only Three-state VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs Current draw in power-down state, PWR_SEL = VDD –10 –10 +10 10 100 +10 250 120 150 µA µA µA µA mA mA µA 0.4V V 2.4 V 0.4 V 2.0 Test Conditions Min. Max. Unit 2.0 0.8 0.7 V V V V Document #: 38-07332 Rev. *A Page 6 of 19 CY2277A Electrical Characteristics (-1, -3, -12) Parameter Description Test Conditions Min. Max. Unit Notes: 6. Electrical parameters are guaranteed with these operating conditions. 7. Guaranteed by design and characterization. Not 100% tested in production. 8. Power supply current will vary with number of outputs which are running. Electrical Characteristics (-1M, -7M, -12M) Parameter VIH VIL VILiic VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Low-level Input Voltage Except Crystal Inputs Except Crystal Inputs SMBus inputs only IOH = 12.6 mA CPUCLK 1.75 IOH = 16.7mA Low-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V IOAPIC 0.4 2.4 V V IOL = 18.2 mA CPUCLK IOL = 23.1 mA IOAPIC High-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V IOH = 32.2 mA SDRAM IOH = 32.2 mA PCICLK IOH = 32.2 mA USBCLK IOH = 32.2 mA IOCLK IOH = 32.2 mA REF0 IOH = 32.2 mA REF1 VOL Low-level Output Voltage [7] Test Conditions Min. Max. Unit 2.0 0.8 0.7 V V V V High-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V VDDQ3, AVDD, VDDCPU = 3.135V IOL = 23.8 mA SDRAM IOL = 23.8 mA PCICLK IOL = 23.8 mA USBCLK IOL = 23.8 mA IOCLK IOL = 23.8 mA REF0 IOL = 23.8 mA REF1 0.8V V IIH IIL IIL IOZ IDD IDD IDDS Input High Current Input Low Current Input Low Current Output Leakage Current Power Supply Current[7, 8] Power Supply Current[7, 8] Power-down Current VIH = VDD VIL = 0V, except PWR_SEL VIL = 0V, PWR_SEL only Three-state VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs Current draw in power-down state, PWR_SEL = VDD –10 +10 10 100 µA µA µA µA mA mA µA –10 +10 250 120 150 Document #: 38-07332 Rev. *A Page 7 of 19 CY2277A Electrical Characteristics (-12I) Parameter VIH VIL VILiic VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Low-level Input Voltage Except Crystal Inputs Except Crystal Inputs SMBus inputs only IOH = 18 mA IOH = 18 mA Low-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V IOL = 29 mA IOL = 29 mA High-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V IOH = 32 mA IOH = 36 mA IOH = 32 mA IOH = 26 mA IOH = 26 mA IOH = 36 mA IOH = 26 mA VOL Low-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V IOH = 24mA IOH = 29 mA IOH = 26 mA IOL = 21 mA IOH = 21 mA IOL = 29mA IOH = 21 mA IIH IIL IIL IOZ IDD IDD IDDS Input High Current Input Low Current Input Low Current Output Leakage Current Power Supply Current Power-down Current [7, 8] Test Conditions Min. Max. Unit 2.0 0.8 0.7 CPUCLK IOAPIC CPUCLK IOAPIC CPUCLK SDRAM PCICLK USBCLK IOCLK REF0 REF1 CPUCLK SDRAM PCICLK USBCLK IOCLK REF0 REF1 –20 +20 10 100 –10 +10 250 120 150 µA µA µA µA mA mA µA 0.8V V 2.4 V 0.4 V 1.75 V V V V High-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V VIH = VDD VIL = 0V, except PWR_SEL VIL = 0V, PWR_SEL only Three-state VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs Current draw in power-down state, PWR_SEL = VDD Power Supply Current[7, 8] Document #: 38-07332 Rev. *A Page 8 of 19 CY2277A Switching Characteristics (-1, -3)[9, 10, 11] Parameter t1 Output CPUCLK SDRAM USBCLK IOCLK REF [0,1] IOAPIC PCI CPUCLK, IOAPIC PCI USBCLK, IOCLK, REF0 SDRAM REF1 CPUCLK USBCLK, IOCLK CPUCLK USBCLK, IOCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK SDRAM PCICLK USBCLK, IOCLK CPUCLK, PCICLK, SDRAM CPU, PCI, SDRAM Description Output Duty Cycle [12] Test Conditions t1 = t1A ÷ t1B Min. 45 Typ. 50 Max. 55 Unit % t1 t2 Output Duty Cycle[12] CPU and IOAPIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate USB, I/O, REF0 Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate REF1 Rising and Falling Edge Rate CPU Clock Rise Time USB Clock and I/O Clock Rise Time CPU Clock Fall Time USB Clock and I/O Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew (-1, -3) CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time t1 = t1A ÷ t1B Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V CPU clocks at 66.66 MHz Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V 40 0.75 0.75 0.75 0.8 50 55 4.0 4.0 4.0 4.0 % V/ns t2 t2 V/ns V/ns t2 t2 t3 t3 t4 t4 t5 t6 t7 t8 t8 t8 t8 t9 Between 0.4V and 2.4V SDRAM clocks at 66.66 MHz Between 0.4V and 2.4V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Between 2.4V and 0.4V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks and at 1.5V for 3.3V clocks Measured at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V CPU, PCI, and SDRAM clock stabilization from power-up Rate of change of frequency 1.0 0.5 0.4 0.5 4.0 2.0 2.13 2.0 2.5 V/ns V/ns ns ns ns ns ps ns ps ps ps ps ns ms 0.4 0.5 2.13 2.0 2.5 100 400 6.0 775 450 650 500 1.3 3 1.0 2.0 t10 Frequency Slew Rate 2 MHz/ ms Notes: 9. All parameters specified with loaded outputs. 10. Over the operating range unless otherwise specified. 11. Parameters specified with: VDDCPU = 2.5V, VDDQ2 = 2.5V, VDDQ3 = 3.3V. 12. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V. Document #: 38-07332 Rev. *A Page 9 of 19 CY2277A Switching Characteristics (-1M, -7M, -12M)[9, 10, 11] Parameter t1 Output CPUCLK SDRAM USBCLK REF [0,1] IOAPIC PCI CPUCLK, IOAPIC PCI USBCLK, REF0 SDRAM REF1 CPUCLK USBCLK CPUCLK USBCLK CPUCLK PCICLK SDRAM CPUCLK, PCICLK CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK SDRAM PCICLK USBCLK, IOCLK CPUCLK, PCICLK, SDRAM CPU, PCI, SDRAM Description Output Duty Cycle[12] Test Conditions t1 = t1A ÷ t1B Min. 45 Typ. 50 Max. 55 Unit % t1 t2 Output Duty Cycle[12] CPU and IOAPIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate USB, REF0 Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate REF1 Rising and Falling Edge Rate CPU Clock Rise Time USB Clock Rise Time CPU Clock Fall Time USB Clock Fall Time CPU-CPU Clock Skew PCI-PCI Clock Skew SDRAM-SDRAM Clock Skew CPU-PCI Clock Skew -1M, -12M CPU-PCI Clock Skew -7M CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time t1 = t1A ÷ t1B Between 0.4V and 2.0V, VDDCPU = 2.5V CPU clocks at 66.66 MHz Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V Between 0.4V and 2.4V SDRAM clocks at 66.66 MHz Between 0.4V and 2.4V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.0V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.0V and 0.4V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V Measured at 1.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks Measured at 1.5V Measured at 1.5V Measured at 1.5V CPU, PCI, and SDRAM clock stabilization from power-up Rate of change of frequency 45 0.60 50 55 4.0 % V/ns t2 t2 t2 t2 t3 t3 t4 t4 t5 t5 t5 t6 t6 t7 t8 t8 t8 t8 t9 0.65 0.65 0.70 0.5 0.4 0.4 100 4.0 4.0 4.0 2.0 2.4 2.5 2.4 2.5 250 400 300 V/ns V/ns V/ns V/ns ns ns ns ns ps ps ps ns ps ps ps ps ps ps ms 1.0 2.0 6.0 750 600 525 600 400 900 3 t10 Frequency Slew Rate 2 MHz/ ms Document #: 38-07332 Rev. *A Page 10 of 19 CY2277A Switching Characteristics (-12)[9, 10, 11] Parameter t1 t2 Output All Clocks CPUCLK, IOAPIC PCI REF0 SDRAM REF1 USBCLK IOCLK CPUCLK USBCLK, IOCLK CPUCLK USBCLK, IOCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK PCICLK CPUCLK, PCICLK, SDRAM CPU, PCI, SDRAM Description Output Duty Cycle [12] Test Conditions t1 = t1A ÷ t1B Between 0.6V and 1.8V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V CPU clocks at 66.6 MHz Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.8V and 2.4V, VDDCPU = 3.3V Between 0.5V and 2.0V SDRAM clocks at 66.6 MHz Between 0.4V and 2.4V Min. 45 1.0 1.0 1.0 1.0 1.5 0.5 Typ. 50 Max. 55 4.0 4.0 4.0 4.0 4.0 2.0 Unit % V/ns CPU and IOAPIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate REF0 Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate REF1, USB and IO Rising and Falling Edge Rate CPU Clock Rise Time USB Clock and I/O Clock Rise Time CPU Clock Fall Time USB Clock and I/O Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew (-12) CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time t2 t2 t2 t2 V/ns V/ns V/ns V/ns t3 t3 t4 t4 t5 t6 t7 t8 t8 t9 Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Between 2.4V and 0.4V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks and at 1.5V for 3.3V clocks Measured at 1.5V CPU, PCI, and SDRAM clock stabilization from power-up Rate of change of frequency 0.4 0.4 1.0 0.4 0.4 1.0 100 1.0 2.0 2.0 4.0 2.0 2.0 4.0 250 4.0 500 250 500 3 ns ns ns ns ps ns ps ps ps ms t10 Frequency Slew Rate 2 MHz/ ms Document #: 38-07332 Rev. *A Page 11 of 19 CY2277A Switching Characteristics (-12I)[9, 10, 11] Parameter t1 t2 Output All Clocks CPUCLK, IOAPIC PCI REF0 SDRAM REF1 USBCLK IOCLK CPUCLK USBCLK, IOCLK CPUCLK USBCLK, IOCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK PCICLK CPUCLK, PCICLK, SDRAM CPU, PCI, SDRAM Description Output Duty Cycle[12] CPU and IOAPIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate REF0 Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate REF1, USB and IO Rising and Falling Edge Rate CPU Clock Rise Time USB Clock and I/O Clock Rise Time CPU Clock Fall Time USB Clock and I/O Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew (-12) CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time Test Conditions t1 = t1A ÷ t1B Between 0.6V and 1.8V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V CPU clocks at 66.6 MHz Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.8V and 2.4V, VDDCPU = 3.3V Between 0.5V and 2.0V SDRAM clocks at 66.6 MHz Between 0.4V and 2.4V Min. 45 1.0 .8 .9 1.0 1 0.5 Typ. 50 Max. 55 4.0 4.0 4.0 4.0 4.0 2.0 Unit % V/ns t2 t2 t2 t2 V/ns V/ns V/ns V/ns t3 t3 t4 t4 t5 t6 t7 t8 t8 t9 Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Between 2.4V and 0.4V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks and at 1.5V for 3.3V clocks, VDDCPU =2.5V Measured at 1.5V CPU, PCI, and SDRAM clock stabilization from power-up Rate of change of frequency 0.4 0.4 1.0 0.4 0.4 1.0 100 1.0 3.0 2.0 4.0 3.0 2.0 4.0 250 4.0 625 350 500 3 ns ns ns ns ps ns ps ps ps ms t10 Frequency Slew Rate 2 MHz/ ms Document #: 38-07332 Rev. *A Page 12 of 19 CY2277A Timing Requirement for the SMBus Parameter t10 t11 t12 t13 t14 t15 t16 SCLK Clock Frequency Time the bus must be free before a new transmission can start Hold time start condition. After this period the first clock pulse is generated. The LOW period of the clock. The HIGH period of the clock. Setup time for start condition. (Only relevant for a repeated start condition.) Hold time DATA for CBUS compatible masters. for SMBus devices DATA input set-up time Rise time of both SDATA and SCLK inputs Fall time of both SDATA and SCLK inputs Set-up time for stop condition 4.0 Description Min. 0 4.7 4 4.7 4 4.7 5 0 250 1 300 ns µs ns µs Max. 100 Unit kHz µs µs µs µs µs µs t17 t18 t19 t20 Switching Waveforms Duty Cycle Timing t1B t1A CPUCLK Outputs HIGH/LOW Time t1C VDD OUTPUT 0V t1D All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t3 t2 t4 Document #: 38-07332 Rev. *A Page 13 of 19 CY2277A Switching Waveforms (continued) CPU-CPU Clock Skew CLK CLK t5 CPU-SDRAM Clock Skew CPUCLK SDRAM t7 CPU-PCI Clock Skew CPUCLK PCICLK t6 CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) [13, 14] Notes: 13. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles. 14. CPU_STOP may be applied asynchronously. It is synchronized internally. Document #: 38-07332 Rev. *A Page 14 of 19 CY2277A Switching Waveforms (continued) PCI_STOP [15, 16] CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN# CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Timing Requirements for the SMBus SDA t11 t18 t19 t12 SCL t12 t13 t16 t14 t17 t15 t20 Notes: 15. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK. 16. PCI_STOP may be applied asynchronously. It is synchronized internally. Document #: 38-07332 Rev. *A Page 15 of 19 CY2277A Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. Application Circuit Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints can be laid out for flexibility. • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF. In some cases, smaller value capacitors may be required. • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout and Termination Techniques for Cypress Clock Generators” for more details. • If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Document #: 38-07332 Rev. *A Page 16 of 19 CY2277A Test Circuit VDDQ3 48 3 0.1 µF 46 7 0.1 µF 10 43 40 37 15 0.1 µF 34 17 31 28 0.1 µF 25 0.1 µF OUTPUTS CLOAD 0.1 µF VDDCPU 0.1 µF VDDQ2 0.1 µF 0.1 µF 21 24 Note: All capacitors should be placed as close to each pin as possible. Ordering Information Ordering Code CY2277APVC-1 CY2277APAC-1M CY2277APVC-3 CY2277APAC-7M CY2277APVC-12 CY2277APAC-12M CY2277APVI-12 Package Name O48 Z48 O48 Z48 O48 Z48 O48 Package Type 48-Pin SSOP 48-Pin TSSOP 48-Pin SSOP 48-Pin TSSOP 48-Pin SSOP 48-Pin TSSOP 48-Pin SSOP Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Industrial Intel and Pentium are registered trademarks of Intel Corporation. All product or company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07332 Rev. *A Page 17 of 19 CY2277A Package Diagrams 48-Lead Shrunk Small Outline Package O48 51-85061-C 48-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48 51-85059-B Document #: 38-07332 Rev. *A Page 18 of 19 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2277A Document Title: CY2277A Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/Mobile PCs with Intel® 82430TX and 2 DIMMs or 3 SO-DIMMs Document Number: 38-07332 REV. ** *A ECN NO. 111731 121855 Issue Date 12/15/01 12/14/02 Orig. of Change DSG RBI Description of Change Change from Spec number: 38-00612 to 38-07332 Power up requirements added to Operating Conditions Information Document #: 38-07332 Rev. *A Page 19 of 19