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CDCE949, CDCEL949
SCAS844F – AUGUST 2007 – REVISED OCTOBER 2016
CDCE(L)913: Flexible Low Power LVCMOS Clock Generator
With SSC Support for EMI Reduction
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
Member of Programmable Clock Generator
Family
– CDCEx913: 1 PLLs, 3 Outputs
– CDCEx925: 2 PLLs, 5 Outputs
– CDCEx937: 3 PLLs, 7 Outputs
– CDCEx949: 4 PLLs, 9 Outputs
In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Settings
Flexible Input Clocking Concept
– External Crystal: 8 to 32 MHz
– On-Chip VCXO: Pull-Range ±150 ppm
– Single-Ended LVCMOS Up to 160 MHz
Free Selectable Output Frequency Up to 230 MHz
Low-Noise PLL Core
– PLL Loop Filter Components Integrated
– Low Period Jitter (Typical 60 ps)
Separate Output Supply Pins
– CDCE949: 3.3 V and 2.5 V
– CDCEL949: 1.8 V
Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2], for Example, SSC Selection,
Frequency Switching, Output Enable or Power
Down
– Generates Highly Accurate Clocks for Video,
Audio, USB, IEEE1394, RFID, Bluetooth®,
WLAN, Ethernet™, and GPS
– Generates Common Clock Frequencies Used
With TI-DaVinci™, OMAP™, DSPs
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
1.8-V Device Core Supply
Wide Temperature Range: –40°C to 85°C
Packaged in TSSOP
Development and Programming Kit for Easy PLL
Design and Programming (TI Pro-Clock™)
2 Applications
D-TVs, STBs, IP-STBs, DVD Players, DVD
Recorders, and Printers
3 Description
The CDCE949 and CDCEL949 are modular PLLbased low cost, high-performance, programmable
clock synthesizers, multipliers and dividers. They
generate up to 9 output clocks from a single input
frequency. Each output can be programmed insystem for any clock frequency up to 230 MHz, using
up to four independent configurable PLLs.
The CDCEx949 has separate output supply pins,
VDDOUT, 1.8 V for the CDCEL949, and 2.5 V to 3.3 V
for CDCE949.
The input accepts an external crystal or LVCMOS
clock signal. If an external crystal is used, an on-chip
load capacitor is adequate for most applications. The
value of the load capacitor is programmable from 0 to
20 pF. Additionally, an on-chip VCXO is selectable,
allowing synchronization of the output frequency to an
external control signal, that is, a PWM signal.
Device Information(1)
PART NUMBER
CDCE949
CDCEL949
PACKAGE
TSSOP (24)
BODY SIZE (NOM)
7.80 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Ethernet
PHY
USB
Controller
CDCE(L)9xx
Clock
25
MHz
WiFi
FPGA
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCE949, CDCEL949
SCAS844F – AUGUST 2007 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
9
1
1
1
2
4
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
EEPROM Specification ............................................. 8
Timing Requirements: CLK_IN ................................. 9
Timing Requirements: SDA/SCL .............................. 9
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 16
9.5 Programming........................................................... 17
9.6 Register Maps ......................................................... 18
10 Application and Implementation........................ 27
10.1 Application Information.......................................... 27
10.2 Typical Application ................................................ 27
11 Power Supply Recommendations ..................... 31
12 Layout................................................................... 31
12.1 Layout Guidelines ................................................. 31
12.2 Layout Example .................................................... 32
13 Device and Documentation Support ................. 33
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Device Support......................................................
Related Documentation.........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
34
34
14 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2016) to Revision F
•
Page
Changed data sheet title from: CDCEx949 Programmable 4-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and
3.3-V LVCMOS Outputs to: CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI
Reduction................................................................................................................................................................................ 1
Changes from Revision D (March 2010) to Revision E
Page
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Condensed down bullets in Features ..................................................................................................................................... 1
•
Deleted 'General Purpose Frequency Synthesizing' from Applications ................................................................................. 1
•
Updated values in the Thermal Information table to align with JEDEC standards ................................................................ 6
•
Changed Byte Read Protocol image, second S to Sr .......................................................................................................... 18
•
Changed 100 MHz < ƒVCO > 200 MHz; TO 80 MHz ≤ ƒVCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4 ................... 29
•
Changed under Example, fifth row, N", 2 places TO N' ....................................................................................................... 29
Changes from Revision C (October 2009) to Revision D
•
2
Page
Added PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096 foot to PLL1, PLL2, PLL3, & PLL4
Configure Register Table...................................................................................................................................................... 22
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SCAS844F – AUGUST 2007 – REVISED OCTOBER 2016
Changes from Revision B (September 2009) to Revision C
•
Page
Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments
sales or marketing representative for more information. ...................................................................................................... 15
Changes from Revision A (December 2007) to Revision B
•
Page
Added Note 3: SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table ................... 6
Changes from Original (August 2007) to Revision A
Page
•
Changed the THERMAL RESISTANCE FOR TSSOP table .................................................................................................. 6
•
Changed Generic Configuration Register table RID From: 0h To: Xb ................................................................................. 19
•
Added note to the PWDN description, Generic Configuration Register table ...................................................................... 19
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Product Folder Links: CDCE949 CDCEL949
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CDCE949, CDCEL949
SCAS844F – AUGUST 2007 – REVISED OCTOBER 2016
www.ti.com
5 Description (continued)
The deep M/N divider ratio allows the generation of zero-ppm audio or video, networking (WLAN, BlueTooth™,
Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as
27 MHz.
All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This
is a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically
adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.
The device supports non-volatile EEPROM programming for easy customization of the device to the application.
It is preset to a factory-default configuration. It can be reprogrammed to a different application configuration
before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable
through the SDA and SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including
frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing
between low level or 3-state for the output-disable function.
The CDCEx949 operates in a 1.8-V environment. It operates within a temperature range of –40°C to 85°C.
6 Pin Configuration and Functions
PW Package
24-Pin TSSOP
(Top View)
Xin/CLK
1
24
Xout
S0
2
23
SDA/S1
VDD
3
22
SCL/S2
VCtrl
4
21
Y1
GND
5
20
GND
VDDOUT
6
19
Y2
Y4
7
18
Y3
Y5
8
17
VDDOUT
GND
9
16
Y6
VDDOUT
10
15
Y7
Y8
11
14
GND
Y9
12
13
VDD
Not to scale
Pin Functions
PIN
NAME
NO.
GND
SCL/S2
(1)
4
TYPE (1)
DESCRIPTION
5, 9, 14, 20
G
Ground
22
I
SCL: Serial clock input (default configuration), LVCMOS; internal pullup 500 kΩ; or
S2: User-programmable control input; LVCMOS inputs; internal pullup 500 kΩ
G = Ground, I = Input, O = Output, P = Power
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Product Folder Links: CDCE949 CDCEL949
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SCAS844F – AUGUST 2007 – REVISED OCTOBER 2016
Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
SDA: Bidirectional serial data input/output (default configuration), LVCMOS; internal
pullup 500 kΩ; or
S1: User-programmable control input; LVCMOS inputs; internal pullup 500 kΩ
SDA/S1
23
I/O
S0
2
I
User-programmable control input S0; LVCMOS inputs; internal pullup 500 kΩ
VCtrl
4
I
VCXO control voltage (leave open or pull up when not used)
VDD
3, 13
P
1.8-V power supply for the device
VDDOUT
6, 10, 17
P
Xin/CLK
1
I
Crystal oscillator input or LVCMOS clock input (selectable through SDA/SCL bus)
Xout
24
O
Crystal oscillator output (leave open or pull up when not used)
Y1
21
Y2
19
Y3
18
Y4
7
O
LVCMOS output
Y5
8
Y6
16
Y7
15
Y8
11
Y9
12
CDCEL949: 1.8-V supply for all outputs
CDCE949: 3.3-V or 2.5-V supply for all outputs
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage
VI
Input voltage (2)
(3)
(2)
MIN
MAX
UNIT
–0.5
2.5
V
–0.5
VDD + 0.5
V
–0.5
VDDOUT + 0.5
V
20
mA
VO
Output voltage
II
Input current (VI < 0, VI > VDD)
IO
Continuous output current
50
mA
TJ
Junction temperature
125
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.
SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2007–2016, Texas Instruments Incorporated
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7.3 Recommended Operating Conditions
VDD
Device supply voltage
VDD(OUT)
Output Yx supply voltage
VIL
Low level input voltage LVCMOS
VIH
High level input voltage LVCMOS
VI(thresh)
Input voltage threshold LVCMOS
VIS
Input voltage
VICLK
Input voltage CLK
IOH /IOL
MIN
NOM
MAX
1.7
1.8
1.9
CDCE949
2.3
3.6
CDCEL949
1.7
1.9
0.3 × VDD
0.7 × VDD
CL
Output load LVCMOS
TA
Operating free-air temperature
V
V
V
V
0.5 × VDD
V
S0
0
1.9
S1, S2, SDA, SCL,
VIthresh = 0.5 × VDD
0
3.6
0
Output current
UNIT
V
1.9
V
VDDout = 3.3 V
±12
mA
VDDout = 2.5 V
±10
mA
VDDout = 1.8 V
±8
mA
10
pF
85
°C
32
MHz
–40
CRYSTAL AND VCXO (1)
fXtal
Crystal Input frequency (fundamental mode)
ESR
Effective series resistance
fPR
Pulling (0 V ≤ VCtrl ≤ 1.8 V) (2)
V(Ctrl)
Frequency control voltage
C0/C1
Pullability ratio
CL
On-chip load capacitance at Xin and Xout
(1)
(2)
8
27
100
±120
±150
Ω
ppm
0
VDD
V
220
0
20
pF
For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family
(SCAA085).
Pulling range depends on crystal type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
7.4 Thermal Information
CDCEx949
THERMAL METRIC (1)
PW (TSSOP)
UNIT
24 PINS
Junction-to-ambient thermal resistance
θJA
(2)
Airflow 0 (LFM)
91
Airflow 150 (LFM)
75
Airflow 200 (LFM)
74
Airflow 250 (LFM)
73
Airflow 500 (LFM)
θJCtop
Junction-to-case (top) thermal resistance
θJB
ψJT
°C/W
65
0.5
°C/W
Junction-to-board thermal resistance
52
°C/W
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
50.1
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
50
°C/W
(1)
(2)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
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SCAS844F – AUGUST 2007 – REVISED OCTOBER 2016
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
All PLLs on
TYP (1)
MAX
38
UNIT
IDD
Supply current (see Figure 1)
All outputs off, fCLK = 27
MHz, fVCO= 135 MHz
IDD(OUT)
Supply current
(see Figure 2 and Figure 3)
No load, all outputs on,
fout = 27 MHz
IDD(PD)
Power down current
Every circuit powered down except SDA/SCL,
fIN = 0 MHz, VDD = 1.9 V
V(PUC)
Supply voltage VDD threshold
for power up control circuit
0.85
1.45
V
fVCO
VCO frequency range of PLL
80
230
MHz
fOUT
LVCMOS output frequency
Per PLL
9
CDCE949
VDDOUT = 3.3 V
4
CDCEL949
VDDOUT = 1.8 V
2
mA
mA
50
µA
230
MHz
LVCMOS
VIK
LVCMOS input voltage
VDD = 1.7 V, II = –18 mA
II
LVCMOS input current
VI = 0 V or VDD, VDD = 1.9 V
IIH
LVCMOS input current for
S0/S1/S2
IIL
CI
–1.2
V
±5
µA
VI = VDD, VDD = 1.9 V
5
µA
LVCMOS input current for
S0/S1/S2
VI = 0 V, VDD = 1.9 V
–4
µA
Input capacitance at Xin/Clk
VICLK = 0 V or VDD
6
Input capacitance at Xout
VIXout = 0 V or VDD
2
Input capacitance at
S0/S1/S2
VIS = 0 V or VDD
3
pF
CDCE949 – LVCMOS FOR VDDOUT = 3.3 V
LVCMOS high-level output
voltage
VOH
LVCMOS low-level output
voltage
VOL
VDDOUT = 3 V, IOH = –0.1 mA
2.9
VDDOUT = 3 V, IOH = –8 mA
2.4
VDDOUT = 3 V, IOH = –12 mA
2.2
V
VDDOUT = 3 V, IOL = 0.1 mA
0.1
VDDOUT = 3 V, IOL = 8 mA
0.5
VDDOUT = 3 V, IOL = 12 mA
0.8
tPLH,
tPHL
Propagation delay
PLL bypass
3.2
tr/tf
Rise and fall time
VDDOUT = 3.3 V (20%–80%)
0.6
1 PLL switching, Y2-to-Y3
60
90
4 PLLs switching, Y2-to-Y9
120
170
1 PLL switching, Y2-to-Y3
70
100
4 PLLs switching, Y2-to-Y9
130
180
tjit(cc)
Cycle-to-cycle jitter (2) (3)
tjit(per)
Peak-to-peak period
jitter (2) (3)
tsk(o)
Output skew (4)
odc
Output duty cycle (5)
fOUT = 50 MHz, Y1-to-Y3
fVCO = 100 MHz, Pdiv = 1
ns
ns
60
fOUT = 50 MHz, Y2-to-Y5 or Y6-to-Y9
160
45%
V
ps
ps
ps
55%
CDCE949 – LVCMOS FOR VDDOUT = 2.5 V
VOH
(1)
(2)
(3)
(4)
(5)
LVCMOS high-level output
voltage
VDDOUT = 2.3 V, IOH = –0.1 mA
2.2
VDDOUT = 2.3 V, IOH = –6 mA
1.7
VDDOUT = 2.3 V, IOH = –10 mA
1.6
V
All typical values are at respective nominal VDD.
10000 cycles.
Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (measured at
Y2), 4-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (manured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz, Y8/9 = 48 MHz.
The tsk(o) specification is only valid for equal loading of each bank of outputs and outputs are generated from the same divider; data
sampled on rising edge (tr).
odc depends on output rise- and fall-time (tr/tf).
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
LVCMOS low-level output
voltage
VOL
TYP (1)
MIN
MAX
VDDOUT = 2.3 V, IOL = 0.1 mA
0.1
VDDOUT = 2.3 V, IOL = 6 mA
0.5
VDDOUT = 2.3 V, IOL = 10 mA
0.7
tPLH,
tPHL
Propagation delay
PLL bypass
3.4
tr/tf
Rise and fall time
VDDOUT = 2.5 V (20%–80%)
0.8
1 PLL switching, Y2-to-Y3
60
90
4 PLLs switching, Y2-to-Y9
120
170
1 PLL switching, Y2-to-Y3
70
100
4 PLLs switching, Y2-to-Y9
130
180
tjit(cc)
Cycle-to-cycle jitter (2) (3)
tjit(per)
Peak-to-peak period
jitter (2) (3)
tsk(o)
Output skew (4)
odc
Output duty cycle (5)
fOUT = 50 MHz, Y1-to-Y3
ns
160
fVCO = 100 MHz, Pdiv = 1
45%
V
ns
60
fOUT = 50 MHz, Y2-to-Y5 or Y6-to-Y9
UNIT
ps
ps
ps
55%
CDCEL949 – LVCMOS FOR VDDOUT = 1.8 V
LVCMOS high-level output
voltage
VOH
LVCMOS low-level output
voltage
VOL
VDDOUT = 1.7 V, IOH = –0.1 mA
1.6
VDDOUT = 1.7 V, IOH = –4 mA
1.4
VDDOUT = 1.7 V, IOH = –8 mA
1.1
V
VDDOUT = 1.7 V, IOL = 0.1 mA
0.1
VDDOUT = 1.7 V, IOL = 4 mA
0.3
VDDOUT = 1.7 V, IOL = 8 mA
0.6
tPLH,
tPHL
Propagation delay
PLL bypass
2.6
tr/tf
Rise and fall time
VDDOUT = 1.8 V (20%–80%)
0.7
1 PLL switching, Y2-to-Y3
70
120
4 PLLs switching, Y2-to-Y9
120
170
1 PLL switching, Y2-to-Y3
90
140
4 PLLs switching, Y2-to-Y9
130
190
tjit(cc)
Cycle-to-cycle jitter (2) (3)
tjit(per)
Peak-to-peak period
jitter (2) (3)
tsk(o)
Output skew (4)
odc
Output duty cycle (5)
fOUT = 50 MHz, Y1-to-Y3
ns
ns
60
fOUT = 50 MHz, Y2-to-Y5 or Y6-to-Y9
V
ps
ps
ps
160
fVCO = 100 MHz, Pdiv = 1
45%
55%
SDA AND SCL
VIK
SCL and SDA input clamp
voltage
VDD = 1.7 V, II = –18 mA
–1.2
V
IIH
SCL and SDA input current
VI = VDD, VDD = 1.9 V
±10
µA
VIH
SDA/SCL input high
voltage (6)
0.7 × VDD
VIL
SDA/SCL input low voltage
VOL
SDA low-level output voltage
IOL = 3 mA, VDD = 1.7 V
CI
SCL/SDA input capacitance
VI = 0 V or VDD
(6)
V
(6)
0.3 × VDD
3
V
0.2 × VDD
V
10
pF
SDA and SCL pins are 3.3-V tolerant.
7.6 EEPROM Specification
MIN
EEcyc
Programming cycles of EEPROM
EEret
Data retention
8
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TYP
MAX
UNIT
1000
cycles
10
years
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SCAS844F – AUGUST 2007 – REVISED OCTOBER 2016
7.7 Timing Requirements: CLK_IN
MIN
f(CLK)
LVCMOS clock input frequency
tr / tf
Rise and fall time CLK signal (20% to 80%)
dutyCLK
Duty cycle CLK at VDD / 2
NOM
MAX
PLL bypass mode
0
160
PLL mode
8
160
3
40%
UNIT
MHz
ns
60%
7.8 Timing Requirements: SDA/SCL
over operating free-air temperature range (unless otherwise noted; see Figure 14)
MIN
NOM
MAX
Standard mode
0
100
Fast mode
0
400
f(SCL)
SCL clock frequency
tsu(START)
START setup time (SCL high before Standard mode
SDA low)
Fast mode
th(START)
START hold time (SCL low after
SDA low)
tw(SCLL)
SCL low-pulse duration
tw(SCLH)
SCL high-pulse duration
th(SDA)
SDA hold time (SDA valid after SCL Standard mode
low)
Fast mode
0
3.45
0
0.9
tsu(SDA)
SDA setup time
Standard mode
250
Fast mode
100
tr
SCL/SDA input rise time
tf
SCL/SDA input fall time
tsu(STOP)
STOP setup time
tBUF
Bus free time between a STOP and
START condition
Standard mode
4.7
4
0.6
Standard mode
4.7
Fast mode
1.3
Standard mode
Fast mode
µs
µs
4
µs
0.6
Standard mode
300
300
Standard mode
4
Fast mode
0.6
Standard mode
4.7
Fast mode
1.3
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µs
ns
1000
Fast mode
kHz
µs
0.6
Fast mode
UNIT
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ns
µs
µs
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7.9 Typical Characteristics
100
90
35
VDD = 1.8 V
4 PLL on
70
25
3 PLL on
60
3 outputs on
IDDOUT - mA
IDD - Supply Current - mA
30
80
2 PLL on
1 PLL on
50
all PLL off
40
VDD = 1.8 V,
VDDOUT = 3.3 V,
9 outputs on
7 outputs on
No Load
5 outputs on
30
20
15
1 output on
all outputs off
10
20
5
10
0
10
60
110
160
PLL - Frequency - MHz
0
10
210
Figure 1. CDCEx949 Supply Current vs PLL Frequency
30
50 70 90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 2. CDCE949 Output Current vs Output Frequency
12
10
VDD = 1.8 V,
VDDOUT = 1.8 V,
No Load
9 outputs on
7 outputs on
5 outputs on
3 outputs on
IDDOUT - mA
8
1 output on
6
all outputs off
4
2
0
10
30
50
70
90
110
130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 3. CDCEL949 Output Current vs Output Frequency
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8 Parameter Measurement Information
Copyright © 2016, Texas Instruments Incorporated
Figure 4. Test Load
CDCE949
CDCEL949
LVCMOS
Typical Driver
Impedance
~ 32 W
LVCMOS
Series
Termination
~ 18 W
Line Impedance
Zo = 50 W
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Figure 5. Test Load for 50-Ω Board Environment
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9 Detailed Description
9.1 Overview
The CDCE949 and CDCEL949 devices are modular PLL-based, low-cost, high-performance, programmable
clock synthesizers, multipliers, and dividers. They generate up to nine output clocks from a single input
frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using one of the
four integrated configurable PLLs.
The CDCEx949 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL949 and 2.5 V to 3.3 V for
CDCE949.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.
Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control
signal, that is, the PWM signal.
The deep M/N divider ratio allows the generation of 0-ppm audio and video, networking (WLAN, Bluetooth,
Ethernet, GPS), or Interface (USB, IEEE1394, memory stick) clocks from a reference input frequency such as
27 MHz.
All PLLs support spread-spectrum clocking (SSC). SSC can be center-spread or down-spread clocking. This is a
common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.
The device supports non-volatile EEPROM programming for easy customization of the device to the application.
It is preset to a factory-default configuration (see Default Device Setting). It can be reprogrammed to a different
application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings
are programmable through the SDA and SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including
frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing
between low level or 3-state for the output-disable function.
The CDCEx949 operates in a 1.8-V environment. It operates within a temperature range of –40°C to 85°C.
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9.2 Functional Block Diagram
VDD
VDDOUT
GND
LV
CMOS
Y1
M2
LV
CMOS
Y2
M3
LV
CMOS
Y3
M4
LV
CMOS
Y4
M5
LV
CMOS
Y5
M6
LV
CMOS
Y6
M7
LV
CMOS
Y7
M8
LV
CMOS
Y8
LV
CMOS
Y9
Pdiv1
M1
Xin/CLK
M9
Input Clock
Vctr
10-Bit
VCXO
XO
Pdiv2
with SSC
Xout
MUX1
PLL 1
LVCMOS
7-Bit
Pdiv3
PLL Bypass
EEPROM
Programming
and
SDA/SCL
Register
Pdiv4
PLL 2
with SSC
MUX2
S0
S1/SDA
S2/SCL
7-Bit
Pdiv6
MUX3
PLL 3
7-Bit
Pdiv7
7-Bit
PLL Bypass
Pdiv8
MUX4
PLL 4
with SSC
Pdiv5
7-Bit
PLL Bypass
with SSC
7-Bit
7-Bit
Pdiv9
PLL Bypass
7-Bit
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9.3 Feature Description
9.3.1 Control Terminal Setting
The CDCEx949 has three user-definable control terminals (S0, S1, and S2) which allow external control of
device settings. They can be programmed to any of the following setting:
• Spread spectrum clocking selection → spread type and spread amount selection
• Frequency selection → switching between any of two user-defined frequencies
• Output state selection → output configuration and power down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
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Feature Description (continued)
Table 1. Control Terminal Definition
Output Y1 and Power Down Selection
Y1 SETTING
Output Y8/Y9 Selection
SSC Selection
PLL Frequency Selection
PLL4 SETTING
Output Y6/Y7 Selection
SSC Selection
PLL Frequency Selection
PLL3 SETTING
Output Y4/Y5 Selection
PLL Frequency Selection
PLL2 SETTING
Output Y2/Y3 Selection
SSC Selection
PLL Frequency Selection
Control
Function
PLL1 SETTING
SSC Selection
EXTERNAL
CONTROL
BITS
Table 2. PLLx Setting (Can Be Selected for Each PLL Individual)
SSC SELECTION (CENTER/DOWN) (1)
CENTER
DOWN
0
SSCx [3-bits]
0
0
0% (off)
0% (off)
0
0
1
±0.25%
–0.25%
0
1
0
±0.5%
–0.5%
0
1
1
±0.75%
–0.75%
1
0
0
±1%
–1%
1
0
1
±1.25%
–1.25%
1
1
0
±1.5%
–1.5%
1
1
1
±2%
–2%
FREQUENCY SELECTION (2)
FSx
FUNCTION
0
Frequency0
1
Frequency1
OUTPUT SELECTION (3) (Y2 ... Y9)
(1)
(2)
(3)
YxYx
FUNCTION
0
State0
1
State1
Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register
Frequency0 and Frequency1 can be any frequency within the specified fVCO range
State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
3-state, low, or active
Table 3. Y1 Setting (1)
Y1 SELECTION
(1)
14
Y1
FUNCTION
0
State 0
1
State 1
State0 and State1 are user definable in Generic Configuration
Register and can be power down, 3-state, low, or active.
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S1/SDA and S2/SCL pins of the CDCEx949 are dual function pins. In default configuration they are defined as
SDA/SCL for the serial interface. They can be programmed as control-pins (S1/S2) by setting the relevant bits in
the EEPROM. Note that the changes to the Control register (Bit [6] of Byte [02]) have no effect until they are
written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).
S0 is not a multi-use pin, it is a control pin only.
9.3.2 Default Device Setting
The internal EEPROM of CDCEx949 is preconfigured as shown in Figure 6 (the input frequency is passed
through to the output as a default). This allows the device to operate in default mode without the extra production
step of program it. The default setting appears after power is supplied or after power-down or power-up
sequence until it is re-programmed by the user to a different application configuration. A new register setting is
programmed through the serial SDA/SCL Interface.
VDD
Vddout
GND
PLL 2
power down
Pdiv4 = 1
Pdiv5 = 1
PLL Bypass
PLL3
LV
CMOS
Y4 = 27 MHz
LV
CMOS
Y5 = 27 MHz
Pdiv6 = 1
LV
CMOS
Y6 = 27 MHz
LV
CMOS
Y7 = 27 MHz
MUX3
power down
M2
SCL
M3
SDA
Programming Bus
Y3 = 27 MHz
MUX2
“0” = outputs 3-State
LV
CMOS
M4
Programming
and
SDA/SCA
Register
S0
Pdiv3 = 1
PLL Bypass
EEPROM
“1” = outputs enabled
Pdiv2 = 1
MUX1
Xout
Y2 = 27 MHz
M5
PLL1
LV
CMOS
Pdiv1 =1
X-tal
power down
Y1 = 27MHz
M6
27 MHz
Crystal
LV
CMOS
M7
M1
Input Clock
Xin
Pdiv7 = 1
PLL Bypass
Figure 6. Default Device Setting
Table 4 shows the factory default setting for the Control Terminal Register (external control pins). In normal
operation, all 8 register settings are available, but in the default configuration only the first two settings (0 and 1)
can be selected with S0, as S1 and S2 configured as programming pins in default mode.
Table 4. Factory Default Setting for Control Terminal Register
Y1
EXTERNAL
CONTROL PINS (1)
PLL1 SETTING
PLL2 SETTING
PLL3 SETTING
PLL3 SETTING
OUTPUT
SELECT
FREQ.
SELECT
SSC
SEL.
OUTPUT
SELECT
FREQ.
SELECT
SSC
SEL.
OUTPUT
SELECT
FREQ.
SELECT
SSC
SEL.
OUTPUT
SELECT
FREQ.
SELECT
SSC
SEL.
OUTPUT
SELECT
S2
S1
S0
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
FS3
SSC3
Y6Y7
FS4
SSC4
Y8Y9
SCL
(I2C)
SDA
(I2C)
0
3-state
fVCO1_0
off
3-state
fVCO2_0
off
3-state
fVCO3_0
off
3-state
fVCO4_0
off
3-state
SCL
(I2C)
SDA
(I2C)
1
enabled
fVCO1_0
off
enabled
fVCO2_0
off
enabled
fVCO3_0
off
enabled
fVCO4_0
off
enabled
(1)
In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any
control-pin function but they are internally interpreted as if S1 = 0 and S2 = 0. However, S0 is a control-pin which in the default mode
switches all outputs ON or OFF (as previously predefined).
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9.3.3 SDA/SCL Serial Interface
The CDCEx949 operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the popular
SMBus or I2C Bus specification. It operates in the standard-mode transfer (up to 100 kbps) and fast-mode
transfer (up to 400 kbps) and supports 7-bit addressing.
The S1/SDA and S2/SCL pins of the CDCEx949 are dual function pins. In the default configuration they are used
as SDA/SCL serial programming interface. They can be re-programmed as general-purpose control pins, S1 and
S2, by changing the corresponding EEPROM setting, Byte 02, Bit [6].
P
S
tw(SCLL)
Bit 7 (MSB)
tw(SCLH)
Bit 6
tr
Bit 0 (LSB)
A
P
tf
VIH
SCL
VIL
tsu(START)
th(START)
tsu(SDA)
th(SDA)
t(BUS)
tsu(STOP)
tf
tr
VIH
SDA
VIL
Figure 7. Timing Diagram for SDA/SCL Serial Control Interface
9.3.4 Data Protocol
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of
Bytes read-out are defined by Byte Count in the Generic Configuration Register. At Block Read instruction all
bytes defined in the Byte Count has to be readout to correctly finish the read cycle.
Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to
each transferred byte independent of whether this is a Byte Write or a Block Write sequence.
If the EEPROM Write Cycle is initiated, the internal SDA register contents are written into the EEPROM. During
this write cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can
be read during the programming sequence (Byte Read or Block Read). The programming status can be
monitored by reading EEPIP, Byte 01–Bit [6].
The offset of the indexed byte is encoded in the command code, as described in Table 5.
Table 5. Slave Receiver Address (7 Bits)
A6
A5
A4
A3
A2
A1 (1)
A0 (1)
R/W
CDCEx913
1
1
0
0
1
0
1
1/0
CDCEx925
1
1
0
0
1
0
0
1/0
CDCEx937
1
1
0
1
1
0
1
1/0
CDCEx949
1
1
0
1
1
0
0
1/0
DEVICE
(1)
Address bits A0 and A1 are programmable through the SDA/SCL bus (Byte 01, Bit [1:0]). This allows addressing up to 4 devices
connected to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.
9.4 Device Functional Modes
9.4.1 SDA/SCL Hardware Interface
Figure 8 shows how the CDCEx949 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple
devices can be connected to the bus but the speed may need to be reduced (400 kHz is the maximum) if many
devices are connected.
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Device Functional Modes (continued)
Note that the pullup resistor value (RP) depends on the supply voltage, bus capacitance and number of
connected devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at
VOLmax = 0.4 V for the output stages (for more details, see SMBus or I2C Bus specification).
CDCE949
CDCEL949
RP
RP
Master
Slave
SDA
SCL
CBUS
CBUS
Copyright © 2016, Texas Instruments Incorporated
Figure 8. SDA/SCL Hardware Interface
9.5 Programming
Table 6. Command Code Definition
BIT
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
7
(6:0)
Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.
1
S
7
Slave Address
1
1
R/W A
LSB
MSB
MSB
S
Start Condition
Sr
Repeated Start Condition
8
Data Byte
1
A
1
P
LSB
R/W 1 = Read (Rd) from CDCE9xx device; 0 = Write (Wr) to the CDCE9xxx
A
Acknowledg (ACK = 0 and NACK =1)
P
Stop Condition
Master to Slave Transmission
Slave to Master Transmission
Figure 9. Generic Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
CommandCode
1
A
8
Data Byte
1
A
1
P
Figure 10. Byte Write Protocol
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S
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7
Slave Address
1
Wr
1
A
8
Data Byte
1
A
1
P
8
CommandCode
1
A
7
Slave Address
1
Sr
1
Rd
1
A
1
A
1
P
Figure 11. Byte Read Protocol
1
S
7
Slave Address
1
Wr
8
Data Byte 0
1
A
1
A
1
A
8
CommandCode
8
Data Byte 1
1
A
1
A
8
Byte Count = N
8
Data Byte N-1
…
NOTE: Data Byte 0 Bits [7:0] is reserved for Revision Code and Vendor Identification. Also it is used for internal test purpose
and must not be overwritten.
Figure 12. Block Write Programming
1
S
7
Slave Address
1
Wr
8
Byte Count N
1
A
1
A
1
A
8
CommandCode
8
Data Byte 0
1
A
1
Sr
…
7
Slave Address
1
Rd
1
A
8
Data Byte N-1
1
A
1
P
Figure 13. Block Read Protocol
P
Bit 7 (MSB)
S
tw(SCLL)
Bit 6
tw(SCLH)
tr
Bit 0 (LSB)
A
P
tf
VIH
SCL
VIL
tSU(START)
t(BUS)
th(START)
t
SU(SDA)
tr
t
tSU(STOP)
h(SDA)
tf
VIH
SDA
VIL
Figure 14. Timing Diagram for the SDA/SCL Serial Control Interface
9.6 Register Maps
9.6.1 SDA/SCL Configuration Registers
The clock input, control pins, PLLs, and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCEx949. All settings can be manually written to the
device through the SDA/SCL bus, or are easily programmable by using the TI Pro Clock software. TI Pro Clock
software allows the user to quickly make all settings and automatically calculates the values for optimized
performance at lowest jitter.
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Table 7. SDA/SCL Registers
ADDRESS OFFSET
REGISTER DESCRIPTION
TABLE
00h
Generic configuration register
Table 9
10h
PLL1 configuration register
Table 10
20h
PLL2 configuration register
Table 11
30h
PLL3 configuration register
Table 12
40h
PLL4 configuration register
Table 13
The grey-highlighted Bits described in the configuration registers tables on the following pages, belong to the
Control Pin Register. The user can predefine up to eight different control settings. These settings can then be
selected by the external control pins, S0, S1, and S2 (see Control Terminal Setting).
Table 8. Configuration Register, External Control Pins
EXTERNAL
CONTROL
PINS
S2 S1 S0
Y1
OUTPUT
SELECT
PLL1 SETTING
FREQ
SELECT
SSC
SELECT
PLL2 SETTING
OUTPUT
SELECT
FREQ
SELECT
SSC
SELECT
PLL3 SETTING
OUTPUT
SELECT
FREQ
SELECT
SSC
SELECT
PLL4 SETTING
OUTPUT
SELECT
FREQ
SELECT
SSC
SELECT
OUTPUT
SELECT
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
FS3
SSC3
Y6Y7
FS4
SSC4
Y8Y9
0
0
0
Y1_0
FS1_0
SSC1_0
Y2Y3_0
FS2_0
SSC2_0
Y4Y5_0
FS3_0
SSC3_0
Y6Y7_0
FS4_0
SSC4_0
Y8Y9_0
0
0
1
Y1_1
FS1_1
SSC1_1
Y2Y3_1
FS2_1
SSC2_1
Y4Y5_1
FS3_1
SSC3_1
Y6Y7_1
FS4_1
SSC4_1
Y8Y9_1
0
1
0
Y1_2
FS1_2
SSC1_2
Y2Y3_2
FS2_2
SSC2_2
Y4Y5_2
FS3_2
SSC3_2
Y6Y7_2
FS4_2
SSC4_2
Y8Y9_2
0
1
1
Y1_3
FS1_3
SSC1_3
Y2Y3_3
FS2_3
SSC2_3
Y4Y5_3
FS3_3
SSC3_3
Y6Y7_3
FS4_3
SSC4_3
Y8Y9_3
1
0
0
Y1_4
FS1_4
SSC1_4
Y2Y3_4
FS2_4
SSC2_4
Y4Y5_4
FS3_4
SSC3_4
Y6Y7_4
FS4_4
SSC4_4
Y8Y9_4
1
0
1
Y1_5
FS1_5
SSC1_5
Y2Y3_5
FS2_5
SSC2_5
Y4Y5_5
FS3_5
SSC3_5
Y6Y7_5
FS4_5
SSC4_5
Y8Y9_5
1
1
0
Y1_6
FS1_6
SSC1_6
Y2Y3_6
FS2_6
SSC2_6
Y4Y5_6
FS3_6
SSC3_6
Y6Y7_6
FS4_6
SSC4_6
Y8Y9_6
1
1
1
Y1_7
FS1_7
SSC1_7
Y2Y3_7
FS2_7
SSC2_7
Y4Y5_7
FS3_7
SSC3_7
Y6Y7_7
FS4_7
SSC4_7
Y8Y9_7
04h
13h
10h-12h
15h
23h
20h-22h
25h
33h
30h-32h
35h
43h
40h-42h
45h
Addr.
Offset (1)
(1)
Address Offset refers to the byte address in the Configuration Register on following pages.
Table 9. Generic Configuration Register
OFFSET
00h
01h
(1)
(2)
(3)
(4)
(5)
(1)
ACRONYM
DEFAULT (3)
7
E_EL
xb
Device Identification (read only): ‘1’ is CDCE949 (3.3V), ‘0’ is CDCEL949 (1.8V)
6:4
RID
Xb
Revision Identification Number (read only)
3:0
VID
1h
Vendor Identification Number (read only)
7
–
0b
Reserved - always write 0
6
EEPIP
0b
EEPROM Programming
Status (4): (read only)
0 – EEPROM programming is completed
1 – EEPROM is in programming mode
5
EELOCK
0b
Permanently Lock EEPROM
Data (5):
0 – EEPROM is not locked
1 – EEPROM is permanently locked
4
PWDN
0b
3:2
INCLK
00b
1:0
SLAVE_ADR
00b
BIT
(2)
DESCRIPTION
Device power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – device active (all PLLs and all outputs are enabled)
1 – device power down (all PLLs in power down and all outputs in 3-State)
Input clock selection:
00 – X-tal
01 – VCXO
10 – LVCMOS
11 – reserved
Programmable Address Bits A0 and A1 of the Slave Receiver Address
Writing data beyond 50h may adversely affect device function.
All data is transferred MSB-first.
Unless custom setting is used.
During EEPROM programming, no data is allowed to be sent to the device through the SDA/SCL bus until the programming sequence is
completed. Data, however, can be read during the programming sequence (Byte Read or Block Read).
If this bit is set high in the EEPROM, the actual data in the EEPROM is permanently locked, and no further programming is possible.
Data, however can still be written through the SDA/SCL bus to the internal register to change device function on the fly. But new data
can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM
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Table 9. Generic Configuration Register (continued)
OFFSET
(1)
02h
BIT
(2)
7
ACRONYM
DEFAULT (3)
M1
1b
DESCRIPTION
Clock source selection for output Y1:
0 – input clock
1 – PLL1 clock
Operation mode selection for pin 22/23 (6)
6
SPICON
0b
5:4
Y1_ST1
11b
3:2
Y1_ST0
01b
1:0
Pdiv1 [9:8]
03h
7:0
Pdiv1 [7:0]
04h
7
Y1_7
0b
6
Y1_6
0b
5
Y1_5
0b
4
Y1_4
0b
3
Y1_3
0b
2
Y1_2
0b
1
Y1_1
1b
0
Y1_0
0b
001h
05h
0 – serial programming interface SDA (pin 23) and SCL (pin 22)
1 – control pins S1 (pin 23) and S2 (pin 22)
Y1-State0/1 Definition (applies to Y1_ST1 and Y1_ST0)
00 –
01 –
10 –
11 –
device power down (all PLLs in power down and all outputs in 3-state)
Y1 disabled to 3-state
Y1 disabled to low
Y1 enabled (normal operation)
10-Bit Y1-Output-Divider
Pdiv1:
Y1_x State Selection (7)
0 – State0 (predefined by Y1-State0 Definition [Y1_ST0])
1 – State1 (predefined by Y1-State1 Definition [Y1_ST1])
Crystal load capacitor
selection (8):
7:3
XCSEL
0 – divider reset and stand-by
1-to-1023 – divider value
0Ah
00h → 0 pF
01h → 1 pF
02h → 2 pF
14h-to-1Fh → 20 pF
Vctr
Xin
20pF
i.e.
XCSEL = 10pF
XO
Xout
06h
(6)
(7)
(8)
(9)
20
20pF
2:0
—
0b
Reserved - do not write others than 0
7:1
BCOUNT
50h
7-Bit Byte Count (Defines the number of Bytes which is sent from this device at the next Block Read
transfer; all bytes must be read out to correctly finish the read cycle.)
0
EEWRITE
0b
0 – no EEPROM write cycle
1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM)
—
—
0h
Reserved – do not write others than 0
Initiate EEPROM Write Cycle(4)
07h-0Fh
VCXO
(9)
Selection of control-pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are
no longer available. However, if VDDOUT is forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins
(SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.
These are the bits of the Control Pin Register. The user can predefine up to eight different control settings. These settings can then be
selected by the external control pins, S0, S1, and S2.
The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors must be used only to do a
fine adjustment of CL by few pF. The value of CL can be programmed with a resolution of 1 pF for a total crystal load range of 0 pF to 20
pF. For CL > 20 pF use additional external capacitors. Also, the device input capacitance must be considered; this adds 1.5 pF (6 pF, 2
pF) to the selected CL. For more information about VCXO configuration and crystal recommendations, see VCXO Application Guideline
for CDCE(L)9xx Family (SCAA085).
NOTE: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are written into the EEPROM.
The EEWRITE cycle is initiated by the rising edge of the EEWRITE-Bit. A static level high does not trigger an EEPROM WRITE cycle.
The EEWRITE-Bit must be reset low after the programming is completed. The programming status can be monitored by readout EEPIP.
If EELOCK is set high, no EEPROM programming is possible.
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Table 10. PLL1 Configuration Register
OFFSET
10h
11h
12h
13h
14h
15h
16h
17h
(1)
(2)
(3)
(4)
(1)
ACRONYM
DEFAULT (3)
7:5
SSC1_7 [2:0]
000b
4:2
SSC1_6 [2:0]
000b
1:0
SSC1_5 [2:1]
7
SSC1_5 [0]
6:4
SSC1_4 [2:0]
000b
3:1
SSC1_3 [2:0]
000b
0
SSC1_2 [2]
7:6
SSC1_2 [1:0]
5:3
SSC1_1 [2:0]
000b
2:0
SSC1_0 [2:0]
000b
7
FS1_7
0b
6
FS1_6
0b
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
7
MUX1
1b
6
M2
1b
5:4
M3
10b
3:2
Y2Y3_ST1
11b
1:0
Y2Y3_ST0
01b
7
Y2Y3_7
0b
6
Y2Y3_6
0b
5
Y2Y3_5
0b
4
Y2Y3_4
0b
3
Y2Y3_3
0b
2
Y2Y3_2
0b
1
Y2Y3_1
1b
0
Y2Y3_0
0b
7
SSC1DC
0b
6:0
Pdiv2
01h
7
—
0b
6:0
Pdiv3
01h
BIT
(2)
000b
000b
DESCRIPTION
SSC1: PLL1 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS1_x: PLL1 Frequency Selection(4)
0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
PLL1 Multiplexer:
0 – PLL1
1 – PLL1 Bypass (PLL1 is in power down)
Output Y2 Multiplexer:
0 – Pdiv1
1 – Pdiv2
Output Y3 Multiplexer:
00 –
01 –
10 –
11 –
Y2, Y3State0/1definition:
00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State (PLL1 on)
10–Y2/Y3 disabled to low (PLL1 on)
11 – Y2/Y3 enabled (normal operation, PLL1 on)
Pdiv1-Divider
Pdiv2-Divider
Pdiv3-Divider
reserved
Y2Y3_x Output State Selection(4)
0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
PLL1 SSC down/center selection:
0 – down
1 – center
7-Bit Y2-Output-Divider Pdiv2:
0 – reset and stand-by
1-to-127 – divider value
Reserved – do not write others than 0
7-Bit Y3-Output-Divider Pdiv3:
0 – reset and stand-by
1-to-127 – divider value
Writing data beyond 50h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 10. PLL1 Configuration Register (continued)
OFFSET
(1)
BIT
(2)
ACRONYM
DEFAULT (3)
18h
7:0
PLL1_0N [11:4
19h
7:4
PLL1_0N [3:0]
3:0
PLL1_0R [8:5]
7:3
PLL1_0R[4:0]
2:0
PLL1_0Q [5:3]
7:5
PLL1_0Q [2:0]
4:2
PLL1_0P [2:0]
010b
1:0
VCO1_0_RANGE
00b
1Ch
7:0
PLL1_1N [11:4]
1Dh
7:4
PLL1_1N [3:0]
3:0
PLL1_1R [8:5]
7:3
PLL1_1R[4:0]
2:0
PLL1_1Q [5:3]
7:5
PLL1_1Q [2:0]
4:2
PLL1_1P [2:0]
010b
1:0
VCO1_1_RANGE
00b
1Ah
1Bh
004h
DESCRIPTION
PLL1_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information, see PLL Frequency Planning)
000h
10h
fVCO1_0 range selection:
1Eh
1Fh
004h
fVCO1_0 < 125 MHz
125 MHz ≤ fVCO1_0 < 150 MHz
150 MHz ≤ fVCO1_0 < 175 MHz
fVCO1_0 ≥ 175 MHz
PLL1_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information, see PLL Frequency Planning).
000h
10h
fVCO1_1 range selection:
(5)
00 –
01 –
10 –
11 –
00 –
01 –
10 –
11 –
fVCO1_1 < 125 MHz
125 MHz ≤ fVCO1_1 < 150 MHz
150 MHz ≤ fVCO1_1 < 175 MHz
fVCO1_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
Table 11. PLL2 Configuration Register
OFFSET (1)
BIT (2)
ACRONYM
DEFAULT (3)
20h
7:5
SSC2_7 [2:0]
000b
4:2
SSC2_6 [2:0]
000b
1:0
SSC2_5 [2:1]
7
SSC2_5 [0]
6:4
SSC2_4 [2:0]
000b
3:1
SSC2_3 [2:0]
000b
0
SSC2_2 [2]
7:6
SSC2_2 [1:0]
5:3
SSC2_1 [2:0]
000b
2:0
SSC2_0 [2:0]
000b
7
FS2_7
0b
6
FS2_6
0b
5
FS2_5
0b
4
FS2_4
0b
3
FS2_3
0b
2
FS2_2
0b
1
FS2_1
0b
0
FS2_0
0b
21h
22h
23h
(1)
(2)
(3)
(4)
22
000b
000b
DESCRIPTION
SSC2: PLL2 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS2_x: PLL2 Frequency Selection(4)
0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
Writing data beyond 50h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 11. PLL2 Configuration Register (continued)
OFFSET
24h
(1)
BIT
(2)
ACRONYM
DEFAULT (3)
7
MUX2
1b
6
M4
1b
5:4
M5
10b
3:2
Y4Y5_ST1
11b
1:0
Y4Y5_ST0
01b
7
Y4Y5_7
0b
6
Y4Y5_6
0b
5
Y4Y5_5
0b
4
Y4Y5_4
0b
3
Y4Y5_3
0b
2
Y4Y5_2
0b
1
Y4Y5_1
1b
0
Y4Y5_0
0b
7
SSC2DC
0b
6:0
Pdiv4
01h
7
—
0b
6:0
Pdiv5
01h
28h
7:0
PLL2_0N [11:4
29h
7:4
PLL2_0N [3:0]
3:0
PLL2_0R [8:5]
7:3
PLL2_0R[4:0]
2:0
PLL2_0Q [5:3]
7:5
PLL2_0Q [2:0]
4:2
PLL2_0P [2:0]
010b
1:0
VCO2_0_RANGE
00b
2Ch
7:0
PLL2_1N [11:4]
2Dh
7:4
PLL2_1N [3:0]
3:0
PLL2_1R [8:5]
7:3
PLL2_1R[4:0]
2:0
PLL2_1Q [5:3]
7:5
PLL2_1Q [2:0]
4:2
PLL2_1P [2:0]
010b
1:0
VCO2_1_RANGE
00b
25h
26h
27h
2Ah
2Bh
004h
DESCRIPTION
PLL2 Multiplexer:
0 – PLL2
1 – PLL2 Bypass (PLL2 is in power down)
Output Y4 Multiplexer:
0 – Pdiv2
1 – Pdiv4
Output Y5 Multiplexer:
00 –
01 –
10 –
11 –
Y4, Y5State0/1definition:
00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State (PLL2 on)
10–Y4/Y5 disabled to low (PLL2 on)
11 – Y4/Y5 enabled (normal operation, PLL2 on)
Pdiv2-Divider
Pdiv4-Divider
Pdiv5-Divider
reserved
Y4Y5_x Output State Selection(4)
0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
PLL2 SSC down/center selection:
0 – down
1 – center
7-Bit Y4-Output-Divider Pdiv4:
0 – reset and stand-by
1-to-127 – divider value
Reserved – do not write others than 0
7-Bit Y5-Output-Divider Pdiv5:
PLL2_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information, see PLL Frequency Planning).
000h
10h
fVCO2_0 range selection:
2Eh
2Fh
004h
00 –
01 –
10 –
11 –
fVCO2_0 < 125 MHz
125 MHz ≤ fVCO2_0 < 150 MHz
150 MHz ≤ fVCO2_0 < 175 MHz
fVCO2_0 ≥ 175 MHz
PLL2_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information, see PLL Frequency Planning).
000h
10h
fVCO2_1 range selection:
(5)
0 – reset and stand-by
1-to-127 – divider value
00 –
01 –
10 –
11 –
fVCO2_1 < 125 MHz
125 MHz ≤ fVCO2_1 < 150 MHz
150 MHz ≤ fVCO2_1 < 175 MHz
fVCO2_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
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Table 12. PLL3 Configuration Register
OFFSET
30h
31h
32h
33h
34h
35h
36h
37h
(1)
(2)
(3)
(4)
24
(1)
ACRONYM
DEFAULT (3)
7:5
SSC3_7 [2:0]
000b
4:2
SSC3_6 [2:0]
000b
1:0
SSC3_5 [2:1]
7
SSC3_5 [0]
6:4
SSC3_4 [2:0]
000b
3:1
SSC3_3 [2:0]
000b
0
SSC3_2 [2]
7:6
SSC3_2 [1:0]
5:3
SSC3_1 [2:0]
000b
2:0
SSC3_0 [2:0]
000b
7
FS3_7
0b
6
FS3_6
0b
5
FS3_5
0b
4
FS3_4
0b
3
FS3_3
0b
2
FS3_2
0b
1
FS3_1
0b
0
FS3_0
0b
7
MUX3
1b
6
M6
1b
5:4
M7
10b
3:2
Y6Y7_ST1
11b
1:0
Y6Y7_ST0
01b
7
Y6Y7_7
0b
6
Y6Y7_6
0b
5
Y6Y7_5
0b
4
Y6Y7_4
0b
3
Y6Y7_3
0b
2
Y6Y7_2
0b
1
Y6Y7_1
1b
0
Y6Y7_0
0b
7
SSC3DC
0b
6:0
Pdiv6
01h
7
—
0b
6:0
Pdiv7
01h
BIT
(2)
000b
000b
DESCRIPTION
SSC3: PLL3 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS3_x: PLL3 Frequency Selection(4)
0 – fVCO3_0 (predefined by PLL3_0 – Multiplier/Divider value)
1 – fVCO3_1 (predefined by PLL3_1 – Multiplier/Divider value)
PLL3 Multiplexer:
0 – PLL3
1 – PLL3 Bypass (PLL3 is in power down)
Output Y6 Multiplexer:
0 – Pdiv4
1 – Pdiv6
Output Y7 Multiplexer:
00 –
01 –
10 –
11 –
Y6, Y7State0/1definition:
00 – Y6/Y7 disabled to 3-State (PLL3 is in power down)
01 – Y6/Y7 disabled to 3-State (PLL3 on)
10 –Y6/Y7 disabled to low (PLL3 on)
11 – Y6/Y7 enabled (normal operation, PLL3 on)
Pdiv4-Divider
Pdiv6-Divider
Pdiv7-Divider
reserved
Y6Y7_x Output State Selection(4)
0 – state0 (predefined by Y6Y7_ST0)
1 – state1 (predefined by Y6Y7_ST1)
PLL3 SSC down/center selection: 0 – down
1 – center
7-Bit Y6-Output-Divider Pdiv6:
0 – reset and stand-by
1-to-127 – divider value
Reserved – do not write others than 0
7-Bit Y7-Output-Divider Pdiv7:
0 – reset and stand-by
1-to-127 – divider value
Writing data beyond 50h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 12. PLL3 Configuration Register (continued)
OFFSET
(1)
BIT
(2)
ACRONYM
DEFAULT (3)
38h
7:0
PLL3_0N [11:4
39h
7:4
PLL3_0N [3:0]
3:0
PLL3_0R [8:5]
7:3
PLL3_0R[4:0]
2:0
PLL3_0Q [5:3]
7:5
PLL3_0Q [2:0]
4:2
PLL3_0P [2:0]
010b
1:0
VCO3_0_RANGE
00b
3Ch
7:0
PLL3_1N [11:4]
3Dh
7:4
PLL3_1N [3:0]
3:0
PLL3_1R [8:5]
7:3
PLL3_1R[4:0]
2:0
PLL3_1Q [5:3]
7:5
PLL3_1Q [2:0]
4:2
PLL3_1P [2:0]
010b
1:0
VCO3_1_RANGE
00b
3Ah
3Bh
004h
DESCRIPTION
PLL3_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO3_0
(for more information, see PLL Frequency Planning).
000h
10h
fVCO3_0 range selection:
3Eh
3Fh
004h
fVCO3_0 < 125 MHz
125 MHz ≤ fVCO3_0 < 150 MHz
150 MHz ≤ fVCO3_0 < 175 MHz
fVCO3_0 ≥ 175 MHz
PLL3_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO3_1
(for more information, see PLL Frequency Planning).
000h
10h
fVCO3_1 range selection:
(5)
00 –
01 –
10 –
11 –
00 –
01 –
10 –
11 –
fVCO3_1 < 125 MHz
125 MHz ≤ fVCO3_1 < 150 MHz
150 MHz ≤ fVCO3_1 < 175 MHz
fVCO3_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
Table 13. PLL4 Configuration Register
OFFSET (1)
BIT (2)
ACRONYM
DEFAULT (3)
40h
7:5
SSC4_7 [2:0]
000b
4:2
SSC4_6 [2:0]
000b
1:0
SSC4_5 [2:1]
7
SSC4_5 [0]
6:4
SSC4_4 [2:0]
000b
3:1
SSC4_3 [2:0]
000b
0
SSC4_2 [2]
7:6
SSC4_2 [1:0]
5:3
SSC4_1 [2:0]
000b
2:0
SSC4_0 [2:0]
000b
7
FS4_7
0b
6
FS4_6
0b
5
FS4_5
0b
4
FS4_4
0b
3
FS4_3
0b
2
FS4_2
0b
1
FS4_1
0b
0
FS4_0
0b
41h
42h
43h
(1)
(2)
(3)
(4)
000b
000b
DESCRIPTION
SSC4: PLL4 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS4_x: PLL4 Frequency Selection(4)
0 – fVCO4_0 (predefined by PLL4_0 – Multiplier/Divider value)
1 – fVCO4_1 (predefined by PLL4_1 – Multiplier/Divider value)
Writing data beyond 50h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 13. PLL4 Configuration Register (continued)
OFFSET
44h
(1)
BIT
(2)
ACRONYM
DEFAULT (3)
7
MUX4
1b
6
M8
1b
5:4
M9
10b
3:2
Y8Y9_ST1
11b
1:0
Y8Y9_ST0
01b
7
Y8Y9_7
0b
6
Y8Y9_6
0b
5
Y8Y9_5
0b
4
Y8Y9_4
0b
3
Y8Y9_3
0b
2
Y8Y9_2
0b
1
Y8Y9_1
1b
0
Y8Y9_0
0b
7
SSC4DC
0b
6:0
Pdiv8
01h
7
—
0b
6:0
Pdiv9
01h
48h
7:0
PLL4_0N [11:4
49h
7:4
PLL4_0N [3:0]
3:0
PLL4_0R [8:5]
7:3
PLL4_0R[4:0]
2:0
PLL4_0Q [5:3]
7:5
PLL4_0Q [2:0]
4:2
PLL4_0P [2:0]
010b
1:0
VCO4_0_RANGE
00b
4Ch
7:0
PLL4_1N [11:4]
4Dh
7:4
PLL4_1N [3:0]
3:0
PLL4_1R [8:5]
7:3
PLL4_1R[4:0]
2:0
PLL4_1Q [5:3]
7:5
PLL4_1Q [2:0]
4:2
PLL4_1P [2:0]
010b
1:0
VCO4_1_RANGE
00b
45h
46h
47h
4Ah
4Bh
004h
DESCRIPTION
PLL4 Multiplexer:
0 – PLL4
1 – PLL4 Bypass (PLL4 is in power down)
Output Y8 Multiplexer:
0 – Pdiv6
1 – Pdiv8
Output Y9 Multiplexer:
00 –
01 –
10 –
11 –
Y8, Y9State0/1definition:
00 – Y8/Y9 disabled to 3-State (PLL4 is in power down)
01 – Y8/Y9 disabled to 3-State (PLL4 on)
10 –Y8/Y9 disabled to low (PLL4 on)
11 – Y8/Y9 enabled (normal operation, PLL4 on)
Y8Y9_x Output State Selection(4)
0 – state0 (predefined by Y8Y9_ST0)
1 – state1 (predefined by Y8Y9_ST1)
PLL4 SSC down/center selection: 0 – down
1 – center
7-Bit Y8-Output-Divider Pdiv8:
4Fh
7-Bit Y9-Output-Divider Pdiv9:
26
0 – reset and stand-by
1-to-127 – divider value
PLL4_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO4_0
(for more information, see PLL Frequency Planning).
000h
10h
004h
00 –
01 –
10 –
11 –
fVCO4_0 < 125 MHz
125 MHz ≤ fVCO4_0 < 150 MHz
150 MHz ≤ fVCO4_0 < 175 MHz
fVCO4_0 ≥ 175 MHz
PLL4_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO4_1
(for more information, see PLL Frequency Planning).
000h
10h
fVCO4_1 range selection:
(5)
0 – reset and stand-by
1-to-127 – divider value
Reserved – do not write others than 0
fVCO4_0 range selection:
4Eh
Pdiv6-Divider
Pdiv8-Divider
Pdiv9-Divider
reserved
00 –
01 –
10 –
11 –
fVCO4_1 < 125 MHz
125 MHz ≤ fVCO4_1 < 150 MHz
150 MHz ≤ fVCO4_1 < 175 MHz
fVCO4_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤7, 0 ≤ r ≤ 511, 0 < N < 4096
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The CDCEx949 device is an easy-to-use high-performance, programmable CMOS clock synthesizer. it can be
used as a crystal buffer, clock synthesizer with separate output supply pin. The CDCEx949 features an on-chip
loop filter and Spread-spectrum modulation. Programming can be done through SPI, pin-mode, or using on-chip
EEPROM. This section shows some examples of using CDCEx949 in various applications.
10.2 Typical Application
Figure 15 shows the use of the CDCEx949 devices for replacement of crystals and crystal oscillators on a
Gigabit Ethernet Switch application.
Crystals + Oscillators
1 x Crystal + 1 x Clock
Crystals:4
Oscillators: 2
Clock: None
Crystals: 1
Oscillators: None
Clock: 1
40 MHz
DP838xx
10/100 PHY
WiFi
25 MHz
DP838xx
10/100 PHY
CDCE(L)9xx
Clock
WiFi
25 MHz
100 MHz
25 MHz
FPGA
USB
Controller
FPGA
25 MHz
USB
Controller
48 MHz
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Figure 15. Crystal and Oscillator Replacement Example
10.2.1 Design Requirements
CDCEx949 supports spread spectrum clocking (SSC) with multiple control parameters:
• Modulation amount (%)
• Modulation frequency (>20 kHz)
• Modulation shape (triangular)
• Center spread / down spread (± or –)
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Typical Application (continued)
Figure 16. Modulation Frequency (fm) and Modulation Amount
10.2.2 Detailed Design Procedure
10.2.2.1 Spread Spectrum Clock (SSC)
Spread spectrum modulation is a method to spread emitted energy over a larger bandwidth. In clocking, spread
spectrum can reduce Electromagnetic Interference (EMI) by reducing the level of emission from clock distribution
network.
CDCS502 with a 25-MHz Crystal, FS = 1, Fout = 100 MHz, and 0%, ±0.5, ±1%, and ±2% SSC
Figure 17. Comparison Between Typical Clock Power Spectrum and Spread-Spectrum Clock
10.2.2.2 PLL Frequency Planning
At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCEx949 are calculated with Equation 1.
ƒ
N
ƒOUT = IN ´
Pdiv M
where
•
•
M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL
Pdiv (1 to 127) is the output divider
The target VCO frequency (ƒVCO) of each PLL is calculated with Equation 2.
N
ƒ VCO = ƒIN ´
M
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(1)
(2)
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Typical Application (continued)
The PLL internally operates as fractional divider and needs the following multiplier/divider settings:
• N
• P = 4 – int(log2N/M; if P < 0 then P = 0
• Q = int(N'/M)
• R = N′ – M × Q
where
N′ = N × 2P
N ≥ M;
80 MHz ≤ ƒVCO ≤ 230 MHz
16 ≤ Q ≤ 63
0≤P≤4
0 ≤ R ≤ 51
Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2
→ fOUT = 54 MHz
→ fOUT = 74.25 MHz
→ fVCO = 108 MHz
→ fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2
→ P = 4 – int(log25.5) = 4 – 2 = 2
2
→ N' = 4 × 2 = 16
→ N' = 11 × 22 = 44
→ Q = int(16) = 16
→ Q = int(22) = 22
→ R = 16 – 16 = 0
→ R = 44 – 44 = 0
The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.
10.2.2.3 Crystal Oscillator Start-Up
When the CDCEx949 is used as a crystal buffer, crystal oscillator start-up dominates the start-up time compared
to the internal PLL lock time. The following diagram shows the oscillator start-up sequence for a 27-MHz crystal
input with an 8-pF load. The start-up time for the crystal is in the order of approximately 250 µs compared to
approximately 10 µs of lock time. In general, lock time is an order of magnitude less compared to the crystal
start-up time.
Figure 18. Crystal Oscillator Start-Up vs PLL Lock Time
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Typical Application (continued)
10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
The frequency for the CDCEx949 is adjusted for media and other applications with the VCXO control input VCtrl.
If a PWM modulated signal is used as a control signal for the VCXO, an external filter is needed.
LP
PWM
control
signal
Vctrl
CDCEx949
Xin/CLK
Xout
Figure 19. Frequency Adjustment Using PWM Input to the VCXO Control
10.2.2.5 Unused Inputs and Outputs
If VCXO pulling functionality is not required, VCtrl should be left floating. All other unused inputs should be set to
GND. Unused outputs should be left floating.
If one output block is not used, TI recommends disabling it. However, TI always recommends providing the
supply for the second output block even if it is disabled.
10.2.2.6 Switching Between XO and VCXO Mode
When the CDCEx949 is in crystal oscillator or in VCXO configuration, the internal capacitors require different
internal capacitance. The following steps are recommended to switch to VCXO mode when the configuration for
the on-chip capacitor is still set for XO mode. To center the output frequency to 0 ppm:
1. While in XO mode, put Vctrl = Vdd/2
2. Switch from X0 mode to VCXO mode
3. Program the internal capacitors to obtain 0 ppm at the output.
10.2.3 Application Curves
Figure 20, Figure 21, Figure 22, and Figure 23 show CDCEx949 measurements with the SSC feature enabled.
Device configuration: 27-MHz input, 27-MHz output.
Figure 20. fOUT = 27 MHz, VCO Frequency < 125 MHz, SSC
(2% Center)
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Figure 21. fOUT = 27 MHz, VCO Frequency > 175 MHz, SSC
(1%, Center)
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Typical Application (continued)
Figure 22. Output Spectrum With SSC Off
Figure 23. Output Spectrum With SSC On, 2% Center
11 Power Supply Recommendations
There is no restriction on the power-up sequence. In case the VDDOUT is applied first, TI recommends grounding
the VDD. In case the VDDOUT is powered while VDD is floating, there is a risk of high current flowing on the VDDOUT.
The device has a power-up control that is connected to the 1.8-V supply. This keeps the whole device disabled
until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal components,
including the outputs. If there is a 3.3-V VDDOUT available before the 1.8-V, the outputs stay disabled until the 1.8V supply reaches a certain level.
12 Layout
12.1 Layout Guidelines
When the CDCEx949 is used as a crystal buffer, any parasitics across the crystal affects the pulling range of the
VCXO. Therefore, take care placing the crystal units on the board. Crystals must be placed as close to the
device as possible, ensuring that the routing lines from the crystal terminals to XIN and XOUT have the same
length.
If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the
device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise
coupling.
Additional discrete capacitors can be required to meet the load capacitance specification of certain crystal. For
example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can
range from 0 pF to 20 pF with steps of 1 pF. The 0.7-pF capacitor therefore can be discretely added on top of an
internal 10-pF capacitor.
To minimize the inductive influence of the trace, TI recommends placing this small capacitor as close to the
device as possible and symmetrically with respect to XIN and XOUT.
Figure 24 shows a conceptual layout detailing recommended placement of power supply bypass capacitors on
the basis of CDCEx949. For component side mounting, use 0402 body size capacitors to facilitate signal routing.
Keep the connections between the bypass capacitors and the power supply on the device as short as possible.
Ground the other side of the capacitor using a low-impedance connection to the ground plane.
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12.2 Layout Example
1
4
3
2
1
3
Place crystal with associated load
caps as close to the chip
Place bypass caps close to the device
pins, ensure wide freq. range
2
Place series termination resistors at
Clock outputs to improve signal integrity
4
Use ferrite beads to isolate the device
supply pins from board noise sources
Figure 24. Annotated Layout
32
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.1.2 Development Support
For development support see the following:
• SMBus
• I2C Bus
13.2 Related Documentation
For related documentation see the following:
VCXO Application Guideline for CDCE(L)9xx Family (SCAA085)
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 14. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
CDCE949
Click here
Click here
Click here
Click here
Click here
CDCEL949
Click here
Click here
Click here
Click here
Click here
13.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.6 Trademarks
TI-DaVinci, OMAP, Pro-Clock, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
Ethernet is a trademark of Xerox Corporation.
All other trademarks are the property of their respective owners.
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13.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCE949PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE949
CDCE949PWG4
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE949
CDCE949PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE949
CDCE949PWRG4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE949
CDCEL949PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCEL949
CDCEL949PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCEL949
CDCEL949PWRG4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCEL949
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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