CY2291

CY2291 Three-PLL General Purpose EPROM Programmable Clock Generator Features ■ ■ ■ ■ ■ ■ ■ ■ ■ Benefits ■ ■ ■ ■ ■ ■ ■ ■ ■ Three integrated phase-locked loops EPROM programmability Factory-programmable (CY2291) or field-programmable (CY2291F) device options Low-skew, low-jitter, high-accuracy outputs Power-management options (Shutdown, OE, Suspend) Frequency select option Smooth slewing on CPUCLK Configurable 3.3V or 5V operation 20-pin SOIC Package Input Frequency Range 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) Generates up to three custom frequencies from external sources Easy customization and fast turnaround Programming support available for all opportunities Meets critical industry standard timing requirements Supports low-power applications Eight user-selectable frequencies on CPU PLL Allows downstream PLLs to stay locked on CPUCLK output Enables application compatibility Industry-standard packaging saves on board space Specifics Factory Programmable Commercial Temperature Factory Programmable Industrial Temperature Field Programmable Commercial Temperature Field Programmable Industrial Temperature Part Number Outputs CY2291 CY2291I CY2291F CY2291FI 8 8 8 8 Output Frequency Range 76.923 kHz–100 MHz (5V) 76.923 kHz–80 MHz (3.3V) 76.923 kHz–90 MHz (5V) 76.923 kHz–66.6 MHz (3.3V) 76.923 kHz–90 MHz (5V) 76.923 kHz–66.6 MHz (3.3V) 76.923 kHz–80 MHz (5V) 76.923 kHz–60.0 MHz (3.3V) Logic Block Diagram 32XIN 32XOUT XTALIN OSC. XTALOUT S0 S1 S2/SUSPEND UPLL (10 BIT) /1,2,4,8 /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40 /48,52,96,104 /2,3,4 CLKA CLKB CPLL (8 BIT) /1,2,4 XBUF CPUCLK OSC. 32K MUX CLKC CLKD SPLL (8 BIT) CLKF CONFIG EPROM SHUTDOWN/ OE Cypress Semiconductor Corporation Document #: 38-07189 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 16, 2008 [+] Feedback CY2291 Pinouts Figure 1. CY2291- 20-pin SOIC 32XOUT 32K CLKC VDD GND XTALIN XTALOUT XBUF CLKD CPUCLK 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 32XIN VBATT SHUTDOWN/OE S2/SUSPEND VDD S1 S0 CLKF CLKA CLKB Pin Definitions Name 32XOUT 32K CLKC VDD GND XTALIN[1] XTALOUT[1, 2] XBUF CLKD CPUCLK CLKB CLKA CLKF S0 S1 S2/SUSPEND SHUTDOWN/OE VBATT 32XIN Pin Number 1 2 3 4, 16 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 32.768-kHz crystal feedback. 32.768-kHz output (always active if VBATT is present). Configurable clock output C. Voltage supply. Ground. Reference crystal input or external reference clock input. Reference crystal feedback. Buffered reference clock output. Configurable clock output D. CPU frequency clock output. Configurable clock output B. Configurable clock output A. Configurable clock output F. CPU clock select input, bit 0. CPU clock select input, bit 1. CPU clock select input, bit 2. Optionally enables suspend feature when LOW.[3] Places outputs in three-state[4] condition and shuts down chip when LOW. Optionally, only places outputs in three-state[4] condition and does not shut down chip when LOW. Battery supply for 32.768-kHz circuit. 32.768-kHz crystal input. Description Notes 1. For best accuracy, use a parallel-resonant crystal, CLOAD ≈ 17 pF or 18 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal). 3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information. 4. The CY2291 has weak pull downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW. Document #: 38-07189 Rev. *C Page 2 of 12 [+] Feedback CY2291 Operation The CY2291 is a third-generation family of clock generators. The CY2291 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems. All parts provide a highly configurable set of clocks for PC motherboard applications. Each of the four configurable clock outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies have low (