CY22E016L

CY22E016L 16 Kbit (2K x 8) nvSRAM Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The Cypress CY22E016L is a fast static RAM with a non-volatile element incorporated in each static memory cell. The SRAM is read and written an infinite number of times, while independent, non-volatile data resides in non-volatile elements. Data transfers from the SRAM to the non-volatile elements (the STORE operation) takes place automatically on power down. A 68 μF or larger capacitor tied from VCAP to ground guarantees the STORE operation, regardless of power down slew rate or loss of power from “hot swapping.” Transfers from the non-volatile elements to the SRAM (the RECALL operation) take place automatically on restoration of power. A hardware STORE is initiated with the HSB pin. 25 ns, 35 ns and 45 ns access times Hands off automatic STORE on power down with external 68 μF capacitor STORE to QuantumTrap™ non-volatile elements is initiated by hardware or AutoStore on power down RECALL to SRAM is initiated on power up Infinite READ, WRITE, and RECALL cycles 10 mA typical ICC at 200 ns cycle time 1,000,000 STORE cycles to QuantumTrap 100 year data retention to QuantumTrap Single 5V operation +10% Commercial and industrial temperature SOIC package RoHS compliance Logic Block Diagram V CC V CAP Quantum Trap 32 X 512 A5 A6 A7 A8 A9 STORE POWER CONTROL STORE/ RECALL CONTROL ROW DECODER STATIC RAM ARRAY 32 X 512 RECALL HSB DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 COLUMN I/O INPUT BUFFERS DQ 1 COLUMN DEC A 0 A 1 A 2 A 3 A 4 A 10 OE CE WE Cypress Semiconductor Corporation Document Number: 001-06727 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 1, 2007 [+] Feedback CY22E016L Pin Configurations V CAP NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 V SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 V CC WE HSB A8 A9 NC OE A 10 CE DQ7 DQ6 DQ5 DQ4 DQ3 28-SOIC Top View (Not To Scale) 23 22 21 20 19 18 17 16 15 Pin Definitions Pin Name A0–A10 WE CE OE VSS VCC HSB IO Type Input Input Input Input Ground Description Address Inputs. Used to select one of the 2,048 bytes of the nvSRAM. Write Enable Input, Active LOW. When selected LOW, this writes data on the IO pins to the address location latched by the falling edge of CE. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. Ground for the Device. Is connected to ground of the system. DQ0-DQ7 Input/Output Bidirectional Data IO lines. Used as input or output lines depending on operation. Power Supply Power Supply Inputs to the Device. Input/Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a non-volatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional). Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to non-volatile elements. No Connect No Connects. This pin is not connected to the die. VCAP NC Document Number: 001-06727 Rev. *D Page 2 of 14 [+] Feedback CY22E016L Device Operation The CY22E016L nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a non-volatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the non-volatile cell (the STORE operation) or from the non-volatile cell to SRAM (the RECALL operation). This unique architecture enables storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The CY22E016L supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the non-volatile cells and up to one million STORE operations. on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the 10 ms STORE cycle.. Figure 1. AutoStore Mode 10k Ohm 1 28 27 26 SRAM Read The CY22E016L performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0–10 determines which of the 2,048 data bytes are accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. 68 UF 6v, +20% U 0.1 F Bypass 14 15 SRAM Write A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs are stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common IO pins IO0–7 is written into the memory if it is valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. Figure 2. System Power Mode 10k Ohm 1 28 27 26 AutoStore Operation During normal AutoStore operation, the CY22E016L draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC and initiates a STORE operation. Figure 1 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor, having a capacity of between 68 μF and 220 μF (±20%) rated at 6V, is provided. In system power mode, both VCC and VCAP are connected to the +5V power supply without the 68 μF capacitor. In this mode, the AutoStore function of the CY22E016L operates U 0.1 F Bypass 14 15 Document Number: 001-06727 Rev. *D 10k Ohm 10k Ohm Page 3 of 14 [+] Feedback CY22E016L If an automatic STORE on power loss is not required, then VCC is tied to ground and +5V is applied to VCAP. This is the AutoStore Inhibit mode where the AutoStore function is disabled. If the CY22E016L is operated in this configuration, references to VCC are changed to VCAP throughout this datasheet. In this mode, STORE operations are triggered with the HSB pin. It is not permissible to change between these three options at will. To prevent unneeded STORE operations, automatic STOREs and those initiated by externally driving HSB LOW are ignored, unless at least one WRITE operation takes place since the most recent STORE or RECALL cycle. An optional pull up resistor is shown connected to HSB. This is used to signal the system that the AutoStore cycle is in progress. Figure 3. AutoStore Inhibit Mode 0.1U F Bypass pin is connected together to the HSB pins from the other CY22E016L. An external pull up resistor to +5V is required, since HSB acts as an open drain pull down. The VCAP pins from the other CY22E016L parts are tied together and share a single capacitor. The capacitor size is scaled by the number of devices connected to it. When any one of the CY22E016L detects a power loss and asserts HSB, the common HSB pin causes all parts to request a STORE cycle. (A STORE takes place in those CY22E016L that are written since the last non-volatile cycle.) During any STORE operation, regardless of how it is initiated, the CY22E016L continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the CY22E016L remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected. 10k Ohm Hardware RECALL (Power Up) During power up or after any low power condition (VCC < VSWITCH), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. 10k Ohm 1 28 27 26 Data Protection The CY22E016L protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY22E016L is in a WRITE mode (both CE and WE are LOW) at power up after a RECALL or after a STORE, the WRITE is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions. Noise Considerations 14 15 Hardware STORE (HSB) Operation The CY22E016L provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven low, the CY22E016L conditionally initiates a STORE operation after tDELAY. An actual STORE cycle begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition, while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the CY22E016L continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it is allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. The HSB pin is used to synchronize multiple CY22E016L while using a single larger capacitor. To operate in this mode, the HSB The CY22E016L is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduces circuit noise. Low Average Active Power CMOS technology provides the CY22E016L the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 4 shows the relationship between ICC and READ/WRITE cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY22E016L depends on the following items: 1. The duty cycle of chip enable 2. The overall cycle rate for accesses 3. The ratio of READs to WRITEs 4. CMOS vs. TTL input levels 5. The operating temperature 6. The VCC level 7. IO loading Page 4 of 14 Document Number: 001-06727 Rev. *D [+] Feedback CY22E016L Preventing STOREs The STORE function is disabled by holding HSB HIGH with a driver capable of sourcing 30 mA at a VOH of at least 2.2V, because it has to overpower the internal pull down device. The device drives HSB low for 20 ns at the onset of a STORE. When the CY22E016L is connected for AutoStore operation (system Table 1. Hardware Mode Selection CE H L L X WE X H L X HSB H H H L A10–A0 X X X X Mode Not Selected Read SRAM Write SRAM Non-volatile STORE IO Output High Z Output Data Input Data Output High Z Power Standby Active Active ICC2 VCC connected to VCC and a 68 μF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the CY22E016L attempts to pull HSB LOW; if HSB does not actually get below VIL, the part stops trying to pull HSB low and abort the STORE attempt. Figure 4. Current versus Cycle Time (READ) Figure 5. Current versus Cycle Time (WRITE) Document Number: 001-06727 Rev. *D Page 5 of 14 [+] Feedback CY22E016L Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V Voltage Applied to Outputs in High Z State ....................................... –0.5V to VCC + 0.5V Input Voltage.............................................–0.5V to Vcc+0.5V Transient Voltage (greater than 20 ns) on Any Pin to Ground Potential .................. –0.5V to VCC + 2.0V Package Power Dissipation Capability (TA = 25°C) ................................................... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) .......................................... +260°C Output Short Circuit Current [1] .................................... 15 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VCC 4.5V to 5.5V DC Electrical Characteristics Over the Operating Range (VCC = 4.5V to 5.5V) [2] Parameter ICC1 Description Average VCC Current Test Conditions Commercial tRC = 25 ns tRC = 35 ns tRC = 45 ns Dependent on output loading and cycle rate. Industrial Values obtained without output loads. IOUT = 0mA. All Inputs Do Not Care, VCC = Max Average current for duration tSTORE Min Max 85 75 65 75 3 10 Unit mA mA mA mA mA mA ICC2 ICC3 Average VCC Current during STORE Average VCC Current at WE > (VCC – 0.2). All other inputs cycling. tAVAV = 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained without output loads. Typical Average VCAP Current All Inputs Do Not Care, VCC = Max during AutoStore Cycle Average current for duration tSTORE VCC Standby Current CE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V). Standby current level after non-volatile cycle is complete. Inputs are static. f = 0 MHz. -1 -5 2.2 VSS – 0.5 IOUT = –4 mA except HSB IOUT = 8 mA except HSB IOUT = 3 mA 2.4 ICC4 ISB 2 2.5 mA mA IILK IOLK VIH VIL VOH VOL VBL Input Leakage Current VCC = Max, VSS < VIN < VCC Off State Output VCC = Max, VSS < VIN < VCC, CE or OE > VIH Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Logic’0’ on HSB +1 +5 VCC + 0.5 0.8 0.4 0.4 μA μA V V V V V Notes 1. Outputs shorted for no more than one second. No more than one output shorted at a time. 2. Typical conditions for the Active Current shown on the front page of the datasheet are average values at 25°C (room temperature) and VCC = 5V. Not 100% tested. Document Number: 001-06727 Rev. *D Page 6 of 14 [+] Feedback CY22E016L Capacitance These parameters are guaranteed but not tested. Parameter CIN COUT Description Input Capacitance Output Capacitance TA = 25°C, f = 1 MHz, VCC = 0 to 3.0 V Test Conditions Max 8 7 Unit pF pF Thermal Resistance These parameters are guaranteed but not tested. Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 28-SOIC TBD TBD Unit °C/W °C/W ΘJA ΘJC AC Test Loads R1 963Ω 5.0V Output 30 pF R2 512Ω Output 5 pF R2 512Ω 5.0V R1 963Ω For Tri-state Specifications AC Test Conditions Input Pulse Levels.................................................... 0V to 3V Input Rise and Fall Times (10% - 90%)........................