CY2303SI

CY2303 Phase-Aligned Clock Multiplier Features • 3-multiplier configuration (1x, 2x, 4x Ref) • 10 MHz to 166.67 MHz operating range (reference input from 10 MHz to 41.67 MHz) • Phase Alignment • 80 ps typical period jitter • Output enable pin • 3.3V operation • 5V Tolerant input • 8-pin 150-mil SOIC package • Commercial and Industrial Temperature available Functional Description The CY2303 is a 3 output 3.3V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part allows user to obtain 1x, 2x, and 4x Ref output frequencies on respective output pins. The CY2303 has an on-chip PLL, which locks to an input clock presented on the REFIN pin. The PLL feedback is internally connected to the REF output. The input-to-output skew is guaranteed to be less than ±200 ps, and output-to-output skew is guaranteed to be less than 200 ps. Multiple CY2303 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 400 ps. The CY2303 is available in commercial and industrial temperature ranges. Selector Guide Part Number CY2303SC, CY2303SXC CY2303SI, CY2303SXI Outputs 3 3 Input Frequency Range 10 MHz–41.67 MHz 10 MHz–41.67 MHz Output Frequency Range 10 MHz–166.67 MHz 10 MHz–166.67 MHz Specifics Commercial Temperature Industrial Temperature Block Diagram FBK Pin Configuration 8-pin SOIC Top View x1 REF REFIN PLL x2 REFx2 REF GND REFIN N/C 1 2 3 4 8 7 6 5 OE VDD REFx4 REFx2 x4 OE REFx4 Cypress Semiconductor Corporation Document #: 38-07249 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised August 2, 2005 CY2303 Pin Description Pin 1 2 3 4 5 6 7 8 REF GND REFIN N/C REFx2 REFx4 VDD OE Signal[1] REF output (1x Reference input) Ground Input reference frequency, 5V tolerant input No Connect 2x Reference input 4x Reference input 3.3V Supply Output Enable (weak pull-up) Storage Temperature ................................. –65°C to +150°C Junction Temperature ................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Description Maximum Ratings Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage (Except Ref)...............–0.5V to VDD + 0.5V DC Input Voltage REFIN ........................................–0.5 to 7V Operating Conditions for CY2303SC Commercial Temperature Devices Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, Fout < 133.33 MHz Load Capacitance, 133.33 MHz < Fout < 166.67 MHz Input Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.0 0 – – – 0.05 Max. 3.6 70 18 12 7 50 Unit V °C pF pF pF ms Electrical Characteristics for CY2303SC Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[2] Output HIGH Voltage[2] Supply Current VIN = 0V VIN = VDD IOL = 8 mA IOH = –8 mA Unloaded outputs, REFIN = 41.67 MHz Unloaded outputs, REFIN = 25 MHz Unloaded outputs, REFIN = 10 MHz Notes: 1. Weak pull-down on all outputs. 2. Parameter is guaranteed by design and characterization. It is not 100% tested in production. Test Conditions Min. – 2.0 – – – 2.4 – – – Max. 0.8 – 100 50 0.4 – 45 32 18 Unit V V µA µA V V mA mA mA Document #: 38-07249 Rev. *B Page 2 of 7 CY2303 Switching Characteristics for CY2303SC Commercial Temperature Devices Parameter 1/t1 Name Output Frequency Duty Cycle t3 t4 t5 t6 t7 tJ tLOCK Rise Time [3] Test Conditions 18-pF load 12-pF load Measured at VDD/2 Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Min. 10 – 40 – – – – – – – Typ. – – 50 – – – – – 80 – Max. 133.33 166.67 60 1.20 1.20 200 ±200 400 ±175 1.0 Unit MHz MHz % ns ns ps ps ps ps ms = t2 ÷ t1 [3] Fall Time[3] Output to Output Skew on rising All outputs equally loaded edges[3] Measured at VDD/2 Delay, REFIN Rising Edge to REF Rising Edge[3] Device to Device Skew[3] Period Jitter[3] PLL Lock Time[3] Measured at VDD/2 from REFIN to any output Measured at VDD/2 on the REF pin of the device (pin 1) Measured at Fout < 133.33 MHz, loaded outputs, 18-pF load Stable power supply, valid clocks presented on REFIN Operating Conditions for CY2303SI Industrial Temperature Devices Parameter VDD TA CL tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, Fout