CY2304SXI-2T

CY2304 3.3V Zero Delay Buffer Features ■ ■ ■ ■ ■ ■ ■ ■ Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations — see Table 1 on page 1 Multiple low-skew outputs 10 MHz to 133 MHz operating range 90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz Space-saving 8-pin 150-mil SOIC package 3.3V operation Industrial temperature available required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. The CY2304 has two banks of two outputs each. The CY2304 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps. The CY2304 is available in two different configurations, as shown in Table 1 on page 1. The CY2304–1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The CY2304–2 allows the user to obtain Ref and 1/2x or 2x frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. Functional Description The CY2304 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is Logic Block Diagram FBK CLKA1 REF PLL CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 Table 1. Available Configurations Device CY2304-1 CY2304-2 CY2304-2 FBK from Bank A or B Bank A Bank B Bank A Frequency Reference Reference 2 × Reference Bank B Frequency Reference Reference/2 Reference Pinouts Figure 1. 8-Pin SOIC - Top View REF CLKA1 CLKA2 GND 1 2 3 4 8 7 6 5 FBK VDD CLKB2 CLKB1 Cypress Semiconductor Corporation Document #: 38-07247 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 18, 2008 [+] Feedback CY2304 l Table 2. Pin Definitions - 8-Pin SOIC Pin 1 2 3 4 5 6 7 8 Signal REF[1] CLKA1[2] CLKA2 GND CLKB1[2] CLKB2 VDD FBK [2] [2] Description Input reference frequency, 5V tolerant input Clock output, Bank A Clock output, Bank A Ground Clock output, Bank B Clock output, Bank B 3.3V supply PLL feedback input Zero Delay and Skew Control Figure 2. REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins To close the feedback loop of the CY2304, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin is driving a total load of 7 pF, with any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in Figure 2. For applications requiring zero input-output delay, all outputs including the one providing feedback must be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. For further information on using CY2304, refer to the application note AN1234 “CY2308: Zero Delay Buffer.” Notes 1. Weak pull down. 2. Weak pull down on all outputs. Document #: 38-07247 Rev. *E Page 2 of 9 [+] Feedback CY2304 Maximum Ratings Supply Voltage to Ground Potential.................–0.5V to +7.0V DC Input Voltage (Except Ref) ...............–0.5V to VDD + 0.5V DC Input Voltage REF.............................................–0.5 to 7V Storage Temperature ..................................–65°C to +150°C Junction Temperature ..................................................150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) .............................> 2000V Operating Conditions for CY2304SC-X Commercial Temperature Devices Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance (below 100 MHz) Load Capacitance (from 100 MHz to 133 MHz) Input Capacitance[3] Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min 3.0 0 – – – 0.05 Max 3.6 70 30 15 7 50 Unit V °C pF pF pF ms Electrical Characteristics for CY2304SC-X Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Output HIGH Voltage[4] Voltage[4] VIN = 0V VIN = VDD IOL = 8 mA (–1, –2) IOH = –8 mA (–1, –2) Unloaded outputs, 100 MHz REF, Select inputs at VDD or GND Unloaded outputs, 66 MHz REF (–1,–2) Unloaded outputs, 33 MHz REF (–1,–2) Test Conditions Min – 2.0 – – – 2.4 – – – – Max 0.8 – 50.0 100.0 0.4 – 25.0 45.0 32.0 18.0 Unit V V μA μA V V μA mA mA mA IDD (PD mode) Power down Supply Current REF = 0 MHz Supply Current Switching Characteristics for CY2304SC-X Commercial Temperature Devices Parameter[5] t1 t1 tDC t3 t3 t4 Name Output Frequency Output Frequency Duty (–1,–2) Cycle[4] = t2 ÷ t1 Test Conditions 30 pF load, all devices 15 pF load, –1, –2 devices Measured at 1.4V, FOUT = 66.66 MHz, 30 pF load Measured between 0.8V and 2.0V, 30 pF load Measured between 0.8V and 2.0V, 15 pF load Measured between 0.8V and 2.0V, 30 pF load Min 10 10 40.0 – – – Typ. – – 50.0 – – – Max 100 133.3 60.0 2.20 1.50 2.20 Unit MHz MHz % ns ns ns Rise Time[4] (–1, –2) Rise Time[4] (–1, –2) Fall Time[4] (–1, –2) Notes 3. Applies to both REF clock and FBK. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 5. All parameters are specified with loaded output. Document #: 38-07247 Rev. *E Page 3 of 9 [+] Feedback CY2304 Switching Characteristics for CY2304SC-X Commercial Temperature Devices (continued) Parameter[5] t4 t5 Fall Time (–1, –2) Name [4] Test Conditions Measured between 0.8V and 2.0V, 15 pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured at 66.67 MHz, loaded outputs, 15 pF load Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load Min – – – – – – – – – – – – Typ. – – – – 0 0 90 – – – – – Max 1.50 200 200 400 ±250 500 175 200 100 400 375 1.0 Unit ns ps ps ps ps ps ps ps ps ps ps ms Output-to-Output Skew on same Bank (–1,–2)[4] Output Bank A to Output Bank B Skew (–1) Output Bank A to Output Bank B Skew (–2) t6 t7 tJ Skew, REF Rising Edge to FBK Rising Edge[4] Device-to-Device Skew[4] Cycle-to-Cycle Jitter[4] (–1) tJ Cycle-to-Cycle Jitter[4] (–2) Measured at 66.67 MHz, loaded outputs 30 pF load Measured at 66.67 MHz, loaded outputs 15 pF load tLOCK PLL Lock Time[4] Stable power supply, valid clocks presented on REF and FBK pins Operating Conditions for CY2304SI-X Industrial Temperature Devices Parameter VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance (below 100 MHz) Load Capacitance (from 100 MHz to 133 MHz) Input Capacitance Description Min 3.0 –40 – – – Max 3.6 85 30 15 7 Unit V °C pF pF pF Electrical Characteristics for CY2304SI-X Industrial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[4] Output HIGH Voltage[4] VIN = 0V VIN = VDD IOL = 8 mA (–1, –2) IOH = –8 mA (–1, –2) Test Conditions Min – 2.0 – – – 2.4 Max 0.8 – 50.0 100.0 0.4 – Unit V V μA μA V V Document #: 38-07247 Rev. *E Page 4 of 9 [+] Feedback CY2304 Electrical Characteristics for CY2304SI-X Industrial Temperature Devices (continued) Parameter IDD Description Supply Current Test Conditions Unloaded outputs, 100 MHz, Select inputs at VDD or GND Unloaded outputs, 66 MHz REF (–1, –2) Unloaded outputs, 33 MHz REF (–1, –2) Min – – – – Max 25.0 45.0 35.0 20.0 Unit μA mA mA mA IDD (PD mode) Power down Supply Current REF = 0 MHz Switching Characteristics for CY2304SI-X Industrial Temperature Devices Parameter[5] t1 t1 tDC t3 t3 t4 t4 t5 Name Output Frequency Output Frequency Duty (–1,–2) Cycle[4] = t2 ÷ t1 Test Conditions 30 pF load, All devices 15 pF load, All devices Measured at 1.4V, FOUT = 66.66 MHz, 30 pF load Measured between 0.8V and 2.0V, 30 pF load Measured between 0.8V and 2.0V, 15 pF load Measured between 0.8V and 2.0V, 30 pF load Measured between 0.8V and 2.0V, 15 pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured at 66.67 MHz, loaded outputs, 15 pF load Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load tJ Cycle-to-Cycle Jitter[4] (–2) Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 66.67 MHz, loaded outputs, 15 pF load tLOCK PLL Lock Time[4] Stable power supply, valid clocks presented on REF and FBK pins Min 10 10 40.0 – – – – – – – – – – – – – – – 50.0 – – – – – – – 0 0 – – – – – – Typ. Max 100 133.3 60.0 2.50 1.50 2.50 1.50 200 200 400 ±250 500 180 200 100 400 380 1.0 Unit MHz MHz % ns ns ns ns ps ps ps ps ps ps ps ps ps ps ms Rise Time[4] (–1, –2) Rise Time[4] (–1, –2) Fall Time[4] (–1, –2) Fall Time[4] (–1, –2) Output-to-Output Skew on same Bank (–1,–2)[4] Output Bank A to Output Bank B Skew (–1) Output Bank A to Output Bank B Skew (–2) t6 t7 tJ Skew, REF Rising Edge to FBK Rising Edge[4] Device-to-Device Skew[4] Cycle-to-Cycle Jitter[4] (–1) Document #: 38-07247 Rev. *E Page 5 of 9 [+] Feedback CY2304 Switching Waveforms Figure 2. Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V Figure 3. All Outputs Rise/Fall Time 2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V OUTPUT Figure 4. Output-Output Skew 1.4V OUTPUT OUTPUT t5 1.4V Figure 5. Input-Output Skew VDD/2 INPUT FBK t6 VDD/2 Figure 6. Device-Device Skew FBK, Device 1 VDD/2 FBK, Device 2 t7 VDD/2 Document #: 38-07247 Rev. *E Page 6 of 9 [+] Feedback CY2304 Figure 7. Test Circuit # 1 VDD 0.1 μ F OUTPUTS V DD 0.1 μ F GND GND CLK OUT C LOAD Test circuit for all parameters except t8 Ordering Information Ordering Code CY2304SC–1 [6] Package Type 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC- Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC- Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC- Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC- Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC- Tape and Reel Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial CY2304SC–1T[6] CY2304SI–1[6] CY2304SI–1T[6] CY2304SC–2[6] CY2304SC–2T[6] Pb-Free CY2304SXC–1 CY2304SXC–1T CY2304SXI–1 CY2304SXI–1T CY2304SXC–2 CY2304SXC–2T CY2304SXI–2 CY2304SXI–2T Note 6. Not recommended for new designs. Document #: 38-07247 Rev. *E Page 7 of 9 [+] Feedback CY2304 Package Drawing and Dimensions Figure 8. 8 Lead (150 Mil) SOIC S08 8-Pin (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG. 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C Document #: 38-07247 Rev. *E Page 8 of 9 [+] Feedback CY2304 Document History Page Document Title: CY2304 3.3V Zero Delay Buffer Document Number: 38-07247 REV. ** *A *B *C *D *E ECN 110512 112294 113934 121851 308436 2542331 Orig. of Change SZV CKN CKN RBI RGL AESA Submission Date 12/11/01 03/04/02 05/01/02 12/14/02 01/26/05 09/18/08 Description of Change Change from Spec number: 38-01010 to 38-07247 On Pin Configuration Diagram (p.1), swapped CLKA2 and CLKA1 Added Operating Conditions for CY2304SI-X Industrial Temperature Devices, p. 4 Power up requirements added to Operating Conditions Information Added Lead-free Devices Updated template. Added Note “Not recommended for new designs.” Removed part number CY2304SI-2 and CY2304SI-2T. Changed Lead-Free to Pb-Free. Changed IDD (PD mode) from 12.0 to 25.0 μA. Deleted Duty Cycle parameters for FOUT < 50.0 MHz for commercial and industrial devices. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb © Cypress Semiconductor Corporation, 2001-2008. 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Document #: 38-07247 Rev. *E Revised September 18, 2008 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback