CY2305_11

CY2305, CY2309 Low Cost 3.3-V Zero Delay Buffer Features ■ Functional Description The CY2309 is a low-cost 3.3-V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100-/133 MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY2309 has two banks of four outputs each, which can be controlled by the select inputs as shown in “Select Input Decoding for CY2309” on page 4. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The CY2305 and CY2309 PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25.0 μA current draw for these parts. The CY2309 PLL shuts down in one additional case as shown in “Select Input Decoding for CY2309” on page 4. Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY2305/CY2309 is available in two or three different configurations, as shown in “Ordering Information for CY2305” on page 13. The CY2305-1/CY2309-1 is the base part. The CY2305-1H/ CY2309-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. Not recommended for new designs. The CY2305C and CY2309C are form, fit, function compatible devices with improved specifications. 10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies Zero input-output propagation delay 60-ps typical cycle-to-cycle jitter (high drive) Multiple low skew outputs ❐ 85 ps typical output-to-output skew ❐ One input drives five outputs (CY2305) ❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309) Compatible with Pentium-based systems Test Mode to bypass phase-locked loop (PLL) (CY2309) Packages: ❐ 8-pin, 150-mil SOIC package (CY2305) ❐ 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309) 3.3-V operation Commercial and industrial temperature ranges ■ ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram PLL REF MUX CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 S2 Select Input Decoding S1 CLKB2 CLKB3 CLKB4 Cypress Semiconductor Corporation Document Number : 38-07140 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 28, 2011 [+] Feedback CY2305, CY2309 Contents Pinouts .............................................................................. 3 Select Input Decoding for CY2309 .................................. 4 Zero Delay and Skew Control.......................................... 4 Absolute Maximum Conditions....................................... 5 Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices.................................. 5 Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices......... 5 Switching Characteristics for CY2305SC-1 and CY2309SC-1 Commercial Temperature Devices.................................. 5 Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices......... 6 Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices ......................................... 6 Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices............... 7 Switching Characteristics for CY2305SI-1 and CY2309SI-1 Industrial Temperature Devices ...................................... 7 Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices............... 8 Switching Waveforms ...................................................... 8 Typical Duty Cycle and IDD Trends for CY2305-1 and CY2309-1 .......................................................................... 10 Typical Duty Cycle and IDD Trends for CY2305-1H and CY2309-1H....................................................................... 11 Test Circuits.................................................................... 12 Ordering Information for CY2305.................................. 13 Ordering Information for CY2309.................................. 13 Ordering Code Definitions ......................................... 14 Package Drawing and Dimensions ............................... 15 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support....................... 19 Products .................................................................... 19 PSoC Solutions ......................................................... 19 Document Number : 38-07140 Rev. *M Page 2 of 19 [+] Feedback CY2305, CY2309 Pinouts Figure 1. Pin Diagram - CY2305 REF CLK2 CLK1 GND 1 2 3 4 8 7 6 5 CLKOUT CLK4 V DD CLK3 Table 1. Pin Description for CY2305 Pin 1 2 3 4 5 6 7 8 REF [1] Signal CLK2[2] CLK1[2] GND CLK3[2] VDD CLK4[2] CLKOUT[2] Buffered clock output Buffered clock output Ground Buffered clock output 3.3-V supply Buffered clock output Description Input reference frequency, 5-V tolerant input Buffered clock output, internal feedback on this pin Figure 2. Pin Diagram - CY2309 REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 Table 2. Pin Description for CY2309 Pin 1 2 3 4 5 6 7 8 9 10 11 12 REF[1] CLKA1[2] CLKA2[2] VDD GND CLKB1[2] CLKB2[2] S2[3] S1[3] CLKB3[2] CLKB4 GND [2] Signal Buffered clock output, Bank A Buffered clock output, Bank A 3.3-V supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Select input, bit 2 Select input, bit 1 Buffered clock output, Bank B Buffered clock output, Bank B Ground Description Input reference frequency, 5-V tolerant input Notes 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull ups on these inputs. Document Number : 38-07140 Rev. *M Page 3 of 19 [+] Feedback CY2305, CY2309 Table 2. Pin Description for CY2309 Pin 13 14 15 16 VDD CLKA3[4] CLKA4 [4] [4] Signal 3.3-V supply Buffered clock output, Bank A Buffered clock output, Bank A Description CLKOUT Buffered output, internal feedback on this pin Select Input Decoding for CY2309 S2 0 0 1 1 S1 0 1 0 1 CLOCK A1–A4 Three-state Driven Driven Driven CLOCK B1–B4 Three-state Three-state Driven Driven CLKOUT[5] Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown N N Y N Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins Zero Delay and Skew Control All outputs must be uniformly loaded to achieve zero delay between the input and output. Because the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. If input to output delay adjustments are required, use Figure 3 to calculate loading differences between the CLKOUT pin and other outputs. For zero output-output skew, be sure to load all outputs equally. For further information, refer to the application note titled “CY2305 and CY2309 as PCI and SDRAM Buffers.” Notes 4. Weak pull down on all outputs 5. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Document Number : 38-07140 Rev. *M Page 4 of 19 [+] Feedback CY2305, CY2309 Absolute Maximum Conditions Supply voltage to ground potential ...............–0.5 V to +7.0 V DC input voltage (Except REF) .......... –0.5 V to VDD + 0.5 V DC input voltage REF ........................................–0.5 V to 7 V Storage temperature .................................. –65°C to +150°C Junction temperature.................................................. 150°C Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2,000 V Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices Parameter VDD TA CL CL CIN tPU Supply voltage Operating temperature (ambient temperature) Load capacitance, below 100 MHz Load capacitance, from 100 MHz to 133 MHz Input capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min 3.0 0 – – – 0.05 Max 3.6 70 30 10 7 50 Unit V °C pF pF pF ms Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH Description Input LOW Input HIGH voltage[6] voltage[6] VIN = 0 V VIN = VDD IOL = 8 mA (–1) IOH = 12 mA (–1H) IOH = –8 mA (–1) IOL = –12 mA (–1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VSS Test Conditions Min – 2.0 – – – 2.4 – – Max 0.8 – 50.0 100.0 0.4 – 12.0 32.0 Unit V V μA μA V V μA mA Input LOW current Input HIGH current Output LOW voltage[7] Output HIGH voltage[7] IDD (PD mode) Power-down supply current IDD Supply current Switching Characteristics for CY2305SC-1 and CY2309SC-1 Commercial Temperature Devices Parameter[9] t1 tDC t3 t4 t5 t6A Name Output frequency Duty cycle[7] = t2 ÷ t1 Rise time[7] Fall time[7] skew[7] Output-to-output Test Conditions 30-pF load 10-pF load Measured at 1.4 V, Fout = 66.67 MHz Measured between 0.8 V and 2.0 V Measured between 0.8 V and 2.0 V All outputs equally loaded Measured at VDD/2 Min 10 10 40.0 – – – – Typ. – 50.0 – – 85 0 Max 100 133.33 60.0 2.50 2.50 250 ±350 Unit MHz MHz % ns ns ps ps Delay, REF rising edge to CLKOUT rising edge[7] Notes 6. REF input has a threshold voltage of VDD/2. 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document Number : 38-07140 Rev. *M Page 5 of 19 [+] Feedback CY2305, CY2309 Switching Characteristics for CY2305SC-1 and CY2309SC-1 Commercial Temperature Devices Parameter[9] t6B Name Delay, REF rising edge to CLKOUT rising edge[8] Device-to-device skew[8] Cycle-to-cycle jitter[8] PLL lock time[8] Test Conditions Measured at VDD/2. Measured in PLL Bypass Mode, CY2309 device only. Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Min 1 Typ. 5 Max 8.7 Unit ns t7 tJ tLOCK – – – – 70 – 700 200 1.0 ps ps ms Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices Parameter[9] t1 tDC tDC t3 t4 t5 t6A t6B Name Output frequency Duty cycle[8] = t2 ÷ t1 Duty Rise Fall cycle[8] time[8] skew[8] = t2 ÷ t1 30 pF load 10 pF load Measured at 1.4 V, Fout = 66.67 MHz Measured at 1.4 V, Fout < 50 MHz Measured between 0.8 V and 2.0 V Measured between 0.8 V and 2.0 V All outputs equally loaded Measured at VDD/2 Measured at VDD/2. Measured in PLL Bypass Mode, CY2309 device only. Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8 V and 2.0 V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Description Min 10 10 40.0 45.0 – – – – 1 Typ. – 50.0 50.0 – – 85 – 5 Max 100 133.33 60.0 55.0 1.50 1.50 250 ±350 8.7 Unit MHz MHz % % ns ns ps ps ns time[8] Output-to-output Delay, REF rising edge to CLKOUT rising edge[8] Delay, REF rising edge to CLKOUT rising edge[8] Device-to-device skew[8] Output slew rate[8] Cycle-to-cycle jitter[8] PLL lock time[8] t7 t8 tJ tLOCK – 1 – – – – 60 – 700 ps V/ns 200 1.0 ps ms Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices Parameter VDD TA CL CL CIN Supply voltage Operating temperature (ambient temperature) Load capacitance, below 100 MHz Load capacitance, from 100 MHz to 133 MHz Input capacitance Description Min 3.0 –40 – – – Max 3.6 85 30 10 7 Unit V °C pF pF pF Notes 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. 9. All parameters specified with loaded outputs. Document Number : 38-07140 Rev. *M Page 6 of 19 [+] Feedback CY2305, CY2309 Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH Description Input LOW voltage[10] [10] Test Conditions Min – 2.0 Max 0.8 – 50.0 100.0 0.4 – 25.0 35.0 Unit V V μA μA V V μA mA Input HIGH voltage Input LOW current Input HIGH current VIN = 0 V VIN = VDD IOL = 8 mA (–1) IOH =12 mA (–1H) IOH = –8 mA (–1) IOL = –12 mA (–1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VSS – – – 2.4 – – Output LOW voltage[11] Output HIGH voltage[11] IDD (PD mode) Power-down supply current IDD Supply current Switching Characteristics for CY2305SI-1 and CY2309SI-1 Industrial Temperature Devices Parameter[12] t1 tDC t3 t4 t5 t6A t6B t7 tJ tLOCK Name Output frequency Duty cycle[11] = t2 ÷ t1 Rise Fall time[11] skew[11] time[11] 30 pF load 10 pF load Measured at 1.4 V, Fout = 66.67 MHz Measured between 0.8 V and 2.0 V Measured between 0.8 V and 2.0 V All outputs equally loaded Test Conditions Min 10 10 40.0 – – – – 1 – – – Typ – 50.0 – – 85 – 5 – 70 – Max 100 133.33 60.0 2.50 2.50 250 ±350 8.7 700 200 1.0 Unit MHz MHz % ns ns ps ps ns ps ps ms Output-to-output Delay, REF rising edge to Measured at VDD/2 CLKOUT rising edge[11] Delay, REF rising edge to Measured at VDD/2. Measured in PLL Bypass Mode, CLKOUT rising edge[11] CY2309 device only. Device-to-device skew[11] Measured at VDD/2 on the CLKOUT pins of devices Cycle-to-cycle jitter PLL lock time[11] [11] Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Notes 10. REF input has a threshold voltage of VDD/2. 11. Parameter is guaranteed by design and characterization. Not 100% tested in production. 12. All parameters specified with loaded outputs Document Number : 38-07140 Rev. *M Page 7 of 19 [+] Feedback CY2305, CY2309 Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices Parameter[13] t1 tDC tDC t3 t4 t5 t6A t6B t7 t8 tJ tLOCK Name Output frequency Duty cycle[14] = t2 ÷ t1 Duty cycle Rise time [14] Description 30 pF load 10 pF load Measured at 1.4 V, Fout = 66.67 MHz Measured at 1.4 V, Fout < 50 MHz Measured between 0.8 V and 2.0 V Measured between 0.8 V and 2.0 V Min 10 10 40.0 45.0 – – – – 1 – 1 – – Typ – 50.0 50.0 – – 85 – 5 – – 60 – Max 100 133.33 60.0 55.0 1.50 1.50 250 ±350 8.7 700 – 200 1.0 Unit MHz MHz % % ns ns ps ps ns ps V/ns ps ms = t2 ÷ t1 [14] Fall time[14] Output-to output skew[14] All outputs equally loaded Delay, REF rising edge to Measured at VDD/2 CLKOUT rising edge[14] Delay, REF rising edge to Measured at VDD/2. Measured in PLL Bypass Mode, CLKOUT rising edge[14] CY2309 device only. Device-to-device skew[14] Measured at VDD/2 on the CLKOUT pins of devices Output slew rate[14] Cycle-to-cycle jitter[14] PLL lock time[14] Measured between 0.8 V and 2.0 V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Switching Waveforms Figure 4. Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V Figure 5. All Outputs Rise/Fall Time 3.3 V 0V OUTPUT 2.0 V 0.8 V t3 2.0 V 0.8 V t4 Figure 6. Output-Output Skew 1.4 V OUTPUT OUTPUT t5 1.4 V Notes 13. All parameters specified with loaded outputs. 14. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document Number : 38-07140 Rev. *M Page 8 of 19 [+] Feedback CY2305, CY2309 Switching Waveforms Figure 7. Input-Output Propagation Delay INPUT VDD/2 OUTPUT t6 VDD/2 Figure 8. Device-Device Skew VDD/2 CLKOUT, Device 1 CLKOUT, Device 2 t7 VDD/2 Document Number : 38-07140 Rev. *M Page 9 of 19 [+] Feedback CY2305, CY2309 Typical Duty Cycle[15] and IDD Trends[16] for CY2305-1 and CY2309-1 Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C) 60 58 56 Duty Cycle (% ) Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C) 60 58 56 Duty Cycle (% ) 54 52 50 48 46 44 42 40 33 MHz 66 MHz 100 MHz 133 MHz 54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 33 MHz 66 MHz 100 MHz 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 Duty Cycle Vs Frequency (for 30 pF Loads over Temperature - 3.3V) 60 58 56 Duty Cycle (%) Duty Cycle Vs Frequency (for 15 pF Loads over Temperature - 3.3V) 60 58 56 Duty Cycle (%) -40C 0C 25C 70C 85C 54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140 54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140 -40C 0C 25C 70C 85C IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C) 140 120 100 IDD (mA) 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 # of Loaded Outputs 33 MHz 66 MHz 100 MHz IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C) 140 120 100 IDD (mA) 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 # of Loaded Outputs 33 MHz 66 MHz 100 MHz Notes 15. Duty cycle is taken from typical chip measured at 1.4 V. 16. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = frequency (Hz)). Document Number : 38-07140 Rev. *M Page 10 of 19 [+] Feedback CY2305, CY2309 Typical Duty Cycle[17] and IDD Trends[18] for CY2305-1H and CY2309-1H Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C) 60 58 56 Duty Cycle (% ) Duty Cycle (% ) 54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 33 MHz 66 MHz 100 MHz 60 58 56 54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 33 MHz 66 MHz 100 MHz 133 MHz Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C) Duty Cycle Vs Frequency (for 30 pF Loads over Temperature - 3.3V) 60 58 56 Duty Cycle (%) Duty Cycle (%) Duty Cycle Vs Frequency (for 15 pF Loads over Temperature - 3.3V) 60 58 56 54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140 -40C 0C 25C 70C 85C 54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140 -40C 0C 25C 70C 85C IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C) 160 140 120 IDD (mA) 33 MHz 66 MHz 100 MHz IDD (mA) 100 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 # of Loaded Outputs 160 140 120 100 80 60 40 20 0 0 1 IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C) 33 MHz 66 MHz 100 MHz 2 3 4 5 6 7 8 9 # of Loaded Outputs Notes 17. Duty cycle is taken from typical chip measured at 1.4 V. 18. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = frequency (Hz)). Document Number : 38-07140 Rev. *M Page 11 of 19 [+] Feedback CY2305, CY2309 Test Circuits Test Circuit # 1 V DD 0.1 μ F CLK OUTPUTS C LOAD V DD 0.1 μ F GND GND 0.1 μ F V DD GND GND out 0.1 μ F Test Circuit # 2 V DD OUTPUTS 1 kΩ 10 pF 1 kΩ For parameter t8 (output slew rate) on -1H devices Document Number : 38-07140 Rev. *M Page 12 of 19 [+] Feedback CY2305, CY2309 Ordering Information for CY2305 Ordering Code CY2305SC-1[19] CY2305SC-1T[19] CY2305SC-1H CY2305SI-1H Pb-free CY2305SXC-1[19] CY2305SXC-1T [19] [19] [19] Package Type 8-pin 150-mil SOIC 8-pin 150-mil SOIC – Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC – Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC – Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC – Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC – Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC – Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC – Tape and Reel Operating Range Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial CY2305SC-1HT CY2305SI-1HT [19] [19] CY2305SXI-1[19] CY2305SXI-1T[19] CY2305SXC-1H[19] CY2305SXC-1HT[19] CY2305SXI-1H[19] CY2305SXI-1HT[19] Ordering Information for CY2309 Ordering Code CY2309SC-1[19] CY2309SC-1T[19] CY2309SC-1H[19] CY2309SC-1HT[19] CY2309ZC-1H[19] CY2309ZC-1HT[19] Pb-free CY2309SXC-1[19] CY2309SXC-1T[19] CY2309SXI-1[19] CY2309SXI-1T[19] CY2309SXC-1H[19] CY2309SXC-1HT[19] CY2309SXI-1H[19] CY2309SXI-1HT[19] CY2309ZXC-1H[19] CY2309ZXC-1HT[19] CY2309ZXI-1H[19] CY2309ZXI-1HT[19] 16-pin 150-mil SOIC 16-pin 150-mil SOIC – Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC – Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC – Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC – Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP – Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP – Tape and Reel Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial 16-pin 150-mil SOIC 16-pin 150-mil SOIC – Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC – Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP – Tape and Reel Package Type Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Note 19. Not recommended for new designs. Document Number : 38-07140 Rev. *M Page 13 of 19 [+] Feedback CY2305, CY2309 Ordering Code Definitions CY 2305 S (X) C – 1 (H) (T) Tape and reel Output Drive: 1 = standard drive 1H = high drive Temperature Range: C = Commercial I = Industrial Package: S = SOIC, leaded Z = TSSOP, leaded SX = SOIC, Pb-free ZX = TSSOP, Pb-free Base device part number 2305 = 5-output zero delay buffer 2309 = 9-output zero delay buffer Company ID: CY = Cypress Document Number : 38-07140 Rev. *M Page 14 of 19 [+] Feedback CY2305, CY2309 Package Drawing and Dimensions Figure 9. 8-Pin (150-Mil) SOIC S8 51-85066 *D Document Number : 38-07140 Rev. *M Page 15 of 19 [+] Feedback CY2305, CY2309 Figure 10. 16-Pin (150-Mil) SOIC S16 51-85068 *C Figure 11. 16-Pin TSSOP 4.40 MM Body Z16.173 51-85091 *C Document Number : 38-07140 Rev. *M Page 16 of 19 [+] Feedback CY2305, CY2309 Acronyms Acronym PCI PLL SDRAM SOIC TSSOP ZDB Description Personal computer interconnect Phase locked loop Synchronous dynamic random access memory Small outline integrated circuit Thin small outline package Zero delay buffer Document Conventions Units of Measure Symbol Unit of Measure degree Celsius micro amperes milli amperes milli seconds Mega Hertz nano seconds pico Farad pico seconds Volts °C µA mA ms MHz ns pF ps V Document Number : 38-07140 Rev. *M Page 17 of 19 [+] Feedback CY2305, CY2309 Document History Page Document Title: CY2305/CY2309 Low Cost 3.3-V Zero Delay Buffer Document Number: 38-07140 Rev. ** *A ECN 110249 111117 Orig. of Change SZV CKN Submission Date 10/19/01 03/01/02 Description of Change Change from Spec number: 38-00530 to 38-07140 Added t6B row to the Switching Characteristics Table; also added the letter “A” to the t6A row Corrected the table title from CY2305SC-IH and CY2309SC-IH to CY2305SI-IH and CY2309SI-IH Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the ordering information table. Added the Tape and Reel option to all the existing packages: CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT, CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT, CY2309SI-1HT, CY2309ZC-1HT, CY2309ZI-1HT Power up requirements added to Operating Conditions information Added Lead-free for all the devices in the ordering information table Added a Lead-free with the new coding for all SOIC devices in the ordering information table Added TSSOP Lead-free devices Added typical values for jitter Updated template. Added Note “Not recommended for new designs.” Added part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1, CY2305ESXI-1T, CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H, CY2305ESXI-1HT, CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1, CY2309ESXI-1T, CY2309ESXC-1H, CY2309ESXC-1HT, CY2309ESXI-1H, CY2309ESXI-1HT, CY2309EZXC-1H, CY2309EZXC-1HT, CY2309EZXI-1H, and CY2309EZXI-1HT in ordering information table. Removed part number CY2305SZC-1, CY2305SZC-1T, CY2305SZI-1, CY2305SZI-1T, CY2305SZC-1H, CY2305SZC-1HT, CY2305SZI-1H, CY2305SZI-1HT, CY2309SZC-1, CY2309SZC-1T, CY2309SZI-1, CY2309SZI-1T, CY2309SZC-1H, CY2309SZC-1HT, CY2309SZI-1H, CY2309SZI-1HT, CY2309ZZC-1H, CY2309ZZC-1HT, CY2309ZI-1H, CY2309ZI-1HT, CY2309ZZI-1H, and CY2309ZZI-1HT in Ordering Information table. Changed Lead-Free to Pb-Free. Removed part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1, CY2305ESXI-1T, CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H, CY2305ESXI-1HT, CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1, CY2309ESXI-1T, CY2309ESXC-1H, CY2309ESXC-1HT, CY2309ESXI-1H, CY2309ESXI-1HT, CY2309EZXC-1H, CY2309EZXC-1HT, CY2309EZXI-1H, and CY2309EZXI-1HT in ordering information table. Removed note references to note 10 in Pb-Free sections of ordering information table. Changed IDD (PD mode) from 12.0 to 25.0 μA for commercial temperature devices Deleted Duty Cycle parameters for Fout < 50 MHz commercial and industrial devices. Reverted IDD (PD mode) and Duty Cycle parameters back to the values in revision *H: Changed IDD (PD mode) from 25 to 12 μA for commercial devices. Added Duty Cycle parameters for Fout < 50 MHz for commercial and industrial devices. *B 117625 HWT 10/21/02 *C *D *E *F *G *H 121828 131503 214083 291099 390582 2542461 RBI RGL RGL RGL RGL AESA 12/14/02 12/12/03 See ECN See ECN See ECN 07/23/08 *I 2565153 AESA 09/18/08 *J 2673353 KVM/PYRS 03/13/09 Document Number : 38-07140 Rev. *M Page 18 of 19 [+] Feedback CY2305, CY2309 Document Title: CY2305/CY2309 Low Cost 3.3-V Zero Delay Buffer Document Number: 38-07140 Rev. *K ECN 2904641 Orig. of Change KVM Submission Date 04/05/10 Description of Change Removed parts CY2305SI-1,CY2305SI-1T,CY2309SI-1,CY2309SI-1H,CY2309SI-1HT,CY2309 SI-1T from Ordering Information. Updated Package Diagram *L *M 3047136 3146330 KVM CXQ 10/04/2010 Added table of contents, ordering code definition, Acronyms and Units tables. Updated 16-pin TSSOP package diagram. 01/18/2011 Added “Not recommended for new designs” statement to Features on page 1. Added ‘not recommended for new designs’ footnote to all parts in the ordering information table. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2001-2011. 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Document Number : 38-07140 Rev. *M Revised January 28, 2011 Page 19 of 19 All product and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback