CY2308SI-3

CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low-skew outputs • Two banks of four outputs, three-stateable by two select inputs • 10-MHz to 133-MHz operating range • 75ps typical cycle-to-cycle jitter (15pF, 66MHz) • Space-saving 16-pin 150-mil SOIC package or 16-pin TSSOP • 3.3V operation • Industrial Temperature available Functional Description The CY2308 is a 3.3V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 200 ps. Input Decoding.” If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The CY2308 PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 50 µA of current draw. The PLL shuts down in two additional cases as shown in the “Select Input Decoding” table. Multiple CY2308 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY2308 is available in five different configurations, as shown in the “Available CY2308 Configurations” table on page 2. The CY2308–1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The CY2308–1H is the high-drive version of the –1, and rise and fall times on this device are much faster. The CY2308–2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The CY2308–3 allows the user to obtain 4X and 2X frequencies on the outputs. The CY2308–4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications. The CY2308–5H is a high-drive version with REF/2 on both banks. The CY2308 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the table “Select Pin Configuration Block Diagram /2 REF PLL FBK MUX /2 CLKA1 CLKA2 Extra Divider (–3, –4) CLKA3 Extra Divider (–5H) S2 S1 SOIC Top View CLKA4 Select Input Decoding /2 CLKB1 REF CLKA1 1 16 2 15 CLKA2 VDD 3 14 4 13 GND CLKB1 CLKB2 S2 5 12 6 11 7 10 8 9 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 CLKB2 CLKB3 Extra Divider (–2, –3) Cypress Semiconductor Corporation Document #: 38-07146 Rev. *D CLKB4 • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 19, 2005 [+] Feedback CY2308 Pin Description Pin Signal Description [1] 1 REF 2 CLKA1[2] Input reference frequency, 5V tolerant input Clock output, Bank A 3 [2] CLKA2 Clock output, Bank A 4 VDD 3.3V supply 5 GND Ground 6 CLKB1[2] Clock output, Bank B 7 CLKB2[2] Clock output, Bank B 8 S2[3] Select input, bit 2 [3] 9 S1 Select input, bit 1 10 CLKB3[2] Clock output, Bank B 11 CLKB4[2] Clock output, Bank B 12 GND Ground 13 VDD 3.3V supply 14 CLKA3[2] Clock output, Bank A 15 CLKA4[2] Clock output, Bank A 16 FBK PLL feedback input Select Input Decoding S2 S1 CLOCK A1–A4 CLOCK B1–B4 Output Source PLL Shutdown 0 0 Three-State Three-State PLL Y 0 1 Driven Three-State PLL N Driven[4] Reference Y Driven PLL N 1 0 1 1 Driven [4] Driven Available CY2308 Configurations Device Feedback From Bank A Frequency Bank B Frequency CY2308–1 Bank A or Bank B Reference Reference CY2308–1H Bank A or Bank B Reference Reference CY2308–2 Bank A Reference Reference/2 CY2308–2 Bank B 2 X Reference Reference CY2308–3 Bank A 2 X Reference Reference or Reference[5] CY2308–3 Bank B 4 X Reference 2 X Reference CY2308–4 Bank A or Bank B 2 X Reference 2 X Reference CY2308–5H Bank A or Bank B Reference /2 Reference /2 Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0. 5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2. Document #: 38-07146 Rev. *D Page 2 of 14 [+] Feedback CY2308 Zero Delay and Skew Control REF. Input to CLKA/CLKB Delay v/s Difference in Loading between FBK pin and CLKA/CLKB Pins To close the feedback loop of the CY2308, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above. Maximum Ratings For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. Storage Temperature .................................. –65°C to +150°C Supply Voltage to Ground Potential................–0.5V to +7.0V DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V DC Input Voltage REF ........................................... –0.5 to 7V Junction Temperature .................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V For zero output-output skew, be sure to load outputs equally. For further information on using CY2308, refer to the application note “CY2308: Zero Delay Buffer.” Operating Conditions for CY2308SC-XX Commercial Temperature Devices Parameter Description Min. Max. Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) 0 70 °C CL Load Capacitance, below 100 MHz – 30 pF Load Capacitance, from 100 MHz to 133 MHz – 15 pF Capacitance[6] CIN Input tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) – 7 pF 0.05 50 ms Note: 6. Applies to both Ref Clock and FBK. Document #: 38-07146 Rev. *D Page 3 of 14 [+] Feedback CY2308 Electrical Characteristics for CY2308SC-XX Commercial Temperature Devices Parameter Description Test Conditions Min. Max. Unit VIL Input LOW Voltage – 0.8 V VIH Input HIGH Voltage 2.0 – V IIL Input LOW Current VIN = 0V – 50.0 µA IIH Input HIGH Current VIN = VDD – 100.0 µA VOL Output LOW Voltage[7] IOL = 8 mA (–1, –2, –3, –4) IOL = 12 mA (–1H, –5H) – 0.4 V VOH Output HIGH Voltage[7] IOH = –8 mA (–1, –2, –3, –4) IOH = –12 mA (–1H, –5H) 2.4 – V IDD (PD mode) Power Down Supply Current REF = 0 MHz – 12.0 µA IDD Supply Current Unloaded outputs, 100-MHz REF, Select inputs at VDD or GND – 45.0 mA – 70.0 (–1H,–5H) mA Unloaded outputs, 66-MHz REF (–1, –2, –3, –4) – 32.0 mA Unloaded outputs, 33-MHz REF (–1, –2, –3, –4) – 18.0 mA Note: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07146 Rev. *D Page 4 of 14 [+] Feedback CY2308 Switching Characteristics for CY2308SC-XX Commercial Temperature Devices [8] Min. Typ. Max. Unit t1 Parameter Output Frequency Name 30-pF load, All devices Test Conditions 10 – 100 MHz t1 Output Frequency 20-pF load, –1H, –5H devices[9] 10 – 133.3 MHz t1 Output Frequency 15-pF load, –1, –2, –3, –4 devices 10 – 133.3 MHz Duty Cycle[7] = t2 ÷ t1 (–1, –2, –3, –4, –1H, –5H) Measured at 1.4V, FOUT = 66.66 MHz 30-pF load 40.0 50.0 60.0 % Duty Cycle[7] = t2 ÷ t1 (–1, –2, –3, –4, –1H, –5H) Measured at 1.4V, FOUT