CY2309SI-1HT

CY2305 CY2309 Low-cost 3.3V Zero Delay Buffer Features • 10-MHz to 100-/133-MHz operating range, compatible with CPU and PCI bus frequencies • Zero input-output propagation delay • Multiple low-skew outputs — Output-output skew less than 250 ps — Device-device skew less than 700 ps — One input drives five outputs (CY2305) — One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309) • Less than 200 ps cycle-cycle jitter, compatible with Pentium-based systems • Test Mode to bypass phase-locked loop (PLL) (CY2309 only [see “Select Input Decoding” on page 2]) • Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil SOIC package (CY2305) • 3.3V operation • Industrial temperature available up to 100-/133-MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY2309 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the “Select Input Decoding” table on page 2. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The CY2305 and CY2309 PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 12.0 µA of current draw for commercial temperature devices and 25.0 µA for industrial temperature parts. The CY2309 PLL shuts down in one additional case as shown in the table below. Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. All outputs have less than 200 ps of cycle-cycle jitter. The input to output propagation delay on both devices is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps. The CY2305/CY2309 is available in two/three different configurations, as shown in the ordering information (page 10). The CY2305-1/CY2309-1 is the base part. The CY2305-1H/ CY2309-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1s. Functional Description The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions of each device operate at Block Diagram PLL REF CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 Select Input Decoding S1 2309-1 Pin Configuration SOIC/TSSOP Top View MUX REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 2309-2 S2 CLKB2 CLKB3 CLKB4 REF CLK2 CLK1 GND 1 2 3 4 SOIC Top View 8 7 6 5 CLKOUT CLK4 V DD CLK3 2309-3 Cypress Semiconductor Corporation Document #: 38-07140 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 14, 2002 CY2305 CY2309 Pin Description for CY2309 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF[1] CLKA1[2] CLKA2 VDD GND CLKB1[2] CLKB2[2] S2[3] S1 [3] [2] Signal Buffered clock output, Bank A Buffered clock output, Bank A 3.3V supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Select input, bit 2 Select input, bit 1 Buffered clock output, Bank B Buffered clock output, Bank B Ground 3.3V supply Buffered clock output, Bank A Buffered clock output, Bank A [2] Description Input reference frequency, 5V-tolerant input CLKB3[2] CLKB4 GND VDD CLKA3[2] CLKA4[2] CLKOUT[2] Buffered output, internal feedback on this pin Pin Description for CY2305 Pin 1 2 3 4 5 6 7 8 REF[1] CLK2[2] CLK1[2] GND CLK3[2] VDD CLK4[2] CLKOUT[2] Signal Buffered clock output Buffered clock output Ground Buffered clock output 3.3V supply Buffered clock output Buffered clock output, internal feedback on this pin Description Input reference frequency, 5V-tolerant input Select Input Decoding for CY2309 S2 0 0 1 1 S1 0 1 0 1 CLOCK A1–A4 Three-state Driven Driven Driven CLOCK B1–B4 Three-state Three-state Driven Driven CLKOUT[4] Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown N N Y N Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Document #: 38-07140 Rev. *C Page 2 of 13 CY2305 CY2309 REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. If input to output delay adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs. For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note entitled “CY2305 and CY2309 as PCI and SDRAM Buffers.” Document #: 38-07140 Rev. *C Page 3 of 13 CY2305 CY2309 Maximum Ratings Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage (Except REF) ............–0.5V to VDD + 0.5V DC Input Voltage REF......................................... –0.5V to 7V Storage Temperature ................................. –65°C to +150°C Junction Temperature ................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ........................... > 2,000V Min. 3.0 0 Max. 3.6 70 30 10 7 0.05 50 Unit V °C pF pF pF ms Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices Parameter VDD TA CL CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Description Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage[5] Input HIGH Voltage[5] VIN = 0V VIN = VDD IOL = 8 mA (–1) IOH = 12 mA (–1H) IOH = –8 mA (–1) IOL = –12 mA (–1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VDD 2.4 12.0 32.0 2.0 50.0 100.0 0.4 Input LOW Current Input HIGH Current Output LOW Voltage[6] Output HIGH Voltage[6] Power Down Supply Current Supply Current Test Conditions Min. Max. 0.8 Unit V V µA µA V V µA mA Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature Devices[7] Parameter t1 Name Output Frequency Duty Cycle[6] = t2 ÷ t1 t3 t4 t5 t6A t6B t7 tJ tLOCK Rise Time [6] Test Conditions 30-pF load 10-pF load Measured at 1.4V, Fout = 66.67 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Skew[6] All outputs equally loaded Min. 10 10 40.0 Typ. Max. 100 133.33 Unit MHz MHz % ns ns ps ps ns ps ps ms 50.0 60.0 2.50 2.50 250 Fall Time[6] Output to Output Delay, REF Rising Edge to Measured at VDD/2 CLKOUT Rising Edge[6] Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL CLKOUT Rising Edge[6] Bypass Mode, CY2309 device only. Device to Device Skew[6] Cycle to Cycle Jitter[6] PLL Lock Time[6] Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin 1 0 5 0 ±350 8.7 700 200 1.0 Notes: 5. REF input has a threshold voltage of VDD/2. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. 7. All parameters specified with loaded outputs. Document #: 38-07140 Rev. *C Page 4 of 13 CY2305 CY2309 Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices[7] Parameter t1 Name Output Frequency Duty Cycle[6] = t2 ÷ t1 Duty Cycle t3 t4 t5 t6A t6B t7 t8 tJ tLOCK [6] Description 30-pF load 10-pF load Measured at 1.4V, Fout = 66.67 MHz Measured at 1.4V, Fout