CY2313ANZ

1CY2310NZCY2310 NZCY2313ANZ CY2313ANZ 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Features • One input to 13 output buffer/driver • Supports up to three SDRAM DIMMs • One additional outputs for feedback • Serial interface for output control • Low skew outputs • Up to 100-MHz operation • Multiple VDD and VSS pins for noise reduction • Low EMI outputs • 28-pin SOIC (300-mil) package • 3.3V operation Functional Description The CY2313ANZ is a 3.3V buffer designed to distribute high-speed clocks in desktop PC applications. The part has 13 outputs, 12 of which can be used to drive up to three SDRAM DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium® II processors. The CY2313ANZ can be used in conjunction with the CY2280, CY2281, CY2282 or similar clock synthesizer for a complete Pentium II motherboard solution. The CY2313ANZ also includes a serial interface which can enable or disable each output clock. On power-up, all output clocks are enabled. Block Diagram Pin Configuration BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN SDRAM4 SDRAM5 SDRAM12 VDDIIC SDATA 28 SOIC Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SDATA Serial Interface Decoding SCLOCK VDD SDRAM11 SDRAM10 VSS VDD SDRAM9 SDRAM8 VSS VDD SDRAM7 SDRAM6 VSS VSSIIC SCLK Pentium is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07144 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised July 09, 2007 CY2313ANZ Pin Summary Name VDD VSS VDDIIC VSSIIC BUF_IN SDATA SCLK SDRAM [0-12] Pins 1, 5, 20, 24, 28 4, 8, 17, 21, 25 13 16 9 14 15 2, 3, 6, 7, 10, 11, 12, 18, 19, 22, 23, 26, 27 Description 3.3V Digital voltage supply Ground Serial interface voltage supply Ground for serial interface Input clock Serial data input, internal pull-up to VDD Serial clock input, internal pull-up to VDD SDRAM clock outputs Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits should be programmed to “0” • Serial interface address for the CY2313ANZ is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ---- Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 27 26 23 22 --19 18 Description SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Reserved, drive to 0 Reserved, drive to 0 SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) Byte 0:SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enabled Bit Pin # Description SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Reserved, drive to 0 Reserved, drive to 0 SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Bit 7 11 Bit 6 10 Bit 5 -Bit 4 -Bit 3 7 Bit 2 6 Bit 1 3 Bit 0 2 Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -12 ------Pin # Description Reserved, drive to 0 SDRAM12 (Active/Inactive) Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Document #: 38-07144 Rev. *B Page 2 of 8 CY2313ANZ Maximum Ratings Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage (Except BUF_IN)........–0.5V to VDD + 0.5V DC Input Voltage (BUF_IN)............................ –0.5V to +7.0V Storage Temperature ................................. –65°C to +150°C Junction Temperature................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions[1] Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min. 3.135 0 Max. 3.465 70 30 7 50 Unit V °C pF pF ms Electrical Characteristics Over the Operating Range Parameter VIL VILiic VIH IIL IIL IIH VOL VOH IDD IDD IDD IDD IDDS Description Input LOW Voltage[2] Input LOW Voltage Input HIGH Voltage[2] Input LOW Current (BUF_IN input) Input LOW Current (Except BUF_IN Pin) Input HIGH Current Output LOW Voltage[3] Output HIGH Supply Supply Supply Voltage[3] Current[3] Current[3] Current[3] VIN = 0V VIN = 0V VIN = VDD IOL = 25 mA IOH = –36 mA Unloaded outputs, 100 MHz Loaded outputs, 100 MHz Unloaded outputs, 66.67 MHz Loaded outputs, 66.67 MHz BUF_IN=VDD or VSS All other inputs at VDD 2.4 200 290 150 185 500 –10 Test Conditions Except serial interface pins For serial interface pins only 2.0 –10 10 100 10 0.4 Min. Max. 0.8 0.7 Unit V V V μA μA μA V V mA mA mA mA μA Supply Current[3] Supply Current Notes: 1. Electrical parameters are guaranteed under the operating conditions specified. 2. BUF_IN input has a threshold voltage of VDD/2. 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07144 Rev. *B Page 3 of 8 CY2313ANZ Switching Characteristics[4] Over the Operating Range Parameter Name Maximum Operating Frequency Duty Cycle[3,5] = t2 ÷ t1 t3 t4 t5 t6 t7 t8 t9 Rising Edge Rate [3] [3] [3] Test Conditions Measured at 1.5V Measured between 0.4V and 2.4V Measured between 2.4V and 0.4V All outputs equally loaded Input edge greater than 1 V/ns Input edge greater than 1 V/ns Input edge greater than 1 V/ns Input edge greater than 1 V/ns Min. 45.0 0.9 0.9 –250 1.0 1.0 1.0 1.0 Typ. 50.0 1.5 1.5 3.5 3.5 5 20 Max. 100 55.0 4.0 4.0 +250 5.0 5.0 12 30 Unit MHz % V/ns V/ns ps ns ns ns ns Falling Edge Rate Output to Output Skew SDRAM Buffer LH Prop. Delay[3] SDRAM Buffer HL Prop. Delay[3] SDRAM Buffer Enable Delay [3] [3] SDRAM Buffer Disable Delay Notes: 4. All parameters specified with loaded outputs. 5. Duty cycle of input clock is 50%. Rising and falling edge rate of the input clock is greater than 1 V/ns. Switching Waveforms Duty Cycle Timing t1 t2 1.5V 1.5V 1.5V All Outputs Rise/Fall Time 2.4V 0.4V t3 2.4V 0.4V t4 3.3V 0V OUTPUT Output-Output Skew OUTPUT 1.5V OUTPUT t5 1.5V Document #: 38-07144 Rev. *B Page 4 of 8 CY2313ANZ Switching Waveforms (continued) SDRAM Buffer LH and HL Propagation Delay INPUT OUTPUT t6 t7 SDRAM Buffer Enable and Disable Times OE Three-State OUTPUTS t8 Active t9 Test Circuit VDD 0.1 μF OUTPUTS CLK out CLOAD GND Document #: 38-07144 Rev. *B Page 5 of 8 CY2313ANZ Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. Application Circuit Rs CPUCLK PCICLK USBCLK REF APIC BUF_IN Rs SDATA SCLK V DD 3.3V Ct V DD SDATA SCLK SDRAM ( 0-12) SDRAM ( 0-12) * CY2280 48 PIN SSOP (or CY2281 or CY2282) Cd 0.1uF V SS CY2313 28-PIN SOIC CY2313A:28 PIN SOIC * THIS FREQUENCY SYNTHESIZER IS USED TO GENERATE CPU, PCI, USB, REF, AND APIC CLOCKS. Cd = DECOUP LING CAPACITOR S Ct = O PTIONAL EMI-R EDUCING CAP ACI TORS Rs = SERIES TERMINATING RESISTORS Summary • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 μF. In some cases, smaller value capacitors may be required. • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout and Termination Techniques for Cypress Clock Generators” for more details. • If a Ferrite Bead is used, a 10 μF–22 μF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Ordering Information Ordering Code CY2313ANZSC–1 Pb-free CY2313ANZSXC–1 CY2313ANZSXC–1T S21 S21 28-Pin SOIC 28-Pin SOIC Tape and Reel Commercial Commercial Package Name S21 Package Type 28-Pin SOIC Operating Range Commercial Document #: 38-07144 Rev. *B Page 6 of 8 CY2313ANZ Package Diagram 28-Lead (300-Mil) Molded SOIC S21 Document #: 38-07144 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2313ANZ Document History Page Document Title: CY2313ANZ 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Document Number: 38-07144 REV. ** *A *B ECN NO. 110253 121831 1244583 Issue Date 11/18/01 12/14/02 See ECN Orig. of Change DSG RBI DPF Description of Change Change from Spec number: 38-00692 to 38-07144 Power up requirements added to Operating Conditions Information Added Pb-free part numbers in the Ordering Information Document #: 38-07144 Rev. *B Page 8 of 8