CY2318BNZPVI-11

CY2318BNZ 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs Features • One input to 18 output buffer/driver • Supports up to four SDRAM DIMMs • Two additional outputs for feedback • SMBus interface for individual output control • Low skew outputs (< 200 ps) • Up to 100 MHz operation for Industrial temperatures • Up to 133 MHz operation for Commercial temperatures • Dedicated OE pin for testing • Space-saving 48-pin SSOP package • 3.3V operation Functional Description The CY2318BNZ is a 3.3V buffer designed to distribute high-speed clocks in PC applications. The part has 18 outputs, 16 of which can be used to drive up to four SDRAM DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium II® processors. The CY2318BNZ can be used in conjunction with the CY2280, CY2281, CY2282 or similar clock synthesizer for a complete Pentium II motherboard solution. The CY2318BNZ also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull up). A separate Output Enable pin facilitates testing on ATE. Block Diagram Pin Configuration SSOP Top View BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17 OE SDATA SMBus Decoding SCLOCK NC NC VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD SDRAM4 SDRAM5 VSS VDD SDRAM6 SDRAM7 VSS VDD SDRAM16 VSS VDDIIC SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC VDD SDRAM15 SDRAM14 VSS VDD SDRAM13 SDRAM12 VSS OE VDD SDRAM11 SDRAM10 VSS VDD SDRAM9 SDRAM8 VSS VDD SDRAM17 VSS VSSIIC SCLOCK Pentium II is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07217 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 4, 2001 CY2318BNZ Pin Summary Name VDD VSS VDDIIC VSSIIC BUF_IN OE SDATA SCLK SDRAM [0–3] SDRAM [4–7] SDRAM [8–11] SDRAM [12–15] SDRAM [16–17] N/C Pins 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 23 26 11 38 24 25 4, 5, 8, 9 13, 14, 17, 18 31, 32, 35, 36 40, 41, 44, 45 21, 28 1, 2, 47, 48 Description 3.3V Digital voltage supply SMBus Voltage supply Ground for SMBus Input clock (5V tolerant) Output Enable (active HIGH), Three-state outputs when LOW[1] SMBus data input[1] SMBus clock input[1] SDRAM byte 0 clock outputs SDRAM byte 1 clock outputs SDRAM byte 2 clock outputs SDRAM byte 3 clock outputs SDRAM clock outputs usable for feedback Reserved for future modifications, do not connect in system 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 Ground Note: 1. Internal pull-up resistor to VDD (value > 100 kohms). Device Functionality OE 0 1 SDRAM [0–17] Hi-Z 1 x BUF_IN Document #: 38-07217 Rev. ** Page 2 of 8 CY2318BNZ Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits should be programmed to “0”. • SMBus Address for the CY2318BNZ is: • • Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 45 44 41 40 36 35 32 31 Description SDRAM15 (Active/Inactive) SDRAM14 (Active/Inactive) SDRAM13 (Active/Inactive) SDRAM12 (Active/Inactive) SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) A6 1 • • A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ---- Byte 0:SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 21 ------Description SDRAM17 (Active/Inactive) SDRAM16 (Active/Inactive) Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Bit 7 18 Bit 6 17 Bit 5 14 Bit 4 13 Bit 3 9 Bit 2 8 Bit 1 5 Bit 0 4 Maximum Ratings Supply Voltage to Ground Potential .................. –0.5 to +7.0V DC Input Voltage (except BUF_IN) .......... –0.5V to VDD + 0.5 DC Input Voltage (BUF_IN).............................. –0.5V to 7.0V Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage (per MIL-STD-883, Method 3015)..............................>2000V Ambient Temperature under BIAS .............. –55°C to +125°C Parameter VDD, VIN TSTG TA TB Description Voltage on Any Pin with Respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating –0.5 to +7.0 –65 to +150 0 to +70 –55 to +125 Unit V °C °C °C Operating Conditions Parameter VDD, VDDIIC TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Description Min. 3.135 –40 20 Max. 3.465 85 30 7 Unit V °C pF pF Page 3 of 8 Document #: 38-07217 Rev. ** CY2318BNZ DC Electrical Characteristics: TA = -40°C to +85°C, VDDQ3 = 3.3V±5% Parameter IDD IDD Tristate VIL VIH IILEAK IILEAK VOL VOH IOL IOH CIN COUT LIN Description 3.3V Supply Current 3.3V Supply Current in Three-state Input Low Voltage Input High Voltage Input Leakage Current, BUF_IN Input Leakage Current Output Low Voltage Output High Voltage Output Low Current Output High Current Input Pin Capacitance (Except BUF_IN) Output Pin Capacitance Input Pin Inductance [2] Test Condition/ Comments BUF_IN = 64 MHz BUF_IN = 100 MHz Min 140 Typ 165 5 Max 200 Unit mA mA Logic Inputs (BUF_IN, OE, SCLOCK, SDATA) GND–0.3 2.0 –5 –20 IOL = 1 mA IOH = –1 mA VOL = 1.5V VOH = 1.5V 3.1 70 65 110 100 185 160 5 6 7 0.8 VDDQ3 + 0.5 +5 +5 50 V V µA µA mV V mA mA pF pF nH Logic Outputs (SDRAM0:17)[3] Pin Capacitance/Inductance Document #: 38-07217 Rev. ** Page 4 of 8 CY2318BNZ AC Electrical Characteristics: TA = –40°C to +85°C, VDDQ3 = 3.3V±5% (Lump Capacitance Test Load = 30 pF) Parameter fIN tR tF tSR tSF tEN tDIS tPR tPF tD Zo Description Input Frequency Output Rise Edge Rate Output Fall Edge Rate Output Skew, Rising Edges Output Skew, Falling Edges Output Enable Time Output Disable Time Rising Edge Propagation Delay Falling Edge Propagation Delay Duty Cycle AC Output Impedance Measured at 1.5V 1.0 1.0 3.0 3.0 50 15 3.85 3.85 Test Condition Commercial Temperature Range Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Min 0 1.5 1.5 Typ Max 133 4.0 4.0 200 200 8.0 8.0 5.0 5.0 60 Unit MHz V/ns V/ns ps ps ns ns ns ns % Ω Notes: 2. OE, SCLOCK, and SDATA logic pins have a 250-kΩ internal pull-up resistor (not CMOS level). 3. Outputs loaded by 6" 60Ω transmission lines with 20-pF capacitors. Test Circuit VDD 0.1 µF OUTPUTS CLK out CLOAD GND Document #: 38-07217 Rev. ** Page 5 of 8 CY2318BNZ Application Circuit Rs CPUCLK PCICLK USBCLK REF APIC BUF_IN Rs SDATA SCLK V DD 3.3V Ct V DD SDATA SCLK SDRAM ( 0-12) SDRAM ( 0-12) * CY2280 48 PIN SSOP (or CY2281 or CY2282) Cd 0.1uF V SS CY2313 28-PIN SOIC CY2313A:28 PIN SOIC * THIS FREQUENCY SYNTHESIZER IS USED TO GENERATE CPU, PCI, USB, REF, AND APIC CLOCKS. Cd = DECOUP LING CAPACITOR S Ct = O PTIONAL EMI-R EDUCING CAP ACI TORS Rs = SERIES TERMINATING RESISTORS Ordering Information Ordering Code CY2318BNZPVI-11 CY2318BNZPVC-11 Package Name O48 O48 Package Type 48-Pin SSOP 48-Pin SSOP Operating Range Industrial (–40°C to 85°C) Commercial (0°C to 70°C) Package Diagram Document #: 38-07217 Rev. ** Page 6 of 8 CY2318BNZ 48-Lead Shrunk Small Outline Package O48 51-85061-B Document #: 38-07217 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2318BNZ Revision History Document Title: CY2318BNZ 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs Document Number: 38-07217 REV. ** ECN NO. 111855 Issue Date 12/09/01 Orig. of Change DSG Description of Change Change from Spec number: 38-01091 to 38-07217 Document #: 38-07217 Rev. ** Page 8 of 8