CY23FP12
200 MHz Field Programmable
Zero Delay Buffer
200 MHz Field Programmable Zero Delay Buffer
Features
Functional Description
■
Fully field-programmable
❐ Input and output dividers
❐ Inverting/non-inverting outputs
❐ Phase-locked loop (PLL) or fanout buffer configuration
■
10 MHz to 200 MHz operating range
■
Split 2.5 V or 3.3 V outputs
■
Two LVCMOS reference inputs
■
Twelve low skew outputs
❐ 35 ps typical output-to-output skew (same frequency)
■
110 ps typical cycle-cycle jitter (same frequency)
■
Three-stateable outputs
■
Less than 50 A shutdown current
■
Spread aware
■
28-pin SSOP
■
3.3 V operation
■
Industrial temperature available
The CY23FP12 is a high performance fully field-programmable
200 MHz zero delay buffer designed for high speed clock
distribution. The integrated PLL is designed for low jitter and
optimized for noise rejection. These parameters are critical for
reference clock distribution in systems using high performance
ASICs and microprocessors.
The CY23FP12 is fully programmable through volume or
prototype programmers, enabling the user to define an
application-specific Zero Delay Buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions listed in Table 2,
and assign a particular function set to any one of the four
possible S1-S2 control bit combinations. This feature enables
the implementation of four distinct personalities, selectable with
S1-S2 bits, on a single programmed silicon. The CY23FP12 also
features a proprietary auto power down circuit that shuts down
the device in case of a REF failure, resulting in less than 50 A
of current draw.
The CY23FP12 provides 12 outputs grouped in two banks with
separate power supply pins which can be connected
independently to either a 2.5 V or a 3.3 V rail.
Selectable reference input is a fault tolerance feature which
enables glitch-free switch over to a secondary clock source when
REFSEL is asserted/de-asserted.
For a complete list of related documentation, click here.
Logic Block Diagram
VDDA
VDDC
CLKA0
Lock Detect
CLKA1
CLKA2
CLKA3
REFSEL
CLKA4
REF1
REF2
FBK
M
N
100 to
400M Hz
PLL
1
2
CLKA5
VSSA
3
VDDB
4
CLKB0
X
CLKB1
CLKB2
CLKB3
Test Logic
S[2:1]
CLKB4
Function
Selection
CLKB5
VSSC
Cypress Semiconductor Corporation
Document Number: 38-07246 Rev. *K
VSSB
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 17, 2017
CY23FP12
Contents
Pin Configuration ............................................................. 3
Pin Description ................................................................. 4
Basic PLL Block Diagram ................................................ 5
Programmable Functions ................................................ 6
Field Programming the CY23FP12 ............................. 8
CyberClocks Software .............................................. 8
CY3672-USB Development Kit ................................... 8
CY23FP12 Frequency Calculation .................................. 8
Absolute Maximum Conditions ....................................... 9
Operating Conditions ....................................................... 9
DC Electrical Specifications .......................................... 10
Thermal Resistance ........................................................ 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 13
Test Circuits .................................................................... 14
Document Number: 38-07246 Rev. *K
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Drawing and Dimensions ............................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY23FP12
Pin Configuration
Figure 1. 28-pin SSOP pinout
Top View
Document Number: 38-07246 Rev. *K
REF2
REF1
1
28
2
27
CLKB0
CLKB1
3
26
4
25
VSSB
CLKB2
5
24
6
23
CLKB3
VDDB
VSSB
CLKB4
CLKB5
VDDB
VDDC
S2
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
REFSEL
FBK
CLKA0
CLKA1
VSSA
CLKA2
CLKA3
VDDA
VSSA
CLKA4
CLKA5
VDDA
VSSC
S1
Page 3 of 19
CY23FP12
Pin Description
Pin No.
Name
I/O
Type
Description
1
REF2
I
LVTTL/LVCMOS Input reference frequency, 5 V tolerant input.
2
REF1
I
LVTTL/LVCMOS Input reference frequency, 5 V tolerant input.
3
CLKB0
O
LVTTL
Clock output, Bank B.
4
CLKB1
O
LVTTL
Clock output, Bank B.
5
VSSB
PWR
POWER
Ground for Bank B.
6
CLKB2
O
LVTTL
Clock output, Bank B.
7
CLKB3
O
LVTTL
Clock output, Bank B.
8
VDDB
PWR
POWER
2.5 V or 3.3 V supply, Bank B.
9
VSSB
PWR
POWER
Ground for Bank B.
10
CLKB4
O
LVTTL
Clock output, Bank B.
11
CLKB5
O
LVTTL
Clock output, Bank B.
12
VDDB
PWR
POWER
2.5 V or 3.3 V supply, Bank B.
13
VDDC
PWR
POWER
3.3 V core supply.
14
S2
I
LVTTL
Select input.
15
S1
I
LVTTL
Select input.
16
VSSC
PWR
POWER
Ground for core.
17
VDDA
PWR
POWER
2.5 V or 3.3 V supply, Bank A.
18
CLKA5
O
LVTTL
Clock output, Bank A.
19
CLKA4
O
LVTTL
Clock output, Bank A.
20
VSSA
PWR
POWER
Ground for Bank A.
21
VDDA
PWR
POWER
2.5 V or 3.3 V supply Bank A.
22
CLKA3
O
LVTTL
Clock output, Bank A.
23
CLKA2
O
LVTTL
Clock output, Bank A.
24
VSSA
PWR
POWER
Ground for Bank A.
25
CLKA1
O
LVTTL
Clock output, Bank A.
26
CLKA0
O
LVTTL
CLock output, Bank A.
27
FBK
I
LVTTL
PLL feedback input.
28
REFSEL
I
LVTTL
Reference select input. When REFSEL = 0, REF1 is selected.
When REFSEL = 1, REF2 is selected.
Document Number: 38-07246 Rev. *K
Page 4 of 19
CY23FP12
Basic PLL Block Diagram
CLKB5
/1,/2,/3,/4,
/x,/2x
CLKB4
/1,/2,/3,/4,
/x,/2x
REF
/M
/1,/2,/3,/4,
/x,/2x
PLL
FBK
/N
Document Number: 38-07246 Rev. *K
/1,/2,/3,/4,
/x,/2x
CLKB3
CLKB2
Output
CLKB1
Function
CLKB0
Select
CLKA5
Matrix
CLKA4
/1,/2,/3,/4,
/x,/2x
CLKA3
/1,/2,/3,/4,
/x,/2x
CLKA1
CLKA2
CLKA0
Page 5 of 19
CY23FP12
Programmable Functions
The following table lists independent functions that can be programmed with a volume or prototype programmer on the “default” silicon.
Table 1. Programmable Functions
Configuration
Description
Default
DC Drive Bank A
Programs the drive strength of Bank A outputs. The user can select one out of two possible +16 mA
drive strength settings that produce output DC currents in the range of ±16 mA to ±20 mA.
DC Drive Bank B
Programs the drive strength of Bank B outputs. The user can select one out of two possible +16 mA
drive strength settings that produce output DC currents in the range of ±16 mA to ±20 mA.
Output Enable for Bank B Enables/Disables CLKB[5:0] outputs. Each of the six outputs can be disabled individually Enable
clocks
if not used, to minimize electromagnetic interference (EMI) and switching noise.
Output Enable for Bank A Enables/Disables CLKA[5:0] outputs. Each of the six outputs can be disabled individually Enable
clocks
if not used, to minimize EMI and switching noise.
Inv CLKA0
Generates an inverted clock on the CLKA0 output. When this option is programmed,
CLKA0 and CLKA1 will become complimentary pairs.
Non-invert
Inv CLKA2
Generates an inverted clock on the CLKA2 output. When this option is programmed,
CLKA2 and CLKA3 will become complimentary pairs.
Non-invert
Inv CLKA4
Generates an inverted clock on the CLKA4 output. When this option is programmed,
CLKA4 and CLKA5 will become complimentary pairs.
Non-invert
Inv CLKB0
Generates an inverted clock on the CLKB0 output. When this option is programmed,
CLKB0 and CLKB1 will become complimentary pairs.
Non-invert
Inv CLKB2
Generates an inverted clock on the CLKB2 output. When this option is programmed,
CLKB2 and CLKB3 will become complimentary pairs.
Non-invert
Inv CLKB4
Generates an inverted clock on the CLKB4 output. When this option is programmed,
CLKB4 and CLKB5 will become complimentary pairs.
Non-invert
Pull-down Enable
Enables/Disables internal pulldowns on all outputs
Enable
Fbk Pull-down Enable
Enables/Disables internal pulldowns on the feedback path (applicable to both internal and Enable
external feedback topologies)
Fbk Sel
Selects between the internal and the external feedback topologies
Document Number: 38-07246 Rev. *K
External
Page 6 of 19
CY23FP12
Table 2 lists independent functions that can be assigned to each of the four S1 and S2 combinations. When a particular S1 and S2
combination is selected, the device assumes the configuration (which is essentially a set of functions given in Table 2) that has been
preassigned to that particular combination.
Table 2. Programmable Functions for S1/S2 Combinations
Function
Description
Default
Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair
See Table 4 on
page 8
Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair
See Table 4 on
page 8
Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair
See Table 4 on
page 8
Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair
See Table 4 on
page 8
Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair
See Table 4 on
page 8
Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair
See Table 4 on
page 8
Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising Enable
edges and shuts down the device in case of a reference “failure.” This failure is triggered
by a drift in reference frequency below a set limit. This auto power down circuit is disabled
internally when one or more of the outputs are configured to be driven directly from the
reference clock.
PLL Power-down
Shuts down the PLL when the device is configured as a non-PLL fanout buffer.
M[7:0]
Assigns an eight-bit value to reference divider –M. The divider can be any integer value 2
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
N[7:0]
Assigns an eight-bit value to feedback divider –N. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
X[6:0]
Assigns a seven-bit value to output divider –X. The divider can be any integer value from 1
5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be activated
by the appropriate output mux setting.
Divider Source
Selects between the PLL output and the reference clock as the source clock for the output See Table 4 on
dividers.
page 8
CLKA54 Source
Independently selects one out of the eight possible output dividers that will connect to the Divide by 2
CLKA5 and CLKA4 pair. Please refer to Table 3 on page 8 for a list of divider values.
CLKA32 Source
Independently selects one out of the eight possible output dividers that will connect to the Divide by 2
CLKA3 and CLKA2 pair. Please refer to Table 3 on page 8 for a list of divider values.
CLKA10 Source
Independently selects one out of the eight possible output dividers that will connect to the Divide by 2
CLKA1 and CLKA0 pair. Please refer to Table 3 on page 8 for a list of divider values.
CLKB54 Source
Independently selects one out of the eight possible output dividers that will connect to the Divide by 2
CLKB5 and CLKB4 pair. Please refer to Table 3 on page 8 for a list of divider values.
CLKB32 Source
Independently selects one out of the eight possible output dividers that will connect to the Divide by 2
CLKB3 and CLKB2 pair. Please refer to Table 3 on page 8 for a list of divider values.
CLKB10 Source
Independently selects one out of the eight possible output dividers that will connect to the Divide by 2
CLKB1 and CLKB0 pair. Please refer to Table 3 on page 8 for a list of divider values.
Document Number: 38-07246 Rev. *K
PLL Enabled
2
Page 7 of 19
CY23FP12
Table 3 is a list of output dividers that are independently selected
to connect to each output pair.
In the default (unprogrammed) state of the device, S1 and S2
pins will function as indicated in Table 4.
Table 3. Output Dividers
CLKA/B Source
Output Connects To
CyberClocks Software
CyberClocks is an easy-to-use software application that allows
the user to custom-configure the CY23FP12. Users can specify
the REF frequency, PLL frequency, output frequencies and/or
post-dividers, and different functional options. CyberClocks
outputs an industry standard JEDEC file used for programming
the CY23FP12.
CyberClocks can be downloaded free of charge from the
Cypress website at www.cypress.com.
0 [000]
REF
1 [001]
Divide by 1
CY3672-USB Development Kit
2 [010]
Divide by 2
3 [011]
Divide by 3
The Cypress CY3672-USB Development Kit, in combination with
the CY3692 Socket Adapter, is used to program samples and
small prototype quantities of the CY23FP12. This portable
programmer connects to a PC via a USB interface.
4 [100]
Divide by 4
5 [101]
Divide by X
6 [110]
Divide by 2X[1]
7 [111]
TEST mode [LOCK signal][2]
CY23FP12 Frequency Calculation
Table 4. S1/S2 Default Functionality
S2
S1
CLKA[5:0]
CLKB[5:0]
Divider
Source
0
0
Three-state
Three-state
PLL
0
1
Driven
Three-state
PLL
1
0
Driven
Driven
Reference
1
1
Driven
Driven
PLL
Field Programming the CY23FP12
The CY23FP12 must be programmed in a device programmer
prior to being installed in a circuit. The CY23FP12 is based on
flash technology, so it can be reprogrammed up to 100 times.
This enables fast and easy design changes and product
updates, and eliminates any issues with old and out-of-date
inventory.
Samples and small prototype quantities can be programmed on
the CY3672-USB programmer. Cypress’s value-added
distribution partners and third-party programming systems from
BP Microsystems, HiLo Systems, and others are available for
large production quantities.
The CY23FP12 is an extremely flexible clock buffer with up to
twelve individual outputs, generated from an integrated PLL.
Four variables are used to determine the final output frequency.
These are the input Reference Frequency, the M and N dividers,
and the post divider.
The basic PLL block diagram is shown in Basic PLL Block
Diagram on page 5. Each of the six clock output pairs has many
post divider options available to it. There are six post divider
options: /1, /2, /3, /4, /X, and /2X. X is a programmable value
between 5 and 130, and 2X is twice that value. The post divider
options can be applied to the calculated PLL frequency or to the
REF directly. The feedback is connected either internally to
CLKA0 or externally to any output.
A programmable divider, M, is inserted between the reference
input, REF, and the phase detector. The divider M can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
A programmable divider, N, is inserted between the feedback
input, FBK, and the phase detector. The divider N can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
The output can be calculated as follows:
FREF / M = FFBK / N.
FPLL = (FREF × N × post divider) / M.
FOUT = FPLL / post divider.
In addition to above divider options, the following option
bypasses the PLL and passes the REF directly to the output.
FOUT = FREF.
Notes
1. Outputs will be rising edge aligned only to those outputs using this same device setting.
2. When the source of an output pair is set to [111], the output pair becomes lock indicator signal. For example, if the source of an output pair (CLKA0, CLKA1) is set
to [111], the CLKA0 and CLKA1, becomes lock indicator signals. In non-invert mode, CLKA0 and CLKA1 signals will be high when the PLL is in lock mode. If CLKA0
is in an invert mode, the CLKA0 will be low and the CLKA1 will be high when the PLL is in lock mode.
Document Number: 38-07246 Rev. *K
Page 8 of 19
CY23FP12
Absolute Maximum Conditions
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Min
Max
Unit
VDD
Parameter
Supply voltage
Description
Non-functional
Condition
–0.5
7
VDC
VIN
Input voltage REF
Relative to VCC
–0.5
VDD + 0.5
VDC
VIN
Input voltage except REF
Relative to VCC
–0.5
VDD + 0.5
VDC
LUI
Latch-up immunity
Functional
TS
Temperature, storage
Non-functional
300
TJ
Junction temperature
ESDh
ESD protection (Human body
model)
MSL
Moisture sensitivity level
GATES
Total functional gate count
Assembled Die
UL–94
Flammability rating
At 1/8 in.
FIT
Failure in time
Manufacturing test
mA
–65
125
°C
–
125
°C
2000
V
MSL – 3
class
21375
each
V–0
class
10
ppm
Operating Conditions
Min
Max
Unit
VDDC
Parameter
Core supply voltage
3.135
3.465
V
VDDA, VDDB
Bank A, Bank B supply voltage
3.135
3.465
V
2.375
2.625
V
°C
TA
Description
Test Conditions
Temperature, operating ambient Commercial temperature
Industrial temperature
tPU
Power-up time for all VDDs to
reach minimum specified voltage
(power ramps must be
monotonic)
Document Number: 38-07246 Rev. *K
0
70
–40
85
0.05
500
ms
Page 9 of 19
CY23FP12
DC Electrical Specifications
Parameter
Description
VIL
Input LOW voltage[3]
VIH
[3]
IIL
Test Conditions
Input HIGH voltage
Input LOW current
Min
Typ
Max
Unit
–
–
0.3 × VDD
V
0.7 × VDD
–
–
V
50
A
[3]
VIN = 0 V
–
–
[3]
IIH
Input HIGH current
VIN = VDD
–
–
50
A
VOL
Output LOW voltage[4]
VDDA/VDDB = 3.3 V,
IOL = 16 mA (standard drive)
VDDA/VDDB = 3.3 V,
IOL = 20 mA (high drive)
VDDA/VDDB = 2.5 V,
IOL = 16 mA (high drive)
–
–
0.5
V
VOH
Output HIGH voltage[4]
VDDA/VDDB = 3.3 V,
IOH = –16 mA (standard drive)
VDDA/VDDB = 3.3 V,
IOH = –20 mA (high drive)
VDDA/VDDB = 2.5 V,
IOH = –16 mA (high drive)
VDD – 0.5
–
–
V
IDDS
Power-down supply current
REF = 0 MHz
–
12
50
A
IDD
Supply current
VDDA = VDDB = 2.5 V,
Unloaded outputs at 166 MHz
–
40
65
mA
VDDA = VDDB = 2.5 V,
Loaded outputs at 166 MHz,
CL = 15 pF
–
65
100
VDDA = VDDB = 3.3 V,
Unloaded outputs at 166 MHz
–
50
80
VDDA = VDDB = 3.3 V,
Loaded outputs at166 MHz,
CL = 15 pF
–
100
120
Thermal Resistance
Parameter [5]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
28-pin SSOP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
65
°C/W
30
°C/W
Notes
3. Applies to both REF Clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5. These parameters are guaranteed by design and are not tested.
Document Number: 38-07246 Rev. *K
Page 10 of 19
CY23FP12
Switching Characteristics
Parameter [6]
fREF
Description
Reference frequency[7]
ERREF
Reference edge rate
DCREF
Reference duty cycle
fOUT
Output frequency[8]
DCOUT
t3
t4
Output duty cycle[6]
Rise
time[6]
Fall time[6]
Min
Typ
Max
Unit
Commercial temperature
Test Conditions
10
–
200
MHz
Industrial temperature
10
–
166.7
1
–
–
V/ns
25
–
75
%
CL = 15 pF,
Commercial temperature
10
–
200
MHz
CL = 15 pF, Industrial temperature
10
–
166.7
CL = 30 pF,
Commercial temperature
10
–
100
CL = 30 pF, Industrial temperature
10
–
83.3
VDDA/B = 3.3 V, measured at VDD/2
45
50
55
VDDA/B = 2.5 V, measured at VDD/2
40
50
60
VDDA/B = 3.3 V, 0.8 V to 2.0 V,
CL = 30 pF (standard drive and high
drive)
–
–
1.6
VDDA/B = 3.3 V, 0.8 V,10 V to 2.0 V,
CL = 15 pF (standard drive and high
drive)
–
–
0.8
VDDA/B = 2.5 V, 0.6 V to 1.8 V,
CL = 30 pF (high drive only)
–
–
2.0
VDDA/B = 2.5 V, 0.6 V to 1.8 V,
CL = 15 pF (high drive only)
–
–
1.0
VDDA/B = 3.3 V, 0.8 V to 2.0 V,
CL = 30 pF (standard drive and high
drive)
–
–
1.6
VDDA/B = 3.3 V, 0.8 V to 2.0 V,
CL = 15 pF (standard drive and high
drive)
–
–
0.8
VDDA/B = 2.5 V, 0.6 V to 1.8 V,
CL = 30 pF (high drive only)
–
–
1.6
VDDA/B = 2.5 V, 0.6 V to 1.8 V,
CL = 15 pF (high drive only)
–
–
0.8
%
ns
ns
Notes
6. All parameters are specified with loaded outputs.
7. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the reference frequency can be lower than 10 MHz. With auto power-down
disabled and PLL power-down enabled, the reference frequency can be as low as DC level.
8. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the output frequency can be lower than 10 MHz. With auto power-down disabled
and PLL power-down enabled, the output frequency can be as low as DC level.
Document Number: 38-07246 Rev. *K
Page 11 of 19
CY23FP12
Switching Characteristics (continued)
Parameter [6]
TTB
Description
[9, 10],
Total timing budget
Bank A and B same frequency
Test Conditions
Min
Typ
Max
Unit
Outputs at 200 MHz, tracking skew
not included
–
–
650
ps
–
–
850
Total timing budget,
Bank A and B different frequency
Output to output skew[11]
All outputs equally loaded
–
35[12]
200
Bank to bank skew
Same frequency
–
–
200
Bank to bank skew
Different frequency
–
–
400
Bank to bank skew
Different voltage, same frequency
–
–
400
t6
Input to output skew
(static phase offset)[11]
Measured at VDD/2, REF to FBK
–
0
250
ps
t7
Device-to-device skew[11]
Measured at VDD/2
–
0
500
ps
200
ps
t5
Banks A and B at same frequency
–
110[13]
Cycle-to-cycle jitter[11] (Peak)
Banks A and B at different
frequencies
–
–
400
tTSK
Tracking skew
Input reference clock at < 50 KHz
modulation with ±3.75% spread
–
–
200
ps
tLOCK
PLL lock time[11]
Stable power supply, valid clock at
REF
–
–
1.0
ms
tLD
Inserted loop delay
Max loop delay for PLL Lock (stable
frequency)
–
–
7
ns
Max loop delay to meet Tracking
Skew Spec
–
–
4
ns
tJ
Cycle-to-cycle
jitter[11] (Peak)
ps
Notes
9. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
10. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle
jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency.
11. All parameters are specified with loaded outputs.
12. Same frequency, 15 pF load, high drive.
13. Same frequency, 15 pF load, low drive.
Document Number: 38-07246 Rev. *K
Page 12 of 19
CY23FP12
Switching Waveforms
Figure 2. Duty Cycle Timing
Figure 3. All Outputs Rise/Fall Time
Figure 4. Output-Output Skew
Figure 5. Input-Output Propagation Delay
Figure 6. Device-Device Skew
Document Number: 38-07246 Rev. *K
Page 13 of 19
CY23FP12
Test Circuits
Figure 7. Test Circuits
Document Number: 38-07246 Rev. *K
Page 14 of 19
CY23FP12
Ordering Information
Ordering Code
Package Type
Operating Range
Pb-free
CY23FP12OXC
28-pin SSOP
Commercial, 0 °C to 70 °C
CY23FP12OXCT
28-pin SSOP – Tape and Reel
Commercial, 0 °C to 70 °C
CY23FP12OXI
28-pin SSOP
Industrial, –40 °C to 85 °C
CY23FP12OXIT
28-pin SSOP – Tape and Reel
Industrial, –40 °C to 85 °C
Programmer
CY3672-USB
Programmer with USB Interface
CY3692
CY23FP12 Socket Adapter for CY3672-USB Programmer (Labeled CY3672 ADP006)
Ordering Code Definitions
CY
23FP12
O
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
O = 28-pin SSOP
Device Number
Company ID: CY = Cypress
Document Number: 38-07246 Rev. *K
Page 15 of 19
CY23FP12
Package Drawing and Dimensions
Figure 8. 28-pin SSOP (210 Mils) Package Outline, 51-85079
51-85079 *F
Document Number: 38-07246 Rev. *K
Page 16 of 19
CY23FP12
Acronyms
Acronym
Document Conventions
Description
Units of Measure
DCXO
Digitally Controlled Crystal Oscillator
ESD
Electrostatic Discharge
°C
degree Celsius
PLL
Phase Locked Loop
MHz
megahertz
RMS
Root Mean Square
µA
microampere
SSOP
Shrunk Small Outline Package
mA
milliampere
XTAL
Crystal
ms
millisecond
ns
nanosecond
Document Number: 38-07246 Rev. *K
Symbol
Unit of Measure
pF
picofarad
ps
picosecond
V
volt
Page 17 of 19
CY23FP12
Document History Page
Document Title: CY23FP12, 200 MHz Field Programmable Zero Delay Buffer
Document Number: 38-07246
Revision
ECN
Submission
Date
Orig. of
Change
**
115158
07/03/02
HWT
Description of Change
New data sheet.
*A
121880
12/14/02
RBI
Power-up requirements added to Absolute Maximum Ratings information
*B
124523
03/19/03
RGL
Final data sheet
Changed title to “200 MHz Field Programmable Zero Delay Buffer”
*C
126938
06/16/03
RGL
Interchanged REF2 in the Pin Configuration diagram
Replaced all divide by 2 default value to divide by 2 in Table 2
Fixed the formula in the Frequency Calculation section
*D
129364
09/10/03
RGL
Changed the CyClocksRT trademark to CyberClocks
Added Note 2 in the TEST mode in Table 3
Added TLD specifications in the Switching Characteristics table
*E
299718
See ECN
RGL
Added lead-free devices
Added typical values
*F
2865396
01/25/2010
KVM
Added captions to tables 1-4.
Added Operating Conditions table.
Various edits to text.
Removed “FTG” from text about the CY3672 programmer.
Specified separate commercial and industrial max values for fREF
Removed part numbers CY23FP12OC, CY23FP12OCT, CY23FP12OI and
CY23FP12OIT.
Changed part number CY3672 to CY3672-USB.
Updated package drawing.
Updated to new template.
*G
3146083
01/18/11
BASH
Modified VIN max value from 7 to VDD + 0.5 in “Absolute Maximum Conditions”
on page 8.
Added Ordering Code Definitions under Ordering Information.
Added Acronyms and Units of Measure.
*H
4291450
02/25/2014
CINM
Updated Package Drawing and Dimensions:
spec 51-85079 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*I
4580603
11/26/2014
AJU
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
5276049
05/27/2016
PSR
Updated Absolute Maximum Conditions:
Removed ØJc, ØJa parameters and their details.
Changed value of MSL parameter from “MSL – 1” to “MSL – 3”.
Added Thermal Resistance.
Updated Package Drawing and Dimensions:
spec 51-85079 – Changed revision from *E to *F.
Updated to new template.
*K
5663650
03/17/2017
PAWK
Document Number: 38-07246 Rev. *K
Updated to new template.
Completing Sunset Review.
Page 18 of 19
CY23FP12
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2002-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-07246 Rev. *K
Revised March 17, 2017
Page 19 of 19
CyberClocks™ is a trademark and CyClocks is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
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