CY23FS04ZXC-2

CY23FS04-2 Failsafe™ 2.5V/3.3V Zero Delay Buffer Features Functional Description ■ Internal DCXO for Continuous Glitch-free Operation ■ Zero Input-Output Propagation Delay ■ Low-Jitter (35 ps max RMS) Outputs ■ Low Output-to-Output Skew (200 ps max) The CY23FS04-2 is a FailSafe™ zero delay buffer with two reference clock inputs and four phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. ■ 4.17 MHz to 50 MHz Reference Input ■ Supports Industry Standard Input Crystals ■ 4.17 MHz to 50 MHz Outputs ■ 5V-Tolerant Inputs ■ Phase-Locked Loop (PLL) Bypass Mode ■ Dual Reference Inputs ■ 16-Pin TSSOP ■ 2.5V or 3.3V Output Power Supplies ■ 3.3V Core Power Supply The continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS04-2 is that the DCXO is in fact the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal that is connected to the DCXO must be an integer factor of the frequency of the reference clock. This factor is set by two select lines: S[2:1], see Table 2. The output power supply VDD can be connected to either 2.5V or 3.3V. VDDC is the power supply pin for internal circuits and must be connected to 3.3V. Logic Block Diagram XIN XOUT REFSEL DCXO REF1 2 FailsafeTM REF2 Block PLL 2 CLKA[1:2] CLKB[1:2] FBK Decoder FAIL# /SAFE 2 S[2:1] Cypress Semiconductor Corporation Document Number: 38-07671 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 29, 2010 [+] Feedback CY23FS04-2 Contents Features ............................................................................. 1 Functional Description ..................................................... 1 Logic Block Diagram ........................................................ 1 Contents ............................................................................ 2 Pin Configuration ............................................................. 3 FailSafe Function .............................................................. 4 XTAL Selection Criteria and Application Example ...... 7 Absolute Maximum Conditions ....................................... 9 Recommended Pullable Crystal Specifications ............ 9 Operating Conditions for FailSafe Devices .................... 9 Document Number: 38-07671 Rev. *B Electrical Characteristics for FailSafe Devices ........... 10 Switching Characteristics for FailSafe Devices .......... 10 Ordering Information ...................................................... 10 Package Diagram ............................................................ 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 12 Worldwide Sales and Design Support ....................... 12 Products .................................................................... 12 PSoC Solutions ......................................................... 12 Page 2 of 12 [+] Feedback CY23FS04-2 Pin Configuration Figure 1. 16-Pin TSSOP Table 1. Pin Definition Pin No. Pin Name Description 5V-tolerant.[4] 1,2 REF[1:2] Reference clock inputs. 3,4 CLKB[1:2] Bank B clock outputs.[1,2] 14,13 CLKA[1:2] Bank A clock outputs.[1,2] 15 FBK Feedback input to the PLL.[1,4] 12,5 S[1:2] Frequency select pins and PLL and DCXO bypass mode.[3] 8 XIN Reference crystal input. 9 XOUT Reference crystal output. 10 FAIL#/SAFE Valid reference indicator. A high level indicates a valid reference input. 11 VDD 2.5V or 3.3V power supply. 7 VDDC 3.3V power supply. 6 VSS Ground. 16 REFSEL Reference select. Selects the active reference clock from either REF1 or REF2. REFSEL = 1, REF1 is selected; REFSEL = 0, REF2 is selected. Table 2. Configuration Table S[2:1] XTAL (MHz) REF (MHz) OUT (MHz) REF:XTAL Ratio Out:XTAL Ratio x1 1/2 1/2 x1 2 2 1 1 Max Min Max Min 01 8.33 30.00 4.17 15.00 4.17 15.00 10 8.00 25.00 16.00 50.00 16.00 50.00 11 8.33 30.00 8.33 30.00 8.33 30.00 x1 00 Max REF:OUT Ratio Min PLL and DCXO Bypass Mode Notes 1. For normal operation, connect either one of the four clock outputs to the FBK input. 2. Weak pull downs on all outputs. 3. Weak pull ups on these inputs. 4. Weak pull down on these inputs Document Number: 38-07671 Rev. *B Page 3 of 12 [+] Feedback CY23FS04-2 FailSafe Function The CY23FS04-2 is targeted at clock distribution applications that require continued operation should the main reference clock fail. Existing approaches to this requirement have used multiple reference clocks with either internal or external methods to switch between references. The problem with this technique is that it leads to interruptions (or glitches) when transitioning from one reference to another, often requiring complex external circuitry or software to maintain system stability. The technique implemented in this design completely eliminates any switching of references to the PLL, greatly simplifying system design. The CY23FS04-2 PLL is driven by the crystal oscillator, which is phase-aligned to an external reference clock so that the output of the device is effectively phase-aligned to the reference via the external feedback loop. This is accomplished by using a digitally controlled capacitor array to pull the crystal frequency over an approximate range of +300 ppm from its nominal frequency. In this mode, if the reference frequency fails (stop or disappear), the DCXO maintains its last setting and a flag signal (FAIL#/SAFE) is set to indicate failure of the reference clock. The CY23FS04-2 provides two select bits, S1 and S2, to control the reference-to-crystal frequency ratio. The DCXO is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this ratio is within the DCXO capture range. If the frequency is out of range, a flag is set on the FAIL#/SAFE pin notifying the system that the selected reference is not valid. If the reference moves in range, then the flag is cleared, indicating to the system that the selected reference is valid. Figure 2. Fail#/Safe Timing for Input Reference Failing Catastrophically REF OUT Fail#/S afe t FSH t FSL Figure 3. Fail#/Safe Timing Formula t F S L (m a x ) = 2 ( tR E F x n ) + 25ns n = F R E F = 4 ( in a b o v e e x a m p le ) F XTAL t F S H ( m in ) = 12( tR E F x n ) + 25ns Table 3. FailSafe Timing Table Parameter Description Conditions tFSL Fail#/Safe Assert Delay Measured at 80% to 20%, Load = 15 pF tFSH Fail#/Safe Deassert Delay Measured at 80% to 20%, Load = 15 pF Document Number: 38-07671 Rev. *B Min See Figure 3 Max Unit See Figure 3 ns ns Page 4 of 12 [+] Feedback CY23FS04-2 Figure 4. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range Reference + 300 ppm Reference Reference - 300 ppm Frequency Reference Off Output + 300 ppm Output Output - 300 ppm Volt Fail#/Safe tFSH tFSL Time Figure 5. FailSafe Reference Switching Behavior Document Number: 38-07671 Rev. *B Page 5 of 12 [+] Feedback CY23FS04-2 Because of the DCXO architecture, the CY23FS04-2 has a much lower bandwidth than a typical PLL-based clock generator. This is shown in Figure 6. This low bandwidth makes the CY23FS04-2 also useful as a jitter attenuator. The loop bandwidth curve is also known as the jitter transfer curve. Figure 6. FailSafe Effective Loop Bandwidth (min) Figure 7. Duty Cycle = t1 / t2 Duty Cycle - t DC VDD/2 VDD/2 VDD/2 VDD 0V t1 t2 Figure 8. Input Slew Rate 70% VDD 70% 30% 30% 0V t SR(I) t SR(I) Figure 9. Output Slew Rate 80% VDD 80% 20% 20% 0V tSR(O) Document Number: 38-07671 Rev. *B tSR(O) Page 6 of 12 [+] Feedback CY23FS04-2 Figure 10. Output to Output Skew and Intrabank Skew VDD/2 VDD/2 t SK Figure 11. Part to Part Skew FBK, Part 1 VDD/2 FBK, Part 2 VDD/2 tSK(PP) Figure 12. Phase Offset REF VDD/2 FBK VDD/2 t(φ) XTAL Selection Criteria and Application Example C0 is the XTAL shunt capacitance (3 pF to 7 pF typ). Choosing the appropriate XTAL ensures the FailSafe device is able to span an appropriate frequency of operation. Also, the XTAL parameters determine the holdover frequency stability. Critical parameters are given here. Cypress recommends that you choose: C1 is the XTAL motional capacitance (10 fF to 30 fF typ). ■ Low C0/C1 ratio (240 or less) so that the XTAL has enough range of pullability ■ Low temperature frequency variation ■ Low manufacturing frequency tolerance ■ Low aging The capacitive load as “seen” by the XTAL is across its terminals. It is named CLOADMIN (for minimum value), and CLOADMAX (for maximum value).These are used to calculate the pull range. Note that the CLOAD range “center” is approximately 20 pF, but you may not want a XTAL calibrated to that load. This is because the pullability is not linear, as represented in the equation above. Plotting the pullability of the XTAL shows this expected behavior as shown in Figure 13. In this example, specifying a XTAL calibrated to 14 pF load provides a balanced ppm pullability range around the nominal frequency. Example: CLOADMIN = (12 pF IC input cap + 0 pF pulling cap + 6 pF trace cap on board) / 2 = 9 pF CLOADMAX = (12 pF IC input cap + 48 pF pulling cap + 6 pF trace cap on board) / 2 = 33 pF Pull Range = (fCLOADMIN – fCLOADMAX) / fCLOADMIN = (C1 / 2) * [(1 / (C0 + CLOADMIN)) – (1 / (C0 + CLOADMAX))] Pull Range in ppm = (C1 / 2) * [(1 / (C0 + CLOADMIN)) – (1 / (C0 + CLOADMAX))] * 106 Document Number: 38-07671 Rev. *B Page 7 of 12 [+] Feedback CY23FS04-2 Figure 13. Frequency vs. CLOAD Behavior for Example XTAL Pullability Range vs CLOAD (Normalized to 14pF CLOAD ) Delta Freq. from nominal (PPM) 400 300 200 100 C0/C1 = 200 0 C0/C1 = 300 -100 C0/C1 = 400 -200 -300 -400 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 CLOAD (pF) Table 4. Pullability Range of XTAL with Different C0/C1 Ratio Pullability Range C0/C1 Ratio CLOAD(min) CLOAD(max) 200 8.0 32.0 –385 333 300 8.0 32.0 –256 222 400 8.0 32.0 –192 166 Calculating the capture range involves subtracting error tolerances as follows: Parameter...........................................................f error (ppm) Manufacturing frequency tolerance ...................................15 Temperature stability ..........................................................30 Aging ................................................................................... 3 Board/trace variation ........................................................... 5 Calculated value of the pullability range for the XTAL with C0/C1 ratio of 200, 300, and 400 are shown in Table 4. For this calculation CLOAD(min) = 8 pF and CLOAD(max)= 32 pF is used. Using a XTAL that has a nominal frequency specified at load capacitance of 14 pF, almost symmetrical pullability range is obtained. Total ....................................................................................53 Next, it is important to calculate the pullability range including error tolerances. This is the capture range of the input reference frequency that the FailSafe device and XTAL combination can reliably span. It is important to note that the XTAL with lower C0/C1 ratio has wider pullability/capture range as compared to the higher C0/C1 ratio. This helps to select the appropriate XTAL for use in the FailSafe application. Document Number: 38-07671 Rev. *B Example: Capture Range for XTAL with C0/C1 Ratio of 200 Negative Capture Range= –385 ppm + 53 ppm = –332 ppm Positive Capture Range = 333 ppm – 53 ppm = +280 ppm Page 8 of 12 [+] Feedback CY23FS04-2 Absolute Maximum Conditions Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Parameter Description Condition Min Max Unit VDD Supply Voltage VIN Input Voltage TS TJ ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 29.87 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) 120.11 °C/W UL–94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level –0.5 4.6 V Relative to VSS –0.5 VDD+0.5 VDC Temperature, Storage Non Functional –65 150 °C Temperature, Junction Functional – 125 °C 2000 – V V–0 1 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. Recommended Pullable Crystal Specifications[5] Parameter Name Comments Min Typ Max Unit 8.00 – 30.00 MHz FNOM Nominal crystal frequency CLOADNOM Nominal load capacitance – 14 – pF R1 Equivalent series resistance (ESR) Fundamental mode – – 25 Ω R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec 3 – – DL Crystal drive level No external series resistor assumed – 0.5 2 mW F3SEPLI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF Parallel resonance, fundamental mode, AT cut C0 / C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 fF Operating Conditions for FailSafe Devices Parameter Description Min Max Unit VDDC 3.3V Supply Voltage 3.135 3.465 V VDD 2.5V Supply Voltage Range 2.375 2.625 V 3.3V Supply Voltage Range 3.135 3.465 V TA Ambient Operating Temperature, Commercial 0 70 °C CL Output Load Capacitance – 30 pF CIN Input Capacitance (except XIN) – 7 pF CXIN Crystal Input Capacitance (all internal caps off) TPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 10 13 pF 0.05 500 ms Note 5. Ecliptek ECX-5788-13.500M, ECX-5807-19.440M, ECX-5872-19.53125M, ECX-6362-18.432M, ECX-5808-27.000M, ECX-5884-17.664M, ECX-5883-16.384M, ECX-5882-19.200M, ECX-5880-24.576M meet these specifications. Document Number: 38-07671 Rev. *B Page 9 of 12 [+] Feedback CY23FS04-2 Electrical Characteristics for FailSafe Devices Parameter Description VIL Input Low Voltage Min Typ Max Unit CMOS Levels, 30% of VDD Test Conditions – – 0.3 × VDD V µA VIH Input High Voltage CMOS Levels, 70% of VDD 0.7 × VDD – IIL Input Low Current VIN = VSS (100k pull up only) – – 50 IIH Input High Current VIN = VDD (100k pull down only) – – 50 µA IOL Output Low Current VOL = 0.5V, VDD = 2.5V – 18 – mA VOL = 0.5V, VDD = 3.3V – 20 – mA IOH Output High Current VOH = VDD – 0.5V, VDD = 2.5V – 18 – mA VOH = VDD – 0.5V, VDD = 3.3V – 20 – mA IDDQ Quiescent Current All inputs grounded, PLL and DCXO in bypass mode, Reference Input = 0 – – 250 µA V Switching Characteristics for FailSafe Devices Parameter[7] Description Test Conditions Min Max Unit fREF Reference Frequency Commercial/Industrial Grades 4.17 50 MHz fOUT Output Frequency 30 pF Load, Commercial Grade 4.17 50 MHz fXIN DCXO Frequency 8.0 30 MHz tDC Duty Cycle Measured at VDD/2 47 53 % tSR(I) Input Slew Rate Measured on REF1 Input, 30% to 70% of VDD 0.5 4.0 V/ns tSR(O) Output Slew Rate Measured from 20% to 80% of VDD = 3.3V, 15 pF Load 0.8 4.0 V/ns Measured from 20% to 80% of VDD = 2.5V, 15 pF Load 0.4 3.0 V/ns All outputs equally loaded, measured at VDD/2 – 200 ps tSK(O) Output to Output Skew tSK(PP) Part to Part Skew Measured at VDD/2 – 500 ps t(φ)[6] Static Phase Offset Measured at VDD/2 – 250 ps tD(φ) [6] tJ(CC) Dynamic Phase Offset Measured at VDD/2 – 200 ps Cycle-to-Cycle Jitter Load = 15 pF, fOUT ≥ 6.25 MHz – 200 ps – 35 psRMS Ordering Information Part Number Package Type Product Flow Pb-free CY23FS04ZXC-2 16-Pin TSSOP Commercial, 0°C to 70°C CY23FS04ZXC-2T 16-Pin TSSOP – Tape and Reel Commercial, 0°C to 70°C Notes 6. The t(φ) reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as tSR(I) is maintained. 7. Parameters guaranteed by design and characterization, not 100% tested in production. Document Number: 38-07671 Rev. *B Page 10 of 12 [+] Feedback CY23FS04-2 Package Diagram Figure 14. 16-Pin TSSOP 4.40 mm Body PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.05gms 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091 *B Document Number: 38-07671 Rev. *B Page 11 of 12 [+] Feedback CY23FS04-2 Document History Page Document Title: CY23FS04-2 Failsafe™ 2.5V/3.3V Zero Delay Buffer Document Number: 38-07671 Rev. ECN No. Submission Date Orig. of Change ** 224423 See ECN RGL *A 276753 See ECN *B 2865337 01/25/2010 Description of Change New data sheet RGL/ZJX Removed (TLOCK) Lock Time Specification CXQ Updated format. Added “Contents” section on page 2. Removed previous Figures 5 and 6. Added / separated Figures 7 through 12. Changed references of “Cl” to “CLOAD”. Removed extra TA reference in Absolute Maximum Conditions. Removed industrial temperature range from TA. Removed CL spec for fOUT > 100 MHz (fOUT max is 50 MHz for -2 devices). Changed table captions for Tables 4, 5, and 6 to section headings. Removed note 5 regarding programming cap array. Replaced crystal ECX–5806–18.432M with ECX–6362–18.432M in Note 6. Changed test condition from 15 pF to 30 pF for fOUT spec. Removed industrial temp range devices from Ordering Information. Removed unreferenced Note 9. Updated package drawing specification to rev *B. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2003-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07671 Rev. *B Revised January 29, 2010 Page 12 of 12 2 FailSafe™ is a trademark of Cypress Semiconductor Corporation. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback