CY23FS08OXI-04T

CY23FS08-04 FailSafe™ 1.8V Zero Delay Buffer Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The CY23FS08-04 is a FailSafe Zero Delay Buffer with two reference clock inputs and eight phase aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. Continuous, glitch free operation is achieved by using a DCXO that serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS08-04 is that the DCXO is in fact, the primary clocking source, that is synchronized (phase aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal that is connected to the DCXO is chosen as an integer factor of the frequency of the reference clock. This factor is set by four select lines: S[4:1]. For more information, see Table 2 on page 3. The CY23FS08-04 has three split power supplies; one for core, another for Bank A outputs, and the third for Bank B outputs. Each output power supply, except VDDC is connected to 1.8V. VDDC is the power supply pin for internal circuits and is connected to 3.3V. Internal DCXO for continuous glitch free operation Zero input-output propagation delay Low output cycle-to-cycle jitter (