CY23FS08_11

CY23FS08 Failsafe™ 2.5 V/3.3 V Zero Delay Buffer Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The CY23FS08 is a FailSafe™ Zero Delay Buffer with two reference clock inputs and eight phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. Continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS08 is that the DCXO is in fact the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal connected to the DCXO, must be chosen to be an integer factor of the frequency of the reference clock. This factor is set by four select lines: S[4:1]. see Table 2. The CY23FS08 has three split power supplies; one for core, another for Bank A outputs, and the third for Bank B outputs. Each output power supply, except VDDC can be connected to either 2.5 V or 3.3 V. VDDC is the power supply pin for internal circuits and must be connected to 3.3 V. Internal DCXO for continuous glitch-free operation Zero input-output propagation delay 100 ps typical output cycle-to-cycle jitter 110 ps typical output-output skew 1 MHz to 200 MHz reference input Supports industry standard input crystals 200 MHz (commercial), 166 MHz (industrial) outputs 5 V-tolerant inputs Phase-locked loop (PLL) bypass mode Dual reference inputs 28-pin SSOP Split 2.5 V or 3.3 V output power supplies 3.3 V core power supply Industrial temperature available Logic Block Diagram XIN XOUT REFSEL DCXO REF1 REF2 FBK FailsafeTM Block PLL 4 4 CLKA[1:4] CLKB[1:4] Decoder FAIL# /SAFE S[4:1] 4 Cypress Semiconductor Corporation Document Number: 38-07518 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 7, 2011 [+] Feedback CY23FS08 Contents Features............................................................................. 1 Functional Description..................................................... 1 Logic Block Diagram........................................................ 1 Contents ............................................................................ 2 Pinouts .............................................................................. 3 FailSafe Function.............................................................. 4 XTAL Selection Criteria and Application Example ...... 8 Absolute Maximum Conditions..................................... 10 Recommended Pullable Crystal Specifications ........... 10 Operating Conditions..................................................... 10 DC Electrical Characteristics ........................................ 11 Switching Characteristics.............................................. 11 Ordering Information....................................................... 11 Package Diagram............................................................ 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Document Number: 38-07518 Rev. *F Page 2 of 15 [+] Feedback CY23FS08 Pinouts Figure 1. Pin Configuration REF1 REF2 VSSB CLKB1 CLKB2 S2 S3 VDDB VSSB CLKB3 CLKB4 VDDB VDDC XIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CY23FS08 28 27 26 25 24 23 22 21 20 19 18 17 16 15 REFSEL FBK VSSA CLKA1 CLKA2 S1 S4 VDDA VSSA CLKA3 CLKA4 VDDA FAIL#/SAFE XOUT 28-pin SSOP Table 1. Pin Definitions Pin Number 1,2 4,5,10,11 25,24,19,18 27 23,6,7,22 14 15 16 13 8,12 3,9 17,21 20,26 28 Pin Name REF1,REF2 CLKB[1:4] CLKA[1:4] FBK S[1:4] XIN XOUT FAIL#/SAFE VDDC VDDB VSSB VDDA VSSA REFSEL Reference clock inputs.[4] 5 V tolerant. Bank B clock outputs.[1, 2] Bank A clock outputs.[1, 2] Feedback input to the PLL.[1] Frequency select pins/PLL and DCXO bypass.[3] Reference crystal input. Reference crystal output. Valid reference indicator. A high level indicates a valid reference input. 3.3 V power supply for the internal circuitry. 2.5 V or 3.3 V power supply for Bank B outputs. Ground. 2.5 V or 3.3 V power supply for Bank A outputs. Ground. Reference select. Selects the active reference clock from either REF1 or REF2. When REFSEL = 1, REF1 is selected. When REFSEL = 0, REF2 is selected. Description Table 2. Configuration Table S[4:1] 0000 1000 1110 8.33 9.50 30 30 16.67 57.00 60.00 180.00 XTAL (MHz) Min Max REF(MHz) Min Max OUT(MHz) Min 8.33 28.50 Max 30.00 90.00 REF:OUT Ratio 2 2 REF:XTAL Out:XTAL Ratio Ratio 2 6 1 3 PLL and DCXO Bypass mode Notes 1. For normal operation, connect either one of the eight clock outputs to the FBK input. 2. Weak pull downs on all CLK outputs. 3. Weak pull ups on these inputs. 4. Weak pull downs on these inputs. Document Number: 38-07518 Rev. *F Page 3 of 15 [+] Feedback CY23FS08 Table 2. Configuration Table (continued) S[4:1] 0101 1011 0011 1001 1111 1100 0001 0110 1101 0100 1010 0010 0111 XTAL (MHz) Min 8.50 8.33 8.33 8.33 8.00 8.00 8.33 8.33 8.33 8.33 8.33 8.33 8.33 Max 30 30 30 30 25 25 30 30 30 30 30 30 30 REF(MHz) Min 6.80 25.00 2.78 8.33 32.00 64.00 1.04 4.17 16.67 4.17 12.50 1.39 6.25 Max 24.00 90.00 10.00 30.00 100.00 200.00 3.75 15.00 60.00 15.00 45.00 5.00 22.50 OUT(MHz) Min 1.70 6.25 2.78 8.33 32.00 64.00 2.08 8.33 33.33 16.67 50.00 11.11 50.00 Max 6.00 22.50 10.00 30.00 100.00 200.00 7.50 30.00 120.00 60.00 180.00 40.00 180.00 REF:OUT Ratio 4 4 ×1 ×1 ×1 ×1 ×2 ×2 ×2 ×4 ×4 ×8 ×8 REF:XTAL Out:XTAL Ratio Ratio 4/5 3 1/3 1 4 8 1/8 1/2 2 1/2 3/2 1/6 3/4 1/5 3/4 1/3 1 4 8 1/4 1 4 2 6 4/3 6 FailSafe Function The CY23FS08 is targeted at clock distribution applications that requires or may require continued operation if the main reference clock fails. Existing approaches to this requirement have used multiple reference clocks with either internal or external methods to switch between references. The problem with this technique is that it leads to interruptions (or glitches) when transitioning from one reference to another, often requiring complex external circuitry or software to maintain system stability. The technique implemented in this design completely eliminates any switching of references to the PLL, greatly simplifying system design. The CY23FS08 PLL is driven by the crystal oscillator, which is phase-aligned to an external reference clock so that the output of the device is effectively phase-aligned to reference via the external feedback loop. This is accomplished by using a digitally controlled capacitor array to pull the crystal frequency over an approximate range of ±300 ppm from its nominal frequency. In this mode, if the reference frequency fails (that is, stops or disappears), the DCXO maintains its last setting and a flag signal (FAIL#/SAFE) is set to indicate failure of the reference clock. The CY23FS08 provides four select bits, S1 through S4 to control the reference to crystal frequency ratio. The DCXO is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this ratio is within the DCXO capture range. If the frequency is out of range, a flag is set on the FAIL#/SAFE pin notifying the system that the selected reference is not valid. If the reference moves in range, then the flag is cleared, indicating to the system that the selected reference is valid. Figure 2. Fail#/Safe Timing for Input Reference Failing Catastrophically REF OUT F A IL # /S A F E tF S L tF S H Document Number: 38-07518 Rev. *F Page 4 of 15 [+] Feedback CY23FS08 Figure 3. Fail#/Safe Timing Formula Table 3. Failsafe Timing Table Parameter tFSL tFSH Description Fail#/Safe Assert Delay Fail#/Safe Deassert Delay Conditions Measured at 80% to 20%, Load = 15 pF Measured at 80% to 20%, Load = 15 pF See Figure 3 Min Max See Figure 3 Unit ns ns Figure 4. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range Reference + 300 ppm Reference Reference - 300 ppm Reference Off Frequency Output + 300 ppm Output Output - 300 ppm Fail#/Safe Volt tFSH tFSL Time Document Number: 38-07518 Rev. *F Page 5 of 15 [+] Feedback CY23FS08 Figure 5. FailSafe Reference Switching Behavior Because of the DCXO architecture, the CY23FS08 has a much lower bandwidth than a typical PLL-based clock generator. This is shown in Figure 6. This low bandwidth makes the CY23FS08 also useful as a jitter attenuator. The loop bandwidth curve is also known as the jitter transfer curve. Figure 6. FailSafe Effective Loop Bandwidth (min) Document Number: 38-07518 Rev. *F Page 6 of 15 [+] Feedback CY23FS08 Figure 7. Duty Cycle Duty Cycle - t DC VDD/2 = t1 / t2 VDD/2 t1 t2 VDD/2 VDD 0V Figure 8. Input Slew Rate 70% 30% t SR(I) t SR(I) 70% 30% 0V VDD Figure 9. Output Slew Rate 80% 20% tSR(O) tSR(O) 80% 20% 0V VDD Figure 10. Output to Output Skew and Intrabank Skew VDD/2 VDD/2 t SK Figure 11. Part to Part Skew FBK, Part 1 FBK, Part 2 VDD/2 VDD/2 tSK(PP) Document Number: 38-07518 Rev. *F Page 7 of 15 [+] Feedback CY23FS08 Figure 12. Phase Offset REF VDD/2 FBK VDD/2 t() XTAL Selection Criteria and Application Example Selecting the appropriate XTAL ensures the FailSafe device is able to span an appropriate frequency of operation. Also, the XTAL parameters determine the holdover frequency stability. Critical parameters are given here. Cypress recommends that you choose: ■ ■ ■ ■ C0 is the XTAL shunt capacitance (3 pF to 7 pF typ). C1 is the XTAL motional capacitance (10 fF to 30 fF typ). The capacitive load as “seen” by the XTAL is across its terminals. It is named CLOADMIN (for minimum value), and CLOADMAX (for maximum value).These are used for calculating the pull range. Note that the CLOAD range “center” is approximately 20 pF, but we may not want a XTAL calibrated to that load. This is because the pullability is not linear, as represented in the equation below. Plotting the pullability of the XTAL shows this expected behavior as shown in Figure 13. In this example, specifying a XTAL calibrated to 14 pF load provides a balanced ppm pullability range around the nominal frequency. Low C0/C1 ratio (240 or less) so that the XTAL has enough range of pullability. Low temperature frequency variation Low manufacturing frequency tolerance Low aging Example: CLOADMIN = (12 pF IC input cap + 0 pF pulling cap + 6 pF trace cap on board) / 2 = 9 pF CLOADMAX = (12 pF IC input cap + 48 pF pulling cap + 6 pF trace cap on board) / 2 = 33 pF Pull Range = (fCLOADMIN – fCLOADMAX) / fCLOADMIN = (C1 / 2) * [(1 / (C0 + CLOADMIN)) – (1 / (C0 + CLOADMAX))] Pull Range in ppm = (C1 / 2) * [(1 / (C0 + CLOADMIN)) – (1 / (C0 + CLOADMAX))] * 106 Document Number: 38-07518 Rev. *F Page 8 of 15 [+] Feedback CY23FS08 Figure 13. Frequency vs. CLOAD Behavior for Example XTAL Pullability Range vs. CLOAD (Normalized to 14pF CLOAD ) 400 Delta Freq. from nominal (PPM) 300 200 100 0 -100 -200 -300 -400 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 CLOAD (pF) C0/C1 = 200 C0/C1 = 300 C0/C1 = 400 Table 4. Pullability Range from XTAL with Different C0/C1 Ratio C0/C1 Ratio 200 300 400 CLOADMIN 8 8 8 CLOADMAX 32 32 32 Pullability Range –385 –256 –192 333 222 166 Calculating the capture range involves subtracting error tolerances as follows: Parameter ........................................................ f error (ppm) Manufacturing frequency tolerance ...................................15 Temperature stability ..........................................................30 Aging ................................................................................... 3 Board/trace variation ........................................................... 5 Total ...................................................................................53 Example: Capture Range for XTAL with C0/C1 Ratio of 200 Negative Capture Range= –385 ppm + 53 ppm = –332 ppm Positive Capture Range = 333 ppm – 53 ppm = +280 ppm It is important to note that the XTAL with lower C0/C1 ratio has wider pullability/capture range as compared to the higher C0/C1 ratio. This helps to select the appropriate XTAL for use in the FailSafe application. Calculated value of the pullability range for the XTAL with C0/C1 ratio of 200, 300, and 400 are shown in Table 4. For this calculation CLOADMIN = 8 pF and CLOADMAX = 32 pF is used. Using a XTAL that has a nominal frequency specified at load capacitance of 14 pF, almost symmetrical pullability range is obtained. Next, it is important to calculate the pullability range including error tolerances. This is the capture range of the input reference frequency that the FailSafe device and XTAL combination can reliably span. Document Number: 38-07518 Rev. *F Page 9 of 15 [+] Feedback CY23FS08 Absolute Maximum Conditions Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Parameter VDD VIN TS TJ ESDHBM ØJC ØJA UL–94 MSL Input Voltage Temperature, Storage Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Description Supply Voltage Relative to VSS Non Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition Min –0.5 –0.5 –65 – 2000 36.17 100.6 V–0 1 Max 4.6 VDD + 0.5 150 125 – Unit V VDC °C °C V °C/W °C/W Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Recommended Pullable Crystal Specifications[5] Parameter FNOM CLNOM R1 R3/R1 DL F3SEPLI F3SEPLO C0 C0/C1 C1 Name Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal drive level Fundamental mode Ratio used because typical R1 values are much less than the maximum spec No external series resistor assumed Comments Parallel resonance, fundamental mode, AT cut Min 8.00 – – 3 – 300 – – 180 14.4 Typ – 14 – – 0.5 – – – – 18 Max 30.00 – 25 – 2 – –150 7 250 21.6 fF mW ppm ppm pF Unit MHz pF  Third overtone separation from 3*FNOM High side Third overtone separation from 3*FNOM Low side Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance Operating Conditions Parameter VDDC VDDA, VDDB TA CL CIN CXIN tPU 3.3 V Supply Voltage 2.5 V Supply Voltage Range 3.3 V Supply Voltage Range Ambient Operating Temperature, Commercial Ambient Operating Temperature, Industrial Output Load Capacitance (Fout < 100 MHz) Output Load Capacitance (Fout > 100 MHz) Input Capacitance (except XIN) Crystal Input Capacitance (all internal caps off) Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min 3.135 2.375 3.135 0 –40 – – – 10 0.05 Max 3.465 2.625 3.465 70 85 30 15 7 13 500 Unit V V V °C °C pF pF pF pF ms Note 5. Ecliptek crystals ECX-5788-13.500M, ECX-5807-19.440M, ECX-5872-19.53125M, ECX-6362-18.432M, ECX-5808-27.000M, ECX-5884-17.664M, ECX-5883-16.384M, ECX-5882-19.200M, ECX-5880-24.576M meet these specifications. Document Number: 38-07518 Rev. *F Page 10 of 15 [+] Feedback CY23FS08 DC Electrical Characteristics Parameter VIL VIH IIL IIH IOL IOH IDDQ Description Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current Output High Current Quiescent Current Test Conditions CMOS Levels, 30% of VDD CMOS Levels, 70% of VDD VIN = VSS (100k pull up only) VIN = VDD (100k pull down only) VOL = 0.5 V, VDD = 2.5 V VOL = 0.5 V, VDD = 3.3 V VOH = VDD – 0.5 V, VDD = 2.5 V VOH = VDD – 0.5 V, VDD = 3.3 V All Inputs grounded, PLL and DCXO in bypass mode, Reference Input = 0 Min – 0.7×VDD – – – – – – – Typ – – – – 18 20 18 20 – Max 0.3×VDD – 50 50 – – – – 250 Unit V V µA µA mA mA mA mA µA Switching Characteristics Parameter[7] fREF fOUT fXIN tDC tSR(I) tSR(O) tSK(O) tSK(IB) tSK(PP) t()[6] tD()[6] tJ(CC) tLOCK Description Reference Frequency Output Frequency DCXO Frequency Duty Cycle Input Slew Rate Output Slew Rate Output to Output Skew Intrabank Skew Part to Part Skew Static Phase Offset Dynamic Phase Offset Cycle-to-Cycle Jitter Lock Time Measured at VDD/2 Measured on REF1 Input, 30% to 70% of VDD Measured from 20% to 80% of VDD = 3.3V, 15 pF Load Measured from 20% to 80% of VDD =2.5V, 15 pF Load All outputs equally loaded, measured at VDD/2 All outputs equally loaded, measured at VDD/2 Measured at VDD/2 Measured at VDD/2 Measured at VDD/2 Load = 15 pF, fOUT 6.25 MHz At room temperature with 18.432 MHz Crystal Industrial Grade 15 pF Load, Commercial Grade 15 pF Load, Industrial Grade Test Conditions Commercial Grade Min 1.04 1.04 1.70 1.70 8.0 47 0.5 0.8 0.4 – – – – – – – – Typ – – – – – – – – – 110 – – – – 100 18 70 Max 200 166.7 200 166.7 30 53 4.0 4.0 3.0 200 75 500 250 500 200 35 – Unit MHz MHz MHz MHz MHz % V/ns V/ns V/ns ps ps ps ps ps ps psRMS ms Ordering Information Part Number Pb-free CY23FS08OXI CY23FS08OXIT CY23FS08OXC CY23FS08OXCT 28-pin SSOP 28-pin SSOP – Tape and Reel 28-pin SSOP 28-pin SSOP – Tape and Reel Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Package Type Product Flow Notes 6. The t() reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as tSR(I) is maintained. 7. Parameters guaranteed by design and characterization, not 100% tested in production. Document Number: 38-07518 Rev. *F Page 11 of 15 [+] Feedback CY23FS08 Ordering Code Definition CY23FS08 OX X (T) Package type: T = tape and reel, blank = tube Temperature code: C = Commercial, I = Industrial Package: 28-pin SSOP, Pb-free Device number Package Diagram Figure 14. 28-pin (5.3 mm) Shrunk Small Outline Package SP28 51-85079 *D Document Number: 38-07518 Rev. *F Page 12 of 15 [+] Feedback CY23FS08 Acronyms Acronym DCXO ESD PLL RMS SSOP XTAL Description digitally controlled crystal oscillator electrostatic discharge phase locked loop root mean square shrunk small outline package crystal Document Conventions Units of Measure Symbol Unit of Measure degree Celsius micro Amperes milli Amperes milli seconds Mega Hertz nano seconds pico Farad pico seconds parts per million Watts ohms Volts C µA mA ms MHz ns pF ps ppm W  V Document Number: 38-07518 Rev. *F Page 13 of 15 [+] Feedback CY23FS08 Document History Page Document Title: CY23FS08 Failsafe™ 2.5 V/3.3 V Zero Delay Buffer Document Number: 38-07518 Rev. ** *A *B *C *D ECN No. 123699 224067 276749 417645 2865396 Submission Date 04/23/03 See ECN See ECN See ECN 01/25/2010 Orig. of Change RGL RGL RGL KVM New Data Sheet Removed (TLOCK) Lock Time Specification. Added Lead-free devices Added typical nos. on jitters Remove figures showing dynamic response to 180° phase change to REF Add waveforms for input slew rate and intrabank skew Change “Cl” to “CLOAD” Absolute Maximum Conditions table: remove duplicate TA parameter Replace crystal ECX–5806–18.432M with ECX–6362–18.432M Remove obsolete part numbers CY23FS08OI, CY23FS08OIT, CY23FS08OC and CY23FS08OCT Replace “Lead-free” with “Pb-free” Remove unreferenced footnote 9 Change package drawing title from “O28” to “SP28”, updated package diagram Added Table of Contents Posting to external web. Changed tD() max value from 200 to 500 and removed tD() Typical value in Switching Characteristics on page 11. Added Ordering Code Definition. Added Acronyms and Units of Measure on page 13. Description of Change RGL/ZJX Changed the XTAL Specifications table. *E *F 2925613 3130032 04/30/10 01/06/2011 KVM BASH Document Number: 38-07518 Rev. *F Page 14 of 15 [+] Feedback CY23FS08 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2003-2011. 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Document Number: 38-07518 Rev. *F Revised January 7, 2011 Page 15 of 15 FailSafe is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback