CY23S08
3.3V Zero Delay Buffer
Features
■ ■ ■
Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations, see Table 3 on page 3 Multiple low-skew outputs ❐ 45 ps typical output-output skew(–1) ❐ Two banks of four outputs, three-stateable by two select inputs 10 MHz to 133 MHz operating range 65 ps typical cycle-cycle jitter (–1, –1H) Advanced 0.65μ CMOS technology Space saving 16-pin 150-mil SOIC/TSSOP packages 3.3V operation Spread Aware™
The CY23S08 has two banks of four outputs each, which can be controlled by the Select inputs as shown in Table 2 on page 3. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The CY23S08 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 50 μA of current draw. The PLL shuts down in two additional cases as shown in Table 2 on page 3. Multiple CY23S08 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY23S08 is available in five different configurations, as shown in Table 3 on page 3. The CY23S08–1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The CY23S08–1H is the high-drive version of the –1, and rise and fall times on this device are much faster. The CY23S08–2 enables the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The CY23S08–2H is the high-drive version of the –2, and rise and fall times on this device are much faster. The CY23S08–3 enables the user to obtain 4X and 2X frequencies on the outputs. The CY23S08–4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications.
■ ■ ■ ■ ■ ■
Functional Description
The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 250 ps.
Logic Block Diagram
/2
REF
PLL
MUX
FBK CLKA1 CLKA2 CLKA3
Extra Divider (–3, –4)
S2 S1
CLKA4
Select Input Decoding
/2
CLKB1 CLKB2 CLKB3
Extra Divider (–2, –2H, –3)
CLKB4
Cypress Semiconductor Corporation Document #: 38-07265 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709 • 408-943-2600 Revised September 05, 2007
[+] Feedback
CY23S08
Pinouts
Figure 1. Pin Diagram - 16 Pin SOIC Package Top View
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
1 2 3 4 5 6 7 8 16 15 14
SOIC
13 12 11 10 9
FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
Table 1. Pin Definition - 16 Pin SOIC Package Pin Signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF[2] CLKA1[3] CLKA2[3] VDD GND CLKB1[3] CLKB2[3] S2[4] S1[4] CLKB3[3] CLKB4[3] GND VDD CLKA3[3] CLKA4[3] FBK Clock output, Bank A Clock output, Bank A 3.3V supply Ground Clock output, Bank B Clock output, Bank B Select input, bit 2 Select input, bit 1 Clock output, Bank B Clock output, Bank B Ground 3.3V supply Clock output, Bank A Clock output, Bank A PLL feedback input
Description
Input reference frequency, 5V tolerant input
Notes 1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2. 2. Weak pull down. 3. Weak pull down on all outputs. 4. Weak pull ups on these inputs.
Document #: 38-07265 Rev. *G
Page 2 of 10
[+] Feedback
CY23S08
Table 2. Select Input Decoding S2 0 0 1 1 S1 0 1 0 1 CLOCK A1–A4 Three-State Driven Driven Driven CLOCK B1–B4 Three-State Three-State Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown Y N Y N
Table 3. Available CY23S08 Configurations Device CY23S08–1 CY23S08–1H CY23S08–2 CY23S08–2H CY23S08–2 CY23S08–2H CY23S08–3 CY23S08–3 CY23S08–4 Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank A Bank B Bank B Bank A Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference Reference 2 X Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Bank B Frequency Reference Reference Reference/2 Reference/2 Reference Reference Reference or Reference[1] 2 X Reference 2 X Reference
Spread Aware
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see Cypress’s application note EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.
Document #: 38-07265 Rev. *G
Page 3 of 10
[+] Feedback
CY23S08
Maximum Ratings
Supply Voltage to Ground Potential................–0.5V to +7.0V DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V DC Input Voltage REF ........................................... –0.5 to 7V Storage Temperature ................................. –65°C to +150°C Max. Soldering Temperature (10 sec.) ....................... 260°C Junction Temperature ................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions for CY23S08SC-XX Commercial Temperature Devices
Parameter[5] VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance[6] Description Min 3.0 0 — — — Max 3.6 70 30 15 7 Unit V °C pF pF pF
Electrical Characteristics for CY23S08SC-XX Commercial Temperature Devices
Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[7] Output HIGH Voltage[7] VIN = 0V VIN = VDD IOL = 8 mA (–1, –2, –3, –4) IOL = 12 mA (-1H, -2H) IOH = –8 mA (–1, –2, –3, –4) IOH = –12 mA (–1H, –2H) Unloaded outputs, 100-MHz REF, Select inputs at VDD or GND Unloaded outputs, 66-MHz REF (–1,–2,–3,–4) Unloaded outputs, 33-MHz REF (–1,–2,–3,–4) Test Conditions Min — 2.0 — — — 2.4 — — — — — Max 0.8 — 50.0 100.0 0.4 — 12.0 45.0 70.0 (–1H, –2H) 32.0 18.0 Unit V V μA μA V V μA mA mA mA mA
Power down Supply Current REF = 0 MHz Supply Current
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices
Parameter[8] t1 t1 t1 t1 t1 Name Output Frequency Output Frequency Output Frequency Output Frequency Output Frequency Duty = t2 ÷ t1 (–1,–2,–3,–4,–1H, -2H) Cycle[7] Duty Cycle[7] = t2 ÷ t1 (–1,–2,–3,–4,–1H, -2H) Test Conditions 30-pF load, –1, –1H, –2, –3 devices 30-pF load, –4 devices 20-pF load, –1H device 15-pF load, –1, –2, –3, devices 15-pF load, –4 devices Measured at VDD/2, FOUT = 66.66 MHz 30-pF load Measured at VDD/2, FOUT
