CY2410

CY2410 MPEG Clock Generator with VCXO MPEG Clock Generator with VCXO Features ■ ■ ■ ■ ■ Benefits ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Integrated phase-locked loop (PLL) Low-jitter, high-accuracy outputs VCXO with analog adjust 3.3 V operation Compatible with MK3727 (–1, –5) Highest-performance PLL tailored for multimedia applications Meets critical timing requirements in complex system designs Large ±150-ppm range, better linearity Application compatibility for a wide variety of designs Enables design compatibility Advanced Features Matches nonlinear MK3727A VCXO control curve (-5) Digital VCXO control Electromagnetic interference (EMI) reduction for standards compliance Second source for existing designs VCXO Control Curve Part Number Outputs CY2410-1 CY2410-5 1 1 Input Frequency Range 13.5-MHz pullable crystal input per Cypress specification 13.5-MHz pullable crystal input per Cypress specification Output Frequencies Other Features Compatible with MK3727 Matches MK3727A nonlinear VCXO Control Curve 1 copy of 27 MHz linear 1 copy of 27 MHz nonlinear CY2410-1, -5 Logic Block Diagram 13.5 XIN XOUT OSC Q  VCO P OUTPUT DIVIDERS 27 MHz VCXO PLL VDD VSS Cypress Semiconductor Corporation Document #: 38-07317 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 16, 2011 [+] Feedback CY2410 CY2410-3 Logic Block Diagram 13.5 XIN XOUT OSC Q  VCO P OUTPUT DIVIDERS 27 MHz PLL Digital VCXO Serial Programming Interface SCLK SDAT VDD VSS Document #: 38-07317 Rev. *G Page 2 of 13 [+] Feedback CY2410 Contents Pin Configuration ............................................................. 4 Pin Definitions for CY2410-1, CY2410-5 ......................... 4 Pullable Crystal Specifications ....................................... 5 Absolute Maximum Conditions ....................................... 7 Recommended Operating Conditions ............................ 7 DC Electrical Specifications ............................................ 7 AC Electrical Specifications (VDD = 3.3 V) ..................... 7 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagram ............................................................ 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Document #: 38-07317 Rev. *G Page 3 of 13 [+] Feedback CY2410 Pin Configuration Figure 1. CY2410-1, CY2410-5 8-pin SOIC XIN VDD VCXO VSS 1 2 3 4 8 7 6 5 XOUT NC or VSS NC or VDD 27 MHz Pin Definitions for CY2410-1, CY2410-5 Name XIN VDD VCXO VSS 27 MHz NC/VDD NC/VSS XOUT[1] 1 2 3 4 5 6 7 8 Pin Number Reference crystal input Voltage supply Input analog control for VCXO Ground 27-MHz clock output No Connect or voltage supply No Connect or ground Reference crystal output Description Note 1. Float XOUT if XIN is externally driven. Document #: 38-07317 Rev. *G Page 4 of 13 [+] Feedback CY2410 Pullable Crystal Specifications Parameter [2] FNOM CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Fundamental mode Condition Parallel resonance, fundamental mode, AT cut Min – – – 3 Typ 13.5 14 – – Max – – 25 – Unit MHz pF  Ratio of third overtone mode ESR Ratio used because typical R1 values to fundamental mode ESR are much less than the maximum spec. Crystal drive level Third overtone separation from 3 × FNOM Third overtone separation from 3 × FNOM Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance No external series resistor assumed High side Low side – 300 – – 180 14.4 0.5 – – – – 18 2.0 – –150 7 250 21.6 mW ppm ppm pF pF Note 2. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M, Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL, PDI HA13500XFSA14XC. Document #: 38-07317 Rev. *G Page 5 of 13 [+] Feedback CY2410 Figure 2. Data Valid and Data Transition Periods Data Valid SDAT Transition to next bit tDH SCLK VIH VIL CLKHIGH tSU CLKLOW Figure 3. Start and Stop Frame SDAT SCLK START Transition to next bit STOP Figure 4. Duty Cycle Definition; DC = t2/t1 t1 t2 CLK 50% 50% Figure 5. Rise and Fall Time Definitions: ER = 0.6 × VDD / t3, EF = 0.6 × VDD / t4 t3 80% CLK 20% t4 Document #: 38-07317 Rev. *G Page 6 of 13 [+] Feedback CY2410 Absolute Maximum Conditions Parameter VDD TS TJ Supply Voltage Storage Temperature Junction Temperature Digital Inputs Digital Outputs referred to VDD Electrostatic Discharge [3] Description Min –0.5 –65 – VSS – 0.3 VSS – 0.3 2000 Max 7.0 125 125 VDD + 0.3 VDD + 0.3 – Unit V °C °C V V V Recommended Operating Conditions Parameter VDD TA CLOAD fREF tPU Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency Power up time for VDD to reach minimum specified voltage (power ramp must be monotonic) Description Min 3.135 0 – – 0.05 Typ 3.3 – – 13.5 – Max 3.465 70 15 – 500 Unit V °C pF MHz ms DC Electrical Specifications Parameter IOH IOL CIN IIZ fXO VVCXO IVDD Name Output HIGH Current: -1, -5 Output LOW Current: -1, -5 Input Capacitance Input Leakage Current VCXO pullability range: -1, -5 VCXO input range Supply Current Description VOH = VDD – 0.5, VDD = 3.3 V VOL = 0.5, VDD = 3.3 V Min 12 12 – – +150 0 – Typ 24 24 – 5 – – 30 Max – – 7 – – VDD 35 Unit mA mA pF A ppm V mA AC Electrical Specifications (VDD = 3.3 V) Parameter[4] DC EROR Name Output Duty Cycle Rising Edge Rate: -1, -5 Description Duty Cycle is defined in Figure 4 on page 6, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 5 on page 6. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 5 on page 6. Peak-to-peak period jitter Min 45 0.8 Typ 50 1.4 Max 55 – Unit % V/ns EROF Falling Edge Rate: -1, -5 0.8 1.4 – V/ns t9 t10 Clock Jitter: -1, -5 PLL Lock Time – – 140 – – 3 ps ms Notes 3. Rated for ten years. 4. Not 100% tested. Document #: 38-07317 Rev. *G Page 7 of 13 [+] Feedback CY2410 Figure 6. Test and Measurement Setup VDD 0.1 F OUTPUTS CLK out CLOAD GND Document #: 38-07317 Rev. *G Page 8 of 13 [+] Feedback CY2410 Ordering Information Ordering Code Pb-free CY2410KSXC–5 CY2410KSXC–5T 8-pin SOIC Commercial 3.3 V 3.3 V Matches nonlinear MK3727A VCXO control curve Matches nonlinear MK3727A VCXO control curve 8-pin SOIC - Tape and Reel Commercial Package Type Operating Range Operating Voltage Features Ordering Code Definitions CY2410K S X C 5 T Tape and Reel Configuration Type Temperature Range: C = Commercial Pb-free Package Type: S = 8-pin SOIC Base Part Number Document #: 38-07317 Rev. *G Page 9 of 13 [+] Feedback CY2410 Package Diagram Figure 7. 8-pin SOIC (150 Mils), 51-85066 51-85066 *E Document #: 38-07317 Rev. *G Page 10 of 13 [+] Feedback CY2410 Acronyms Acronym PLL EMI ESD ESR PLL SOIC VCXO phase-locked loop electromagnetic interference electrostatic discharge equivalent series resistance phase locked loop small outline integrated circuit voltage controlled crystal oscillator Description Document Conventions Units of Measure Symbol C MHz F mA ms mW  ppm % pF ps V degree Celsius Mega Hertz micro Farad milli Amperes milli seconds milli Watts ohms parts per million percent pico Farad pico seconds Volts Unit of Measure Document #: 38-07317 Rev. *G Page 11 of 13 [+] Feedback CY2410 Document History Page Document Title: CY2410, MPEG Clock Generator with VCXO Document Number: 38-07317 REV. ** *A *B *C ECN NO. 111553 114937 121418 126905 Submission Date 02/12/02 09/24/02 12/06/02 06/17/03 Orig. of Change CKN CKN CKN RGL New Data Sheet Added -6 to data sheet, Advance Information to Final Updated the Pullable Crystal Specifications table on page 2 Added -7 part to data sheet Added new parameter on the Pullable Crystal table Power up requirements added to the operating conditions Added VCXO -7 pullability range in the DC Specs with min. value of ±115 ppm Updated template. Added Note “Not recommended for new designs.” Added part number CY2410SXC-1, CY2410SXC-1T, CY2410SXC-5, CY2410SXC-5T, CY2410KSXC-5, and CY2410KSXC-5T in ordering information table. Removed all part numbers for non-Pb-free packages (part numbers beginning CY2410SC). Removed details specific to the -3, -4, -6 and -7 versions. Updated ordering information table. Removed part numbers CY2410SXC-1, CY2410SXC-1T, CY2410SXC-5T, and CY2410SXC-5 Updated package diagram. Updated copyright section. Added Ordering Code Definitions. Updated Package Diagram. Updated Acronyms and Units of Measure. Updated in new template. Description of Change *D *E 131100 2440886 01/20/03 See ECN RGL AESA *F 2897373 03/22/10 CXQ *G 3317009 07/16/2011 BASH Document #: 38-07317 Rev. *G Page 12 of 13 [+] Feedback CY2410 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07317 Rev. *G Revised July 16, 2011 Page 13 of 13 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback